Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8216075 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
262 |
| auto[1] |
6094979 |
1 |
|
|
T26 |
402 |
|
T1 |
763 |
|
T11 |
329 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11796421 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
520 |
| auto[1] |
2514633 |
1 |
|
|
T26 |
144 |
|
T1 |
167 |
|
T11 |
111 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8229883 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
286 |
| auto[1] |
6081171 |
1 |
|
|
T26 |
378 |
|
T1 |
555 |
|
T11 |
244 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1770978 |
1 |
|
|
T26 |
93 |
|
T1 |
152 |
|
T11 |
31 |
| auto[1] |
auto[0] |
auto[1] |
1257736 |
1 |
|
|
T26 |
55 |
|
T1 |
97 |
|
T11 |
21 |
| auto[1] |
auto[1] |
auto[0] |
1795560 |
1 |
|
|
T26 |
141 |
|
T1 |
236 |
|
T11 |
102 |
| auto[1] |
auto[1] |
auto[1] |
1256897 |
1 |
|
|
T26 |
89 |
|
T1 |
70 |
|
T11 |
90 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |