Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8217169 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
282 |
| auto[1] |
6093885 |
1 |
|
|
T26 |
382 |
|
T1 |
863 |
|
T11 |
163 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11799834 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
621 |
| auto[1] |
2511220 |
1 |
|
|
T26 |
43 |
|
T1 |
257 |
|
T11 |
127 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8241706 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
334 |
| auto[1] |
6069348 |
1 |
|
|
T26 |
330 |
|
T1 |
895 |
|
T11 |
279 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1766959 |
1 |
|
|
T26 |
80 |
|
T1 |
302 |
|
T11 |
121 |
| auto[1] |
auto[0] |
auto[1] |
1254179 |
1 |
|
|
T26 |
15 |
|
T1 |
93 |
|
T11 |
92 |
| auto[1] |
auto[1] |
auto[0] |
1791169 |
1 |
|
|
T26 |
207 |
|
T1 |
336 |
|
T11 |
31 |
| auto[1] |
auto[1] |
auto[1] |
1257041 |
1 |
|
|
T26 |
28 |
|
T1 |
164 |
|
T11 |
35 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |