Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8216597 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
366 |
| auto[1] |
6094457 |
1 |
|
|
T26 |
298 |
|
T1 |
664 |
|
T11 |
190 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11797120 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
567 |
| auto[1] |
2513934 |
1 |
|
|
T26 |
97 |
|
T1 |
124 |
|
T11 |
87 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8226348 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
302 |
| auto[1] |
6084706 |
1 |
|
|
T26 |
362 |
|
T1 |
629 |
|
T11 |
224 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1790481 |
1 |
|
|
T26 |
126 |
|
T1 |
272 |
|
T11 |
63 |
| auto[1] |
auto[0] |
auto[1] |
1259592 |
1 |
|
|
T26 |
56 |
|
T1 |
64 |
|
T11 |
35 |
| auto[1] |
auto[1] |
auto[0] |
1780291 |
1 |
|
|
T26 |
139 |
|
T1 |
233 |
|
T11 |
74 |
| auto[1] |
auto[1] |
auto[1] |
1254342 |
1 |
|
|
T26 |
41 |
|
T1 |
60 |
|
T11 |
52 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |