Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8252384 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
431 |
| auto[1] |
6058670 |
1 |
|
|
T26 |
233 |
|
T1 |
604 |
|
T11 |
390 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11804643 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
560 |
| auto[1] |
2506411 |
1 |
|
|
T26 |
104 |
|
T1 |
162 |
|
T11 |
89 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8250002 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
318 |
| auto[1] |
6061052 |
1 |
|
|
T26 |
346 |
|
T1 |
793 |
|
T11 |
187 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1782010 |
1 |
|
|
T26 |
160 |
|
T1 |
403 |
|
T11 |
18 |
| auto[1] |
auto[0] |
auto[1] |
1254013 |
1 |
|
|
T26 |
72 |
|
T1 |
101 |
|
T11 |
13 |
| auto[1] |
auto[1] |
auto[0] |
1772631 |
1 |
|
|
T26 |
82 |
|
T1 |
228 |
|
T11 |
80 |
| auto[1] |
auto[1] |
auto[1] |
1252398 |
1 |
|
|
T26 |
32 |
|
T1 |
61 |
|
T11 |
76 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |