Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8220484 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
398 |
| auto[1] |
6090570 |
1 |
|
|
T26 |
266 |
|
T1 |
758 |
|
T11 |
158 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11796978 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
613 |
| auto[1] |
2514076 |
1 |
|
|
T26 |
51 |
|
T1 |
72 |
|
T11 |
117 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8225920 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
430 |
| auto[1] |
6085134 |
1 |
|
|
T26 |
234 |
|
T1 |
621 |
|
T11 |
245 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1791724 |
1 |
|
|
T26 |
121 |
|
T1 |
345 |
|
T11 |
72 |
| auto[1] |
auto[0] |
auto[1] |
1261003 |
1 |
|
|
T26 |
48 |
|
T1 |
39 |
|
T11 |
74 |
| auto[1] |
auto[1] |
auto[0] |
1779334 |
1 |
|
|
T26 |
62 |
|
T1 |
204 |
|
T11 |
56 |
| auto[1] |
auto[1] |
auto[1] |
1253073 |
1 |
|
|
T26 |
3 |
|
T1 |
33 |
|
T11 |
43 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |