Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8242432 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
296 |
| auto[1] |
6068622 |
1 |
|
|
T26 |
368 |
|
T1 |
704 |
|
T11 |
283 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11799839 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
571 |
| auto[1] |
2511215 |
1 |
|
|
T26 |
93 |
|
T1 |
98 |
|
T11 |
128 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8224104 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
312 |
| auto[1] |
6086950 |
1 |
|
|
T26 |
352 |
|
T1 |
638 |
|
T11 |
281 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1795013 |
1 |
|
|
T26 |
135 |
|
T1 |
316 |
|
T11 |
71 |
| auto[1] |
auto[0] |
auto[1] |
1260721 |
1 |
|
|
T26 |
35 |
|
T1 |
62 |
|
T11 |
68 |
| auto[1] |
auto[1] |
auto[0] |
1780722 |
1 |
|
|
T26 |
124 |
|
T1 |
224 |
|
T11 |
82 |
| auto[1] |
auto[1] |
auto[1] |
1250494 |
1 |
|
|
T26 |
58 |
|
T1 |
36 |
|
T11 |
60 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |