Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8239708 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
319 |
| auto[1] |
6071346 |
1 |
|
|
T26 |
345 |
|
T1 |
684 |
|
T11 |
203 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13537158 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
650 |
| auto[1] |
773896 |
1 |
|
|
T26 |
14 |
|
T1 |
42 |
|
T11 |
52 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8244558 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
354 |
| auto[1] |
6066496 |
1 |
|
|
T26 |
310 |
|
T1 |
892 |
|
T11 |
242 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2660576 |
1 |
|
|
T26 |
138 |
|
T1 |
461 |
|
T11 |
108 |
| auto[1] |
auto[0] |
auto[1] |
389483 |
1 |
|
|
T26 |
7 |
|
T1 |
20 |
|
T11 |
35 |
| auto[1] |
auto[1] |
auto[0] |
2632024 |
1 |
|
|
T26 |
158 |
|
T1 |
389 |
|
T11 |
82 |
| auto[1] |
auto[1] |
auto[1] |
384413 |
1 |
|
|
T26 |
7 |
|
T1 |
22 |
|
T11 |
17 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |