Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8217815 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
444 |
| auto[1] |
6093239 |
1 |
|
|
T26 |
220 |
|
T1 |
935 |
|
T11 |
216 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11798843 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
605 |
| auto[1] |
2512211 |
1 |
|
|
T26 |
59 |
|
T1 |
133 |
|
T11 |
117 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8234507 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
421 |
| auto[1] |
6076547 |
1 |
|
|
T26 |
243 |
|
T1 |
629 |
|
T11 |
242 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1785491 |
1 |
|
|
T26 |
105 |
|
T1 |
200 |
|
T11 |
76 |
| auto[1] |
auto[0] |
auto[1] |
1255601 |
1 |
|
|
T26 |
40 |
|
T1 |
43 |
|
T11 |
87 |
| auto[1] |
auto[1] |
auto[0] |
1778845 |
1 |
|
|
T26 |
79 |
|
T1 |
296 |
|
T11 |
49 |
| auto[1] |
auto[1] |
auto[1] |
1256610 |
1 |
|
|
T26 |
19 |
|
T1 |
90 |
|
T11 |
30 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |