Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8275535 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
327 |
| auto[1] |
6035519 |
1 |
|
|
T26 |
337 |
|
T1 |
864 |
|
T11 |
256 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11786114 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
534 |
| auto[1] |
2524940 |
1 |
|
|
T26 |
130 |
|
T1 |
171 |
|
T11 |
120 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8211301 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
333 |
| auto[1] |
6099753 |
1 |
|
|
T26 |
331 |
|
T1 |
563 |
|
T11 |
265 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1797370 |
1 |
|
|
T26 |
82 |
|
T1 |
182 |
|
T11 |
48 |
| auto[1] |
auto[0] |
auto[1] |
1271586 |
1 |
|
|
T26 |
69 |
|
T1 |
61 |
|
T11 |
33 |
| auto[1] |
auto[1] |
auto[0] |
1777443 |
1 |
|
|
T26 |
119 |
|
T1 |
210 |
|
T11 |
97 |
| auto[1] |
auto[1] |
auto[1] |
1253354 |
1 |
|
|
T26 |
61 |
|
T1 |
110 |
|
T11 |
87 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |