Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8214622 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
346 |
| auto[1] |
6096432 |
1 |
|
|
T26 |
318 |
|
T1 |
748 |
|
T11 |
272 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11789448 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
591 |
| auto[1] |
2521606 |
1 |
|
|
T26 |
73 |
|
T1 |
148 |
|
T11 |
123 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8218204 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
354 |
| auto[1] |
6092850 |
1 |
|
|
T26 |
310 |
|
T1 |
746 |
|
T11 |
235 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1763157 |
1 |
|
|
T26 |
119 |
|
T1 |
264 |
|
T11 |
39 |
| auto[1] |
auto[0] |
auto[1] |
1257487 |
1 |
|
|
T26 |
49 |
|
T1 |
76 |
|
T11 |
29 |
| auto[1] |
auto[1] |
auto[0] |
1808087 |
1 |
|
|
T26 |
118 |
|
T1 |
334 |
|
T11 |
73 |
| auto[1] |
auto[1] |
auto[1] |
1264119 |
1 |
|
|
T26 |
24 |
|
T1 |
72 |
|
T11 |
94 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |