Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8184642 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
459 |
| auto[1] |
6126412 |
1 |
|
|
T26 |
205 |
|
T1 |
762 |
|
T11 |
228 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13532285 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
655 |
| auto[1] |
778769 |
1 |
|
|
T26 |
9 |
|
T1 |
27 |
|
T11 |
39 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8215227 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
393 |
| auto[1] |
6095827 |
1 |
|
|
T26 |
271 |
|
T1 |
770 |
|
T11 |
158 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2635859 |
1 |
|
|
T26 |
168 |
|
T1 |
363 |
|
T11 |
76 |
| auto[1] |
auto[0] |
auto[1] |
384821 |
1 |
|
|
T26 |
6 |
|
T1 |
18 |
|
T11 |
27 |
| auto[1] |
auto[1] |
auto[0] |
2681199 |
1 |
|
|
T26 |
94 |
|
T1 |
380 |
|
T11 |
43 |
| auto[1] |
auto[1] |
auto[1] |
393948 |
1 |
|
|
T26 |
3 |
|
T1 |
9 |
|
T11 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |