Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8221874 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
275 |
| auto[1] |
6089180 |
1 |
|
|
T26 |
389 |
|
T1 |
966 |
|
T11 |
231 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13536579 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
654 |
| auto[1] |
774475 |
1 |
|
|
T26 |
10 |
|
T1 |
20 |
|
T11 |
34 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8245327 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
412 |
| auto[1] |
6065727 |
1 |
|
|
T26 |
252 |
|
T1 |
538 |
|
T11 |
189 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2647929 |
1 |
|
|
T26 |
106 |
|
T1 |
217 |
|
T11 |
72 |
| auto[1] |
auto[0] |
auto[1] |
388376 |
1 |
|
|
T26 |
4 |
|
T1 |
7 |
|
T11 |
15 |
| auto[1] |
auto[1] |
auto[0] |
2643323 |
1 |
|
|
T26 |
136 |
|
T1 |
301 |
|
T11 |
83 |
| auto[1] |
auto[1] |
auto[1] |
386099 |
1 |
|
|
T26 |
6 |
|
T1 |
13 |
|
T11 |
19 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |