Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8205551 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
360 |
| auto[1] |
6105503 |
1 |
|
|
T26 |
304 |
|
T1 |
714 |
|
T11 |
193 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13530457 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
653 |
| auto[1] |
780597 |
1 |
|
|
T26 |
11 |
|
T1 |
23 |
|
T11 |
34 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8214977 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
362 |
| auto[1] |
6096077 |
1 |
|
|
T26 |
302 |
|
T1 |
718 |
|
T11 |
178 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2649568 |
1 |
|
|
T26 |
123 |
|
T1 |
307 |
|
T11 |
65 |
| auto[1] |
auto[0] |
auto[1] |
388383 |
1 |
|
|
T26 |
7 |
|
T1 |
7 |
|
T11 |
20 |
| auto[1] |
auto[1] |
auto[0] |
2665912 |
1 |
|
|
T26 |
168 |
|
T1 |
388 |
|
T11 |
79 |
| auto[1] |
auto[1] |
auto[1] |
392214 |
1 |
|
|
T26 |
4 |
|
T1 |
16 |
|
T11 |
14 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |