Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8225852 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
370 |
| auto[1] |
6085202 |
1 |
|
|
T26 |
294 |
|
T1 |
711 |
|
T11 |
197 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13534064 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
656 |
| auto[1] |
776990 |
1 |
|
|
T26 |
8 |
|
T1 |
42 |
|
T11 |
34 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8232980 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
342 |
| auto[1] |
6078074 |
1 |
|
|
T26 |
322 |
|
T1 |
992 |
|
T11 |
212 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2668749 |
1 |
|
|
T26 |
169 |
|
T1 |
533 |
|
T11 |
119 |
| auto[1] |
auto[0] |
auto[1] |
390518 |
1 |
|
|
T26 |
2 |
|
T1 |
26 |
|
T11 |
25 |
| auto[1] |
auto[1] |
auto[0] |
2632335 |
1 |
|
|
T26 |
145 |
|
T1 |
417 |
|
T11 |
59 |
| auto[1] |
auto[1] |
auto[1] |
386472 |
1 |
|
|
T26 |
6 |
|
T1 |
16 |
|
T11 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |