Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8245778 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
421 |
| auto[1] |
6065276 |
1 |
|
|
T26 |
243 |
|
T1 |
735 |
|
T11 |
324 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13536652 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
655 |
| auto[1] |
774402 |
1 |
|
|
T26 |
9 |
|
T1 |
24 |
|
T11 |
74 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8244241 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
401 |
| auto[1] |
6066813 |
1 |
|
|
T26 |
263 |
|
T1 |
652 |
|
T11 |
381 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2653391 |
1 |
|
|
T26 |
181 |
|
T1 |
344 |
|
T11 |
101 |
| auto[1] |
auto[0] |
auto[1] |
388795 |
1 |
|
|
T26 |
6 |
|
T1 |
14 |
|
T11 |
22 |
| auto[1] |
auto[1] |
auto[0] |
2639020 |
1 |
|
|
T26 |
73 |
|
T1 |
284 |
|
T11 |
206 |
| auto[1] |
auto[1] |
auto[1] |
385607 |
1 |
|
|
T26 |
3 |
|
T1 |
10 |
|
T11 |
52 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |