Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8228415 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
266 |
| auto[1] |
6082639 |
1 |
|
|
T26 |
398 |
|
T1 |
853 |
|
T11 |
231 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13529402 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
654 |
| auto[1] |
781652 |
1 |
|
|
T26 |
10 |
|
T1 |
30 |
|
T11 |
59 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8205985 |
1 |
|
|
T24 |
774 |
|
T25 |
88 |
|
T26 |
371 |
| auto[1] |
6105069 |
1 |
|
|
T26 |
293 |
|
T1 |
849 |
|
T11 |
293 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2647349 |
1 |
|
|
T26 |
85 |
|
T1 |
335 |
|
T11 |
101 |
| auto[1] |
auto[0] |
auto[1] |
387654 |
1 |
|
|
T26 |
4 |
|
T1 |
13 |
|
T11 |
26 |
| auto[1] |
auto[1] |
auto[0] |
2676068 |
1 |
|
|
T26 |
198 |
|
T1 |
484 |
|
T11 |
133 |
| auto[1] |
auto[1] |
auto[1] |
393998 |
1 |
|
|
T26 |
6 |
|
T1 |
17 |
|
T11 |
33 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |