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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 947
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T768 /workspace/coverage/cover_reg_top/24.gpio_intr_test.3559024491 Aug 09 07:01:41 PM PDT 24 Aug 09 07:01:42 PM PDT 24 53310766 ps
T104 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.785458904 Aug 09 07:01:19 PM PDT 24 Aug 09 07:01:20 PM PDT 24 122862654 ps
T769 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3880566502 Aug 09 07:01:42 PM PDT 24 Aug 09 07:01:44 PM PDT 24 79790594 ps
T770 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3757657584 Aug 09 07:01:29 PM PDT 24 Aug 09 07:01:32 PM PDT 24 819888112 ps
T771 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2455811558 Aug 09 07:01:02 PM PDT 24 Aug 09 07:01:03 PM PDT 24 50747523 ps
T772 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.497170762 Aug 09 07:01:31 PM PDT 24 Aug 09 07:01:32 PM PDT 24 35599333 ps
T91 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1328628112 Aug 09 07:01:11 PM PDT 24 Aug 09 07:01:12 PM PDT 24 104320746 ps
T773 /workspace/coverage/cover_reg_top/41.gpio_intr_test.150341744 Aug 09 07:01:41 PM PDT 24 Aug 09 07:01:41 PM PDT 24 17193709 ps
T774 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.1363260509 Aug 09 07:01:39 PM PDT 24 Aug 09 07:01:40 PM PDT 24 26261755 ps
T775 /workspace/coverage/cover_reg_top/33.gpio_intr_test.3921443463 Aug 09 07:01:41 PM PDT 24 Aug 09 07:01:42 PM PDT 24 15263043 ps
T105 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1087126153 Aug 09 07:01:10 PM PDT 24 Aug 09 07:01:11 PM PDT 24 19227278 ps
T776 /workspace/coverage/cover_reg_top/47.gpio_intr_test.2578037109 Aug 09 07:01:37 PM PDT 24 Aug 09 07:01:38 PM PDT 24 12436157 ps
T777 /workspace/coverage/cover_reg_top/46.gpio_intr_test.1088508746 Aug 09 07:01:40 PM PDT 24 Aug 09 07:01:41 PM PDT 24 12256796 ps
T40 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.289688483 Aug 09 07:01:19 PM PDT 24 Aug 09 07:01:21 PM PDT 24 420807768 ps
T778 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1408813928 Aug 09 07:01:28 PM PDT 24 Aug 09 07:01:30 PM PDT 24 126362957 ps
T779 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3655195059 Aug 09 07:01:02 PM PDT 24 Aug 09 07:01:03 PM PDT 24 15363326 ps
T780 /workspace/coverage/cover_reg_top/11.gpio_intr_test.3293186248 Aug 09 07:01:19 PM PDT 24 Aug 09 07:01:20 PM PDT 24 63078510 ps
T781 /workspace/coverage/cover_reg_top/39.gpio_intr_test.114498202 Aug 09 07:01:40 PM PDT 24 Aug 09 07:01:41 PM PDT 24 93239689 ps
T782 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1333784032 Aug 09 07:01:19 PM PDT 24 Aug 09 07:01:21 PM PDT 24 245029052 ps
T92 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1371756858 Aug 09 07:01:19 PM PDT 24 Aug 09 07:01:20 PM PDT 24 29994065 ps
T783 /workspace/coverage/cover_reg_top/9.gpio_intr_test.1434077637 Aug 09 07:01:20 PM PDT 24 Aug 09 07:01:21 PM PDT 24 20093272 ps
T41 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3924131890 Aug 09 07:01:03 PM PDT 24 Aug 09 07:01:04 PM PDT 24 252986266 ps
T784 /workspace/coverage/cover_reg_top/37.gpio_intr_test.3519065683 Aug 09 07:01:43 PM PDT 24 Aug 09 07:01:43 PM PDT 24 17308586 ps
T785 /workspace/coverage/cover_reg_top/29.gpio_intr_test.3473785886 Aug 09 07:01:38 PM PDT 24 Aug 09 07:01:39 PM PDT 24 100515388 ps
T106 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.4185177830 Aug 09 07:01:11 PM PDT 24 Aug 09 07:01:12 PM PDT 24 22248862 ps
T786 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.503556758 Aug 09 07:01:41 PM PDT 24 Aug 09 07:01:42 PM PDT 24 14462407 ps
T787 /workspace/coverage/cover_reg_top/48.gpio_intr_test.953626667 Aug 09 07:01:38 PM PDT 24 Aug 09 07:01:38 PM PDT 24 34346875 ps
T788 /workspace/coverage/cover_reg_top/42.gpio_intr_test.1926921263 Aug 09 07:01:40 PM PDT 24 Aug 09 07:01:41 PM PDT 24 146418753 ps
T789 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2226880094 Aug 09 07:01:28 PM PDT 24 Aug 09 07:01:29 PM PDT 24 28202283 ps
T790 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3104104547 Aug 09 07:01:12 PM PDT 24 Aug 09 07:01:14 PM PDT 24 346888356 ps
T42 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2116972078 Aug 09 07:01:10 PM PDT 24 Aug 09 07:01:11 PM PDT 24 227088532 ps
T93 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1614727170 Aug 09 07:00:54 PM PDT 24 Aug 09 07:00:55 PM PDT 24 12599349 ps
T791 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.653897330 Aug 09 07:01:29 PM PDT 24 Aug 09 07:01:29 PM PDT 24 96903186 ps
T792 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3692169674 Aug 09 07:01:02 PM PDT 24 Aug 09 07:01:03 PM PDT 24 14375299 ps
T793 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.420673870 Aug 09 07:01:39 PM PDT 24 Aug 09 07:01:39 PM PDT 24 62604675 ps
T44 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2392231720 Aug 09 07:01:30 PM PDT 24 Aug 09 07:01:31 PM PDT 24 39508354 ps
T794 /workspace/coverage/cover_reg_top/32.gpio_intr_test.2233548892 Aug 09 07:01:41 PM PDT 24 Aug 09 07:01:42 PM PDT 24 15449588 ps
T795 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.975213109 Aug 09 07:01:02 PM PDT 24 Aug 09 07:01:05 PM PDT 24 220566135 ps
T796 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2839569062 Aug 09 07:01:19 PM PDT 24 Aug 09 07:01:21 PM PDT 24 30948897 ps
T797 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3737289981 Aug 09 07:01:19 PM PDT 24 Aug 09 07:01:20 PM PDT 24 42215368 ps
T798 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1581675699 Aug 09 07:01:12 PM PDT 24 Aug 09 07:01:13 PM PDT 24 13389787 ps
T96 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2587024111 Aug 09 07:01:01 PM PDT 24 Aug 09 07:01:02 PM PDT 24 24709581 ps
T799 /workspace/coverage/cover_reg_top/5.gpio_intr_test.2058890844 Aug 09 07:01:09 PM PDT 24 Aug 09 07:01:10 PM PDT 24 22882029 ps
T800 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.4236388102 Aug 09 07:01:38 PM PDT 24 Aug 09 07:01:38 PM PDT 24 26148929 ps
T801 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.173161241 Aug 09 07:01:12 PM PDT 24 Aug 09 07:01:13 PM PDT 24 137519101 ps
T802 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2611187454 Aug 09 07:01:38 PM PDT 24 Aug 09 07:01:39 PM PDT 24 41614712 ps
T803 /workspace/coverage/cover_reg_top/8.gpio_intr_test.1078976596 Aug 09 07:01:18 PM PDT 24 Aug 09 07:01:19 PM PDT 24 165606667 ps
T45 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3394171682 Aug 09 07:01:30 PM PDT 24 Aug 09 07:01:32 PM PDT 24 667042602 ps
T804 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.4206409360 Aug 09 07:01:19 PM PDT 24 Aug 09 07:01:20 PM PDT 24 153821481 ps
T805 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1154482884 Aug 09 07:01:31 PM PDT 24 Aug 09 07:01:33 PM PDT 24 31373242 ps
T806 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2941496723 Aug 09 07:01:03 PM PDT 24 Aug 09 07:01:04 PM PDT 24 72362654 ps
T807 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.4229291469 Aug 09 07:01:11 PM PDT 24 Aug 09 07:01:12 PM PDT 24 58574378 ps
T808 /workspace/coverage/cover_reg_top/22.gpio_intr_test.390716777 Aug 09 07:01:40 PM PDT 24 Aug 09 07:01:40 PM PDT 24 16865437 ps
T809 /workspace/coverage/cover_reg_top/15.gpio_intr_test.4165406132 Aug 09 07:01:28 PM PDT 24 Aug 09 07:01:29 PM PDT 24 12347464 ps
T810 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1545179394 Aug 09 07:01:29 PM PDT 24 Aug 09 07:01:30 PM PDT 24 19176181 ps
T110 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.335302461 Aug 09 07:01:10 PM PDT 24 Aug 09 07:01:11 PM PDT 24 75729598 ps
T111 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1517777500 Aug 09 07:01:19 PM PDT 24 Aug 09 07:01:20 PM PDT 24 44006049 ps
T811 /workspace/coverage/cover_reg_top/36.gpio_intr_test.3681431503 Aug 09 07:01:40 PM PDT 24 Aug 09 07:01:41 PM PDT 24 15894584 ps
T812 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2453696898 Aug 09 07:01:11 PM PDT 24 Aug 09 07:01:12 PM PDT 24 35415299 ps
T813 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.4053993861 Aug 09 07:01:31 PM PDT 24 Aug 09 07:01:33 PM PDT 24 138884557 ps
T814 /workspace/coverage/cover_reg_top/28.gpio_intr_test.3928779896 Aug 09 07:01:41 PM PDT 24 Aug 09 07:01:42 PM PDT 24 15685720 ps
T815 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.155739992 Aug 09 07:01:02 PM PDT 24 Aug 09 07:01:03 PM PDT 24 71692784 ps
T816 /workspace/coverage/cover_reg_top/17.gpio_intr_test.511097521 Aug 09 07:01:38 PM PDT 24 Aug 09 07:01:39 PM PDT 24 16025580 ps
T817 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3321457455 Aug 09 07:01:30 PM PDT 24 Aug 09 07:01:31 PM PDT 24 12916622 ps
T818 /workspace/coverage/cover_reg_top/23.gpio_intr_test.2062512273 Aug 09 07:01:43 PM PDT 24 Aug 09 07:01:43 PM PDT 24 52664312 ps
T819 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2747002317 Aug 09 07:01:02 PM PDT 24 Aug 09 07:01:03 PM PDT 24 42928903 ps
T820 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2326645369 Aug 09 07:01:10 PM PDT 24 Aug 09 07:01:10 PM PDT 24 66794994 ps
T821 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2556320906 Aug 09 07:01:01 PM PDT 24 Aug 09 07:01:04 PM PDT 24 45999711 ps
T94 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.292289098 Aug 09 07:01:02 PM PDT 24 Aug 09 07:01:03 PM PDT 24 46092221 ps
T822 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3325138641 Aug 09 07:01:38 PM PDT 24 Aug 09 07:01:39 PM PDT 24 207708909 ps
T823 /workspace/coverage/cover_reg_top/43.gpio_intr_test.1929208032 Aug 09 07:01:37 PM PDT 24 Aug 09 07:01:38 PM PDT 24 12460051 ps
T824 /workspace/coverage/cover_reg_top/3.gpio_intr_test.3583603393 Aug 09 07:01:12 PM PDT 24 Aug 09 07:01:13 PM PDT 24 21996261 ps
T97 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2708995618 Aug 09 07:01:04 PM PDT 24 Aug 09 07:01:06 PM PDT 24 153614416 ps
T95 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.646809913 Aug 09 07:01:10 PM PDT 24 Aug 09 07:01:11 PM PDT 24 55973441 ps
T825 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1934054342 Aug 09 07:01:30 PM PDT 24 Aug 09 07:01:31 PM PDT 24 149379726 ps
T826 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3159313776 Aug 09 07:01:03 PM PDT 24 Aug 09 07:01:04 PM PDT 24 142156089 ps
T827 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3923526753 Aug 09 07:01:31 PM PDT 24 Aug 09 07:01:32 PM PDT 24 55927232 ps
T828 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2876906553 Aug 09 07:01:10 PM PDT 24 Aug 09 07:01:12 PM PDT 24 41138153 ps
T829 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3196530709 Aug 09 07:01:13 PM PDT 24 Aug 09 07:01:14 PM PDT 24 39385084 ps
T830 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3626835012 Aug 09 07:01:10 PM PDT 24 Aug 09 07:01:11 PM PDT 24 42584046 ps
T831 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.906693651 Aug 09 07:01:03 PM PDT 24 Aug 09 07:01:05 PM PDT 24 36813445 ps
T832 /workspace/coverage/cover_reg_top/2.gpio_intr_test.40800639 Aug 09 07:01:02 PM PDT 24 Aug 09 07:01:03 PM PDT 24 40377031 ps
T833 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.672963635 Aug 09 07:01:12 PM PDT 24 Aug 09 07:01:13 PM PDT 24 18370171 ps
T834 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1104454173 Aug 09 07:01:31 PM PDT 24 Aug 09 07:01:33 PM PDT 24 304818267 ps
T835 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3642686871 Aug 09 07:01:37 PM PDT 24 Aug 09 07:01:38 PM PDT 24 386678688 ps
T836 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3566910129 Aug 09 07:01:11 PM PDT 24 Aug 09 07:01:13 PM PDT 24 144010231 ps
T837 /workspace/coverage/cover_reg_top/18.gpio_intr_test.2197516814 Aug 09 07:01:40 PM PDT 24 Aug 09 07:01:41 PM PDT 24 53140728 ps
T838 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1621351998 Aug 09 07:01:13 PM PDT 24 Aug 09 07:01:14 PM PDT 24 58019716 ps
T839 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2682838667 Aug 09 07:01:01 PM PDT 24 Aug 09 07:01:02 PM PDT 24 60212565 ps
T840 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3756123154 Aug 09 07:01:20 PM PDT 24 Aug 09 07:01:21 PM PDT 24 79177459 ps
T841 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1757104952 Aug 09 07:01:04 PM PDT 24 Aug 09 07:01:05 PM PDT 24 23656049 ps
T842 /workspace/coverage/cover_reg_top/7.gpio_intr_test.3495141213 Aug 09 07:01:11 PM PDT 24 Aug 09 07:01:12 PM PDT 24 12178194 ps
T843 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.847216689 Aug 09 07:01:30 PM PDT 24 Aug 09 07:01:31 PM PDT 24 14566999 ps
T844 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2444941062 Aug 09 07:01:29 PM PDT 24 Aug 09 07:01:30 PM PDT 24 34789927 ps
T845 /workspace/coverage/cover_reg_top/6.gpio_intr_test.3043032805 Aug 09 07:01:14 PM PDT 24 Aug 09 07:01:14 PM PDT 24 16452659 ps
T846 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.899709859 Aug 09 07:01:01 PM PDT 24 Aug 09 07:01:02 PM PDT 24 139754655 ps
T847 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.919488164 Aug 09 07:01:29 PM PDT 24 Aug 09 07:01:30 PM PDT 24 46590266 ps
T848 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4225926392 Aug 09 07:01:51 PM PDT 24 Aug 09 07:01:52 PM PDT 24 150887287 ps
T849 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1701470984 Aug 09 07:02:04 PM PDT 24 Aug 09 07:02:06 PM PDT 24 46120828 ps
T850 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2901205244 Aug 09 07:01:56 PM PDT 24 Aug 09 07:01:57 PM PDT 24 38589530 ps
T851 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2904989193 Aug 09 07:01:47 PM PDT 24 Aug 09 07:01:48 PM PDT 24 57639315 ps
T852 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2746946106 Aug 09 07:01:49 PM PDT 24 Aug 09 07:01:49 PM PDT 24 26141004 ps
T853 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.806822527 Aug 09 07:01:50 PM PDT 24 Aug 09 07:01:51 PM PDT 24 78895214 ps
T854 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.447199787 Aug 09 07:01:53 PM PDT 24 Aug 09 07:01:55 PM PDT 24 52684370 ps
T855 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3212487261 Aug 09 07:01:48 PM PDT 24 Aug 09 07:01:49 PM PDT 24 42830554 ps
T856 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3189365842 Aug 09 07:02:01 PM PDT 24 Aug 09 07:02:03 PM PDT 24 227696466 ps
T857 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1232803840 Aug 09 07:01:51 PM PDT 24 Aug 09 07:01:52 PM PDT 24 98166199 ps
T858 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2993837128 Aug 09 07:01:58 PM PDT 24 Aug 09 07:01:59 PM PDT 24 1285795362 ps
T859 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3128718182 Aug 09 07:01:47 PM PDT 24 Aug 09 07:01:48 PM PDT 24 219826172 ps
T860 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2559703059 Aug 09 07:01:56 PM PDT 24 Aug 09 07:01:57 PM PDT 24 57057175 ps
T861 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1057551291 Aug 09 07:01:46 PM PDT 24 Aug 09 07:01:47 PM PDT 24 50482342 ps
T862 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2470196517 Aug 09 07:01:49 PM PDT 24 Aug 09 07:01:50 PM PDT 24 217249275 ps
T863 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3301214763 Aug 09 07:01:48 PM PDT 24 Aug 09 07:01:49 PM PDT 24 34416945 ps
T864 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3386807398 Aug 09 07:01:47 PM PDT 24 Aug 09 07:01:48 PM PDT 24 95037255 ps
T865 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.672529010 Aug 09 07:01:51 PM PDT 24 Aug 09 07:01:52 PM PDT 24 190939493 ps
T866 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3919510358 Aug 09 07:01:47 PM PDT 24 Aug 09 07:01:49 PM PDT 24 138666423 ps
T867 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2418860892 Aug 09 07:01:47 PM PDT 24 Aug 09 07:01:48 PM PDT 24 46378341 ps
T868 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3348347236 Aug 09 07:01:55 PM PDT 24 Aug 09 07:01:57 PM PDT 24 132111810 ps
T869 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.222844311 Aug 09 07:01:48 PM PDT 24 Aug 09 07:01:49 PM PDT 24 150788221 ps
T870 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3197969287 Aug 09 07:02:06 PM PDT 24 Aug 09 07:02:08 PM PDT 24 99662110 ps
T871 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.596262423 Aug 09 07:01:49 PM PDT 24 Aug 09 07:01:51 PM PDT 24 189523114 ps
T872 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1502507590 Aug 09 07:01:46 PM PDT 24 Aug 09 07:01:47 PM PDT 24 35865886 ps
T873 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1225543882 Aug 09 07:02:01 PM PDT 24 Aug 09 07:02:02 PM PDT 24 180682464 ps
T874 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3562824434 Aug 09 07:02:06 PM PDT 24 Aug 09 07:02:08 PM PDT 24 122369332 ps
T875 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.401821227 Aug 09 07:01:51 PM PDT 24 Aug 09 07:01:53 PM PDT 24 143318094 ps
T876 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2685079058 Aug 09 07:01:47 PM PDT 24 Aug 09 07:01:49 PM PDT 24 39653227 ps
T877 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2670482329 Aug 09 07:01:45 PM PDT 24 Aug 09 07:01:46 PM PDT 24 1584614559 ps
T878 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2731056398 Aug 09 07:01:58 PM PDT 24 Aug 09 07:01:59 PM PDT 24 143348416 ps
T879 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3038311367 Aug 09 07:01:46 PM PDT 24 Aug 09 07:01:47 PM PDT 24 64904111 ps
T880 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1049143271 Aug 09 07:02:00 PM PDT 24 Aug 09 07:02:01 PM PDT 24 626932975 ps
T881 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.102292581 Aug 09 07:01:46 PM PDT 24 Aug 09 07:01:48 PM PDT 24 101644080 ps
T882 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4228008106 Aug 09 07:02:06 PM PDT 24 Aug 09 07:02:07 PM PDT 24 66146970 ps
T883 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2938190056 Aug 09 07:01:54 PM PDT 24 Aug 09 07:01:56 PM PDT 24 227380060 ps
T884 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2586807479 Aug 09 07:01:48 PM PDT 24 Aug 09 07:01:49 PM PDT 24 83330698 ps
T885 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1496124278 Aug 09 07:01:49 PM PDT 24 Aug 09 07:01:50 PM PDT 24 346873498 ps
T886 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.325333494 Aug 09 07:02:08 PM PDT 24 Aug 09 07:02:08 PM PDT 24 35731629 ps
T887 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2290303296 Aug 09 07:01:56 PM PDT 24 Aug 09 07:01:57 PM PDT 24 158354344 ps
T888 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3957383334 Aug 09 07:01:48 PM PDT 24 Aug 09 07:01:49 PM PDT 24 48607762 ps
T889 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2147537589 Aug 09 07:02:05 PM PDT 24 Aug 09 07:02:06 PM PDT 24 55993231 ps
T890 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.656965760 Aug 09 07:01:49 PM PDT 24 Aug 09 07:01:50 PM PDT 24 120089345 ps
T891 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1096816338 Aug 09 07:01:49 PM PDT 24 Aug 09 07:01:50 PM PDT 24 79459032 ps
T892 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3462733450 Aug 09 07:01:57 PM PDT 24 Aug 09 07:01:58 PM PDT 24 55625522 ps
T893 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1934348655 Aug 09 07:01:48 PM PDT 24 Aug 09 07:01:50 PM PDT 24 43427916 ps
T894 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2858836012 Aug 09 07:01:56 PM PDT 24 Aug 09 07:01:58 PM PDT 24 1456064380 ps
T895 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1588963193 Aug 09 07:01:56 PM PDT 24 Aug 09 07:01:58 PM PDT 24 87093732 ps
T896 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2587759758 Aug 09 07:01:52 PM PDT 24 Aug 09 07:01:53 PM PDT 24 69449264 ps
T897 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2855255502 Aug 09 07:01:49 PM PDT 24 Aug 09 07:01:50 PM PDT 24 255278785 ps
T898 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3644663337 Aug 09 07:01:46 PM PDT 24 Aug 09 07:01:48 PM PDT 24 132585139 ps
T899 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.4283859744 Aug 09 07:01:47 PM PDT 24 Aug 09 07:01:48 PM PDT 24 291674330 ps
T900 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2904530898 Aug 09 07:01:57 PM PDT 24 Aug 09 07:01:58 PM PDT 24 52285683 ps
T901 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1575950496 Aug 09 07:01:57 PM PDT 24 Aug 09 07:01:58 PM PDT 24 33520315 ps
T902 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2508516654 Aug 09 07:02:07 PM PDT 24 Aug 09 07:02:08 PM PDT 24 36769285 ps
T903 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2412122509 Aug 09 07:01:48 PM PDT 24 Aug 09 07:01:49 PM PDT 24 70815320 ps
T904 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.66206887 Aug 09 07:01:47 PM PDT 24 Aug 09 07:01:49 PM PDT 24 155918563 ps
T905 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.4288406033 Aug 09 07:02:01 PM PDT 24 Aug 09 07:02:02 PM PDT 24 61985723 ps
T906 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1302987031 Aug 09 07:01:55 PM PDT 24 Aug 09 07:01:57 PM PDT 24 266230093 ps
T907 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2429050065 Aug 09 07:01:57 PM PDT 24 Aug 09 07:01:58 PM PDT 24 142421471 ps
T908 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3936225460 Aug 09 07:02:08 PM PDT 24 Aug 09 07:02:09 PM PDT 24 29198663 ps
T909 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1015970489 Aug 09 07:01:57 PM PDT 24 Aug 09 07:01:59 PM PDT 24 187246866 ps
T910 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.676346485 Aug 09 07:01:56 PM PDT 24 Aug 09 07:01:57 PM PDT 24 535004966 ps
T911 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1078251755 Aug 09 07:01:55 PM PDT 24 Aug 09 07:01:56 PM PDT 24 130067737 ps
T912 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.51062868 Aug 09 07:01:56 PM PDT 24 Aug 09 07:01:57 PM PDT 24 71268536 ps
T913 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.518995990 Aug 09 07:01:51 PM PDT 24 Aug 09 07:01:52 PM PDT 24 247469678 ps
T914 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2272901401 Aug 09 07:01:59 PM PDT 24 Aug 09 07:02:01 PM PDT 24 244104889 ps
T915 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1466832019 Aug 09 07:01:55 PM PDT 24 Aug 09 07:01:56 PM PDT 24 141278505 ps
T916 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1345033306 Aug 09 07:01:47 PM PDT 24 Aug 09 07:01:48 PM PDT 24 23290862 ps
T917 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3626774170 Aug 09 07:01:47 PM PDT 24 Aug 09 07:01:48 PM PDT 24 42643134 ps
T918 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3501471024 Aug 09 07:01:48 PM PDT 24 Aug 09 07:01:49 PM PDT 24 161826978 ps
T919 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2645597074 Aug 09 07:01:56 PM PDT 24 Aug 09 07:01:58 PM PDT 24 44194965 ps
T920 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1024452859 Aug 09 07:01:49 PM PDT 24 Aug 09 07:01:51 PM PDT 24 72923133 ps
T921 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3802615451 Aug 09 07:01:50 PM PDT 24 Aug 09 07:01:51 PM PDT 24 82811393 ps
T922 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1393540293 Aug 09 07:01:57 PM PDT 24 Aug 09 07:01:58 PM PDT 24 62507663 ps
T923 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.270828006 Aug 09 07:01:49 PM PDT 24 Aug 09 07:01:51 PM PDT 24 73126359 ps
T924 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3023083582 Aug 09 07:01:46 PM PDT 24 Aug 09 07:01:47 PM PDT 24 66242082 ps
T925 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1684993577 Aug 09 07:02:05 PM PDT 24 Aug 09 07:02:07 PM PDT 24 80407727 ps
T926 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3654366585 Aug 09 07:01:58 PM PDT 24 Aug 09 07:01:59 PM PDT 24 49881335 ps
T927 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.456300321 Aug 09 07:01:51 PM PDT 24 Aug 09 07:01:52 PM PDT 24 260701754 ps
T928 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1299507790 Aug 09 07:02:00 PM PDT 24 Aug 09 07:02:01 PM PDT 24 230862090 ps
T929 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3690590704 Aug 09 07:02:05 PM PDT 24 Aug 09 07:02:06 PM PDT 24 59326210 ps
T930 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3160127168 Aug 09 07:01:58 PM PDT 24 Aug 09 07:01:59 PM PDT 24 84351075 ps
T931 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3704819243 Aug 09 07:01:50 PM PDT 24 Aug 09 07:01:51 PM PDT 24 44843529 ps
T932 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.4112658223 Aug 09 07:01:49 PM PDT 24 Aug 09 07:01:51 PM PDT 24 294136893 ps
T933 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3604068480 Aug 09 07:01:56 PM PDT 24 Aug 09 07:01:58 PM PDT 24 61895938 ps
T934 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.54942140 Aug 09 07:01:57 PM PDT 24 Aug 09 07:01:58 PM PDT 24 52609844 ps
T935 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4070931944 Aug 09 07:01:50 PM PDT 24 Aug 09 07:01:51 PM PDT 24 363028795 ps
T936 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3503728820 Aug 09 07:01:57 PM PDT 24 Aug 09 07:01:58 PM PDT 24 30489906 ps
T937 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1735521097 Aug 09 07:01:48 PM PDT 24 Aug 09 07:01:50 PM PDT 24 191982352 ps
T938 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.179664922 Aug 09 07:01:56 PM PDT 24 Aug 09 07:01:57 PM PDT 24 75217923 ps
T939 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.762340947 Aug 09 07:01:57 PM PDT 24 Aug 09 07:01:58 PM PDT 24 108511341 ps
T940 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2192169991 Aug 09 07:01:57 PM PDT 24 Aug 09 07:01:58 PM PDT 24 331888337 ps
T941 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2906204478 Aug 09 07:01:57 PM PDT 24 Aug 09 07:01:58 PM PDT 24 116503926 ps
T942 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.216082472 Aug 09 07:01:47 PM PDT 24 Aug 09 07:01:48 PM PDT 24 262112468 ps
T943 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.110471449 Aug 09 07:01:57 PM PDT 24 Aug 09 07:01:58 PM PDT 24 40113566 ps
T944 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2466476193 Aug 09 07:02:07 PM PDT 24 Aug 09 07:02:08 PM PDT 24 85195586 ps
T945 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2974317916 Aug 09 07:01:55 PM PDT 24 Aug 09 07:01:56 PM PDT 24 354030760 ps
T946 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1913285931 Aug 09 07:01:56 PM PDT 24 Aug 09 07:01:58 PM PDT 24 115804808 ps
T947 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.575154015 Aug 09 07:01:49 PM PDT 24 Aug 09 07:01:50 PM PDT 24 129767953 ps

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1186731393
Short name T1
Test name
Test status
Simulation time 371834354 ps
CPU time 4.2 seconds
Started Aug 09 07:03:29 PM PDT 24
Finished Aug 09 07:03:33 PM PDT 24
Peak memory 198516 kb
Host smart-818c44bd-c892-4990-a894-e01266adecc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186731393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.1186731393
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.627989567
Short name T65
Test name
Test status
Simulation time 291343206 ps
CPU time 1.37 seconds
Started Aug 09 07:03:08 PM PDT 24
Finished Aug 09 07:03:10 PM PDT 24
Peak memory 198756 kb
Host smart-a8a94713-23cf-490d-a98c-e1427a4a0bec
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627989567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.gpio_intr_with_filter_rand_intr_event.627989567
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.936167788
Short name T27
Test name
Test status
Simulation time 74072844866 ps
CPU time 544.8 seconds
Started Aug 09 07:03:18 PM PDT 24
Finished Aug 09 07:12:23 PM PDT 24
Peak memory 198904 kb
Host smart-c94dffbd-62f7-4b91-b4c5-195ef98dfa42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=936167788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.936167788
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.1291094673
Short name T35
Test name
Test status
Simulation time 90902405 ps
CPU time 0.98 seconds
Started Aug 09 07:02:16 PM PDT 24
Finished Aug 09 07:02:17 PM PDT 24
Peak memory 215452 kb
Host smart-b142d8f3-6a6b-44bf-b494-b34bd47fb9f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291094673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.1291094673
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3448200027
Short name T82
Test name
Test status
Simulation time 35419611 ps
CPU time 0.89 seconds
Started Aug 09 07:01:02 PM PDT 24
Finished Aug 09 07:01:03 PM PDT 24
Peak memory 196768 kb
Host smart-d6141028-90be-459b-819c-b6ef05b8d05b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448200027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.3448200027
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.289688483
Short name T40
Test name
Test status
Simulation time 420807768 ps
CPU time 1.47 seconds
Started Aug 09 07:01:19 PM PDT 24
Finished Aug 09 07:01:21 PM PDT 24
Peak memory 198976 kb
Host smart-1c82cc61-92ec-40b3-8f3d-e361fe989676
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289688483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.gpio_tl_intg_err.289688483
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.3433796785
Short name T240
Test name
Test status
Simulation time 13334555 ps
CPU time 0.57 seconds
Started Aug 09 07:02:08 PM PDT 24
Finished Aug 09 07:02:09 PM PDT 24
Peak memory 194456 kb
Host smart-131bec5c-518e-41a5-85f4-5bb83db5377d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433796785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.3433796785
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3756123154
Short name T840
Test name
Test status
Simulation time 79177459 ps
CPU time 1.09 seconds
Started Aug 09 07:01:20 PM PDT 24
Finished Aug 09 07:01:21 PM PDT 24
Peak memory 198768 kb
Host smart-4b1060b5-bbd1-404d-9d39-c8cf4ee31de5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756123154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.3756123154
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.906706633
Short name T100
Test name
Test status
Simulation time 19080719 ps
CPU time 0.84 seconds
Started Aug 09 07:01:02 PM PDT 24
Finished Aug 09 07:01:03 PM PDT 24
Peak memory 197676 kb
Host smart-23a5b13a-5c5a-4812-8813-83a173734c93
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906706633 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.gpio_same_csr_outstanding.906706633
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3159313776
Short name T826
Test name
Test status
Simulation time 142156089 ps
CPU time 0.89 seconds
Started Aug 09 07:01:03 PM PDT 24
Finished Aug 09 07:01:04 PM PDT 24
Peak memory 198456 kb
Host smart-dcb41cd5-0925-4059-8621-89642a72cc56
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159313776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.3159313776
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1517777500
Short name T111
Test name
Test status
Simulation time 44006049 ps
CPU time 0.91 seconds
Started Aug 09 07:01:19 PM PDT 24
Finished Aug 09 07:01:20 PM PDT 24
Peak memory 198540 kb
Host smart-601b3de1-3336-4029-ade0-bb9cb053ae22
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517777500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1517777500
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3655195059
Short name T779
Test name
Test status
Simulation time 15363326 ps
CPU time 0.66 seconds
Started Aug 09 07:01:02 PM PDT 24
Finished Aug 09 07:01:03 PM PDT 24
Peak memory 195972 kb
Host smart-73ecf43b-581d-46e5-b2c9-b0ba79b4a4e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655195059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3655195059
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.906693651
Short name T831
Test name
Test status
Simulation time 36813445 ps
CPU time 1.44 seconds
Started Aug 09 07:01:03 PM PDT 24
Finished Aug 09 07:01:05 PM PDT 24
Peak memory 197384 kb
Host smart-5dde76dd-2def-451c-8c6c-724953d5db31
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906693651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.906693651
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1513952809
Short name T81
Test name
Test status
Simulation time 15145041 ps
CPU time 0.63 seconds
Started Aug 09 07:01:04 PM PDT 24
Finished Aug 09 07:01:04 PM PDT 24
Peak memory 195348 kb
Host smart-137460de-33e6-4eb1-8b4d-1b660eeaa8c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513952809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1513952809
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.28281796
Short name T753
Test name
Test status
Simulation time 53275602 ps
CPU time 0.78 seconds
Started Aug 09 07:01:03 PM PDT 24
Finished Aug 09 07:01:04 PM PDT 24
Peak memory 198608 kb
Host smart-e128e6b2-3a0c-4125-8f58-7d70c6d3b62c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28281796 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.28281796
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1614727170
Short name T93
Test name
Test status
Simulation time 12599349 ps
CPU time 0.59 seconds
Started Aug 09 07:00:54 PM PDT 24
Finished Aug 09 07:00:55 PM PDT 24
Peak memory 195160 kb
Host smart-e0537fb5-0011-42f6-b9c6-420b88659d96
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614727170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.1614727170
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.3546637329
Short name T733
Test name
Test status
Simulation time 14788621 ps
CPU time 0.67 seconds
Started Aug 09 07:01:02 PM PDT 24
Finished Aug 09 07:01:03 PM PDT 24
Peak memory 195200 kb
Host smart-d79dcb7c-162e-4023-ac62-96708f9b359c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546637329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3546637329
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.155739992
Short name T815
Test name
Test status
Simulation time 71692784 ps
CPU time 0.67 seconds
Started Aug 09 07:01:02 PM PDT 24
Finished Aug 09 07:01:03 PM PDT 24
Peak memory 196196 kb
Host smart-d66d52dd-7b67-474f-a2e6-52f9c56c6a0d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155739992 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.gpio_same_csr_outstanding.155739992
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.4636469
Short name T746
Test name
Test status
Simulation time 55551382 ps
CPU time 1.02 seconds
Started Aug 09 07:01:01 PM PDT 24
Finished Aug 09 07:01:02 PM PDT 24
Peak memory 198616 kb
Host smart-463ebfd7-5ba3-480f-9c05-b065ce0b0c48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4636469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.4636469
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2708995618
Short name T97
Test name
Test status
Simulation time 153614416 ps
CPU time 1.51 seconds
Started Aug 09 07:01:04 PM PDT 24
Finished Aug 09 07:01:06 PM PDT 24
Peak memory 197920 kb
Host smart-f4b1867d-92a3-4bfe-a510-640bc275023a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708995618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2708995618
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2682838667
Short name T839
Test name
Test status
Simulation time 60212565 ps
CPU time 0.7 seconds
Started Aug 09 07:01:01 PM PDT 24
Finished Aug 09 07:01:02 PM PDT 24
Peak memory 196108 kb
Host smart-9fed4d4c-9742-4722-8395-7a8523692d42
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682838667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2682838667
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2747002317
Short name T819
Test name
Test status
Simulation time 42928903 ps
CPU time 0.96 seconds
Started Aug 09 07:01:02 PM PDT 24
Finished Aug 09 07:01:03 PM PDT 24
Peak memory 198604 kb
Host smart-67323c56-8048-44a6-9271-dd1939cba0f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747002317 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.2747002317
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3692169674
Short name T792
Test name
Test status
Simulation time 14375299 ps
CPU time 0.64 seconds
Started Aug 09 07:01:02 PM PDT 24
Finished Aug 09 07:01:03 PM PDT 24
Peak memory 195388 kb
Host smart-bf32043e-32c9-46b4-abdc-694f73bc7299
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692169674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.3692169674
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1410982155
Short name T728
Test name
Test status
Simulation time 31320479 ps
CPU time 0.61 seconds
Started Aug 09 07:01:05 PM PDT 24
Finished Aug 09 07:01:05 PM PDT 24
Peak memory 195160 kb
Host smart-d53c6f20-6d85-4506-b07a-14c9f6c08966
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410982155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1410982155
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3890842056
Short name T763
Test name
Test status
Simulation time 255197053 ps
CPU time 1.53 seconds
Started Aug 09 07:01:02 PM PDT 24
Finished Aug 09 07:01:03 PM PDT 24
Peak memory 198820 kb
Host smart-8e8b0338-d63c-482a-aa4e-b0dfcefa31c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890842056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.3890842056
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.285531714
Short name T32
Test name
Test status
Simulation time 119528097 ps
CPU time 0.86 seconds
Started Aug 09 07:01:00 PM PDT 24
Finished Aug 09 07:01:01 PM PDT 24
Peak memory 198208 kb
Host smart-8954057b-c59f-4dc9-9dda-84f0465fdeac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285531714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.gpio_tl_intg_err.285531714
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3737289981
Short name T797
Test name
Test status
Simulation time 42215368 ps
CPU time 0.76 seconds
Started Aug 09 07:01:19 PM PDT 24
Finished Aug 09 07:01:20 PM PDT 24
Peak memory 198404 kb
Host smart-2ece3c50-db2d-4004-98ee-d82781146cca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737289981 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.3737289981
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1371756858
Short name T92
Test name
Test status
Simulation time 29994065 ps
CPU time 0.58 seconds
Started Aug 09 07:01:19 PM PDT 24
Finished Aug 09 07:01:20 PM PDT 24
Peak memory 194396 kb
Host smart-815c5077-6639-4b9b-a324-d54c0598b487
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371756858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.1371756858
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3575216772
Short name T748
Test name
Test status
Simulation time 15957507 ps
CPU time 0.59 seconds
Started Aug 09 07:01:21 PM PDT 24
Finished Aug 09 07:01:22 PM PDT 24
Peak memory 194392 kb
Host smart-17de4087-6445-4e13-87e1-b450a8f5f34a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575216772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3575216772
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1239302447
Short name T84
Test name
Test status
Simulation time 15739177 ps
CPU time 0.69 seconds
Started Aug 09 07:01:19 PM PDT 24
Finished Aug 09 07:01:20 PM PDT 24
Peak memory 195600 kb
Host smart-169ed205-0658-46fe-be18-4b09e1143d0b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239302447 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1239302447
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2893330586
Short name T724
Test name
Test status
Simulation time 34375570 ps
CPU time 1.65 seconds
Started Aug 09 07:01:17 PM PDT 24
Finished Aug 09 07:01:19 PM PDT 24
Peak memory 198792 kb
Host smart-1f8e4dfe-c119-4e3b-8738-f76d09c2b882
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893330586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.2893330586
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2839569062
Short name T796
Test name
Test status
Simulation time 30948897 ps
CPU time 1.5 seconds
Started Aug 09 07:01:19 PM PDT 24
Finished Aug 09 07:01:21 PM PDT 24
Peak memory 198768 kb
Host smart-8becbcf1-9b1e-4bcd-ad84-6ad4b69b0752
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839569062 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.2839569062
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2628153108
Short name T758
Test name
Test status
Simulation time 12674959 ps
CPU time 0.61 seconds
Started Aug 09 07:01:18 PM PDT 24
Finished Aug 09 07:01:19 PM PDT 24
Peak memory 195248 kb
Host smart-aa402477-0e78-44f1-be3a-107bd30b59d9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628153108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.2628153108
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.3293186248
Short name T780
Test name
Test status
Simulation time 63078510 ps
CPU time 0.61 seconds
Started Aug 09 07:01:19 PM PDT 24
Finished Aug 09 07:01:20 PM PDT 24
Peak memory 194536 kb
Host smart-daa43d00-c6e0-463e-a002-b783c5caabd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293186248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.3293186248
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.4206409360
Short name T804
Test name
Test status
Simulation time 153821481 ps
CPU time 0.84 seconds
Started Aug 09 07:01:19 PM PDT 24
Finished Aug 09 07:01:20 PM PDT 24
Peak memory 197648 kb
Host smart-d9722fd1-beef-459a-9005-6011a69e8402
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206409360 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.4206409360
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3769121921
Short name T743
Test name
Test status
Simulation time 292944286 ps
CPU time 1.8 seconds
Started Aug 09 07:01:21 PM PDT 24
Finished Aug 09 07:01:23 PM PDT 24
Peak memory 198748 kb
Host smart-8ecd49d9-6106-4a6a-85f2-8ba1bf04af2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769121921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.3769121921
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1545179394
Short name T810
Test name
Test status
Simulation time 19176181 ps
CPU time 0.86 seconds
Started Aug 09 07:01:29 PM PDT 24
Finished Aug 09 07:01:30 PM PDT 24
Peak memory 198604 kb
Host smart-43e1fda9-1259-416b-b07a-7a86596c3dd8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545179394 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.1545179394
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3156774347
Short name T749
Test name
Test status
Simulation time 12729690 ps
CPU time 0.6 seconds
Started Aug 09 07:01:28 PM PDT 24
Finished Aug 09 07:01:28 PM PDT 24
Peak memory 195380 kb
Host smart-acaea069-7da2-4f43-8273-ad176d06c6e3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156774347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.3156774347
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.4964203
Short name T767
Test name
Test status
Simulation time 22382830 ps
CPU time 0.58 seconds
Started Aug 09 07:01:29 PM PDT 24
Finished Aug 09 07:01:30 PM PDT 24
Peak memory 194396 kb
Host smart-1e590c7b-29be-4cf3-80a8-bc79e31281ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4964203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.4964203
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2444941062
Short name T844
Test name
Test status
Simulation time 34789927 ps
CPU time 0.85 seconds
Started Aug 09 07:01:29 PM PDT 24
Finished Aug 09 07:01:30 PM PDT 24
Peak memory 196992 kb
Host smart-5eb713bb-2d01-4de9-92fb-5069668e90de
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444941062 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2444941062
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2735085006
Short name T723
Test name
Test status
Simulation time 66395320 ps
CPU time 2.17 seconds
Started Aug 09 07:01:32 PM PDT 24
Finished Aug 09 07:01:34 PM PDT 24
Peak memory 198824 kb
Host smart-457148c8-6a9c-44b9-9b4e-c9d2572deca0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735085006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.2735085006
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3394171682
Short name T45
Test name
Test status
Simulation time 667042602 ps
CPU time 1.22 seconds
Started Aug 09 07:01:30 PM PDT 24
Finished Aug 09 07:01:32 PM PDT 24
Peak memory 198720 kb
Host smart-3458e61f-c08f-4860-8adc-29bc3b97b4ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394171682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.3394171682
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.31337555
Short name T744
Test name
Test status
Simulation time 22337478 ps
CPU time 0.78 seconds
Started Aug 09 07:01:28 PM PDT 24
Finished Aug 09 07:01:29 PM PDT 24
Peak memory 198536 kb
Host smart-a62b5124-fad9-4789-a098-da38e413003c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31337555 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.31337555
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3321457455
Short name T817
Test name
Test status
Simulation time 12916622 ps
CPU time 0.6 seconds
Started Aug 09 07:01:30 PM PDT 24
Finished Aug 09 07:01:31 PM PDT 24
Peak memory 194440 kb
Host smart-f7515d5b-0387-4bc5-acdb-46035767bf85
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321457455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.3321457455
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.2646789557
Short name T741
Test name
Test status
Simulation time 22384147 ps
CPU time 0.66 seconds
Started Aug 09 07:01:30 PM PDT 24
Finished Aug 09 07:01:31 PM PDT 24
Peak memory 195176 kb
Host smart-f9b908aa-2d56-4966-8a2a-673958ff5c38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646789557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.2646789557
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1689948147
Short name T99
Test name
Test status
Simulation time 36155534 ps
CPU time 0.88 seconds
Started Aug 09 07:01:30 PM PDT 24
Finished Aug 09 07:01:31 PM PDT 24
Peak memory 197772 kb
Host smart-a99412c2-ea1a-41ce-81e0-2beaf3d17577
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689948147 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.1689948147
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.4053993861
Short name T813
Test name
Test status
Simulation time 138884557 ps
CPU time 1.92 seconds
Started Aug 09 07:01:31 PM PDT 24
Finished Aug 09 07:01:33 PM PDT 24
Peak memory 198688 kb
Host smart-2deec739-f69d-4fba-9be8-cee3dfa052bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053993861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.4053993861
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.919488164
Short name T847
Test name
Test status
Simulation time 46590266 ps
CPU time 0.89 seconds
Started Aug 09 07:01:29 PM PDT 24
Finished Aug 09 07:01:30 PM PDT 24
Peak memory 197900 kb
Host smart-f325a6c1-a0cf-4e1e-9cba-f8d6d2c03008
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919488164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.gpio_tl_intg_err.919488164
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1154482884
Short name T805
Test name
Test status
Simulation time 31373242 ps
CPU time 0.79 seconds
Started Aug 09 07:01:31 PM PDT 24
Finished Aug 09 07:01:33 PM PDT 24
Peak memory 198580 kb
Host smart-092c390b-ee7a-48f3-816f-b52686fb35d6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154482884 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1154482884
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2227438146
Short name T80
Test name
Test status
Simulation time 30871629 ps
CPU time 0.61 seconds
Started Aug 09 07:01:30 PM PDT 24
Finished Aug 09 07:01:31 PM PDT 24
Peak memory 195544 kb
Host smart-c5887ae5-777e-4e7c-ac13-ea5c8a308984
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227438146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2227438146
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.4174350165
Short name T725
Test name
Test status
Simulation time 17714277 ps
CPU time 0.62 seconds
Started Aug 09 07:01:30 PM PDT 24
Finished Aug 09 07:01:31 PM PDT 24
Peak memory 194484 kb
Host smart-2e4aed4f-4cc1-4deb-82f8-6911805db459
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174350165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.4174350165
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2124576463
Short name T102
Test name
Test status
Simulation time 36265986 ps
CPU time 0.66 seconds
Started Aug 09 07:01:29 PM PDT 24
Finished Aug 09 07:01:30 PM PDT 24
Peak memory 195536 kb
Host smart-76007477-a419-45fe-a094-d672ae8c8499
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124576463 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2124576463
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3755641035
Short name T761
Test name
Test status
Simulation time 56874846 ps
CPU time 2.91 seconds
Started Aug 09 07:01:29 PM PDT 24
Finished Aug 09 07:01:33 PM PDT 24
Peak memory 198744 kb
Host smart-70c3e083-9342-4c87-9e63-8a1329ccce2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755641035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.3755641035
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2392231720
Short name T44
Test name
Test status
Simulation time 39508354 ps
CPU time 0.92 seconds
Started Aug 09 07:01:30 PM PDT 24
Finished Aug 09 07:01:31 PM PDT 24
Peak memory 197844 kb
Host smart-91a1e232-2a49-4cab-bb42-391275ac7586
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392231720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.2392231720
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.497170762
Short name T772
Test name
Test status
Simulation time 35599333 ps
CPU time 1.07 seconds
Started Aug 09 07:01:31 PM PDT 24
Finished Aug 09 07:01:32 PM PDT 24
Peak memory 198648 kb
Host smart-5eb4d536-1cad-48c4-a715-2abb6d91b013
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497170762 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.497170762
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.788607784
Short name T90
Test name
Test status
Simulation time 16201521 ps
CPU time 0.64 seconds
Started Aug 09 07:01:30 PM PDT 24
Finished Aug 09 07:01:30 PM PDT 24
Peak memory 195596 kb
Host smart-efcd525a-0a5f-47af-8023-fbe0a520e55e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788607784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio
_csr_rw.788607784
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.4165406132
Short name T809
Test name
Test status
Simulation time 12347464 ps
CPU time 0.59 seconds
Started Aug 09 07:01:28 PM PDT 24
Finished Aug 09 07:01:29 PM PDT 24
Peak memory 195120 kb
Host smart-08b59aab-48bc-4c91-84ec-7392e6cba389
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165406132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.4165406132
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.847216689
Short name T843
Test name
Test status
Simulation time 14566999 ps
CPU time 0.7 seconds
Started Aug 09 07:01:30 PM PDT 24
Finished Aug 09 07:01:31 PM PDT 24
Peak memory 195700 kb
Host smart-3adf9ad3-4c14-4fbf-8f2c-3795d434b9c5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847216689 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 15.gpio_same_csr_outstanding.847216689
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3757657584
Short name T770
Test name
Test status
Simulation time 819888112 ps
CPU time 3.17 seconds
Started Aug 09 07:01:29 PM PDT 24
Finished Aug 09 07:01:32 PM PDT 24
Peak memory 198768 kb
Host smart-c9d0c36b-ff01-4e27-8152-bcc483e4da51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757657584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.3757657584
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1934054342
Short name T825
Test name
Test status
Simulation time 149379726 ps
CPU time 0.84 seconds
Started Aug 09 07:01:30 PM PDT 24
Finished Aug 09 07:01:31 PM PDT 24
Peak memory 197544 kb
Host smart-606dd993-32ac-4857-96db-b5d716ca78c0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934054342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.1934054342
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2226880094
Short name T789
Test name
Test status
Simulation time 28202283 ps
CPU time 0.84 seconds
Started Aug 09 07:01:28 PM PDT 24
Finished Aug 09 07:01:29 PM PDT 24
Peak memory 198540 kb
Host smart-33d7e897-52dd-41fd-a075-4aedd938fe46
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226880094 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2226880094
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.653897330
Short name T791
Test name
Test status
Simulation time 96903186 ps
CPU time 0.59 seconds
Started Aug 09 07:01:29 PM PDT 24
Finished Aug 09 07:01:29 PM PDT 24
Peak memory 194312 kb
Host smart-f16ecd11-c745-47b1-9e10-a95b48be057c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653897330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.653897330
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.1929580140
Short name T729
Test name
Test status
Simulation time 13869775 ps
CPU time 0.6 seconds
Started Aug 09 07:01:32 PM PDT 24
Finished Aug 09 07:01:32 PM PDT 24
Peak memory 194492 kb
Host smart-0f7cb02b-2ff3-4eeb-a315-cae6018af0d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929580140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.1929580140
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.509116338
Short name T103
Test name
Test status
Simulation time 18781317 ps
CPU time 0.84 seconds
Started Aug 09 07:01:29 PM PDT 24
Finished Aug 09 07:01:30 PM PDT 24
Peak memory 197008 kb
Host smart-b3a8ec49-eb77-4805-90ba-83166c41f0a8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509116338 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 16.gpio_same_csr_outstanding.509116338
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.3657131988
Short name T740
Test name
Test status
Simulation time 56827593 ps
CPU time 1.35 seconds
Started Aug 09 07:01:32 PM PDT 24
Finished Aug 09 07:01:34 PM PDT 24
Peak memory 198756 kb
Host smart-19f22e0b-598c-4a8a-b45e-d7e93ac1db1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657131988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.3657131988
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.4190640765
Short name T43
Test name
Test status
Simulation time 236465808 ps
CPU time 1.43 seconds
Started Aug 09 07:01:30 PM PDT 24
Finished Aug 09 07:01:32 PM PDT 24
Peak memory 198700 kb
Host smart-fb951f81-139a-4ef1-bece-b8b8b02a3f9c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190640765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.4190640765
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3892502694
Short name T726
Test name
Test status
Simulation time 42965566 ps
CPU time 0.78 seconds
Started Aug 09 07:01:28 PM PDT 24
Finished Aug 09 07:01:29 PM PDT 24
Peak memory 198600 kb
Host smart-f56bd949-660f-4b4d-878e-d23e71c38ffc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892502694 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3892502694
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.820363996
Short name T737
Test name
Test status
Simulation time 15529223 ps
CPU time 0.59 seconds
Started Aug 09 07:01:30 PM PDT 24
Finished Aug 09 07:01:30 PM PDT 24
Peak memory 194048 kb
Host smart-08ed0472-b683-4037-937a-548fd10c1fea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820363996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.820363996
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.511097521
Short name T816
Test name
Test status
Simulation time 16025580 ps
CPU time 0.62 seconds
Started Aug 09 07:01:38 PM PDT 24
Finished Aug 09 07:01:39 PM PDT 24
Peak memory 194492 kb
Host smart-c2f5ee49-af4b-433e-81cf-b2683a874d8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511097521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.511097521
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1104454173
Short name T834
Test name
Test status
Simulation time 304818267 ps
CPU time 0.77 seconds
Started Aug 09 07:01:31 PM PDT 24
Finished Aug 09 07:01:33 PM PDT 24
Peak memory 195548 kb
Host smart-bff5120b-8562-4a29-8292-56037acd395a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104454173 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.1104454173
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1408813928
Short name T778
Test name
Test status
Simulation time 126362957 ps
CPU time 2.62 seconds
Started Aug 09 07:01:28 PM PDT 24
Finished Aug 09 07:01:30 PM PDT 24
Peak memory 198876 kb
Host smart-edc94689-c5a1-4468-996d-d39e1103fc9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408813928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1408813928
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3923526753
Short name T827
Test name
Test status
Simulation time 55927232 ps
CPU time 0.88 seconds
Started Aug 09 07:01:31 PM PDT 24
Finished Aug 09 07:01:32 PM PDT 24
Peak memory 198452 kb
Host smart-42c817ee-de34-407d-9c73-1bf7393bd853
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923526753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.3923526753
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.1363260509
Short name T774
Test name
Test status
Simulation time 26261755 ps
CPU time 0.84 seconds
Started Aug 09 07:01:39 PM PDT 24
Finished Aug 09 07:01:40 PM PDT 24
Peak memory 198652 kb
Host smart-56e8cad8-9dc8-4ec2-ae30-ae77486688b9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363260509 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.1363260509
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.420673870
Short name T793
Test name
Test status
Simulation time 62604675 ps
CPU time 0.59 seconds
Started Aug 09 07:01:39 PM PDT 24
Finished Aug 09 07:01:39 PM PDT 24
Peak memory 194016 kb
Host smart-810c812e-ff2e-4bab-bb54-4380b8cff08e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420673870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio
_csr_rw.420673870
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2197516814
Short name T837
Test name
Test status
Simulation time 53140728 ps
CPU time 0.67 seconds
Started Aug 09 07:01:40 PM PDT 24
Finished Aug 09 07:01:41 PM PDT 24
Peak memory 194564 kb
Host smart-328785d3-6e78-4528-9850-266ae0d0b234
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197516814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2197516814
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1424121821
Short name T98
Test name
Test status
Simulation time 43831804 ps
CPU time 0.72 seconds
Started Aug 09 07:01:39 PM PDT 24
Finished Aug 09 07:01:39 PM PDT 24
Peak memory 196328 kb
Host smart-aaed87d8-45f3-4890-b60d-b0fbd1a4ab82
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424121821 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.1424121821
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3325138641
Short name T822
Test name
Test status
Simulation time 207708909 ps
CPU time 1.27 seconds
Started Aug 09 07:01:38 PM PDT 24
Finished Aug 09 07:01:39 PM PDT 24
Peak memory 198820 kb
Host smart-c2a2c224-0f06-4476-9021-2b0f5ed3231f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325138641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3325138641
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3642686871
Short name T835
Test name
Test status
Simulation time 386678688 ps
CPU time 1.32 seconds
Started Aug 09 07:01:37 PM PDT 24
Finished Aug 09 07:01:38 PM PDT 24
Peak memory 198584 kb
Host smart-84fa6155-b532-415c-8628-dbc5e49e7f92
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642686871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.3642686871
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2611187454
Short name T802
Test name
Test status
Simulation time 41614712 ps
CPU time 1.36 seconds
Started Aug 09 07:01:38 PM PDT 24
Finished Aug 09 07:01:39 PM PDT 24
Peak memory 198864 kb
Host smart-e28d03e5-17bb-4bf4-9296-b0183a2bb4f2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611187454 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2611187454
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.4236388102
Short name T800
Test name
Test status
Simulation time 26148929 ps
CPU time 0.58 seconds
Started Aug 09 07:01:38 PM PDT 24
Finished Aug 09 07:01:38 PM PDT 24
Peak memory 195380 kb
Host smart-b04865b2-db0e-4bf4-b671-390c6d61c0dc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236388102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.4236388102
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1801152448
Short name T747
Test name
Test status
Simulation time 68765635 ps
CPU time 0.62 seconds
Started Aug 09 07:01:41 PM PDT 24
Finished Aug 09 07:01:42 PM PDT 24
Peak memory 194516 kb
Host smart-4dd5818a-4603-4849-9869-8cefd2eecd2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801152448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1801152448
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.503556758
Short name T786
Test name
Test status
Simulation time 14462407 ps
CPU time 0.64 seconds
Started Aug 09 07:01:41 PM PDT 24
Finished Aug 09 07:01:42 PM PDT 24
Peak memory 196128 kb
Host smart-72842dfc-91f1-4ced-ba91-14fa64d3fa4b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503556758 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.503556758
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3880566502
Short name T769
Test name
Test status
Simulation time 79790594 ps
CPU time 1.88 seconds
Started Aug 09 07:01:42 PM PDT 24
Finished Aug 09 07:01:44 PM PDT 24
Peak memory 198840 kb
Host smart-fc35f099-5ce3-4c00-89fe-56c4d96dc8c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880566502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3880566502
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3102545812
Short name T30
Test name
Test status
Simulation time 59215561 ps
CPU time 0.88 seconds
Started Aug 09 07:01:38 PM PDT 24
Finished Aug 09 07:01:39 PM PDT 24
Peak memory 197560 kb
Host smart-e4eead92-694f-4757-8a13-7226e26c7891
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102545812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3102545812
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.292289098
Short name T94
Test name
Test status
Simulation time 46092221 ps
CPU time 0.76 seconds
Started Aug 09 07:01:02 PM PDT 24
Finished Aug 09 07:01:03 PM PDT 24
Peak memory 196616 kb
Host smart-3751f718-96a9-4e24-9ce4-1388f738fa95
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292289098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.292289098
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.975213109
Short name T795
Test name
Test status
Simulation time 220566135 ps
CPU time 2.69 seconds
Started Aug 09 07:01:02 PM PDT 24
Finished Aug 09 07:01:05 PM PDT 24
Peak memory 198696 kb
Host smart-2238a078-4f67-432b-afe6-ed52a680f475
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975213109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.975213109
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1938424237
Short name T754
Test name
Test status
Simulation time 15807805 ps
CPU time 0.63 seconds
Started Aug 09 07:01:03 PM PDT 24
Finished Aug 09 07:01:04 PM PDT 24
Peak memory 195724 kb
Host smart-ae6a89da-275b-44c9-8854-6fdf5813915d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938424237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1938424237
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2455811558
Short name T771
Test name
Test status
Simulation time 50747523 ps
CPU time 0.84 seconds
Started Aug 09 07:01:02 PM PDT 24
Finished Aug 09 07:01:03 PM PDT 24
Peak memory 198588 kb
Host smart-91320036-cf90-4530-b5d3-6a2ab3675d81
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455811558 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2455811558
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2658028205
Short name T85
Test name
Test status
Simulation time 22357137 ps
CPU time 0.62 seconds
Started Aug 09 07:01:01 PM PDT 24
Finished Aug 09 07:01:01 PM PDT 24
Peak memory 195016 kb
Host smart-e98556fb-6f48-494e-b1c1-bec75a248808
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658028205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.2658028205
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.40800639
Short name T832
Test name
Test status
Simulation time 40377031 ps
CPU time 0.61 seconds
Started Aug 09 07:01:02 PM PDT 24
Finished Aug 09 07:01:03 PM PDT 24
Peak memory 194448 kb
Host smart-f61432a0-56fe-4766-8cc3-dd217826653e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40800639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.40800639
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2941496723
Short name T806
Test name
Test status
Simulation time 72362654 ps
CPU time 0.85 seconds
Started Aug 09 07:01:03 PM PDT 24
Finished Aug 09 07:01:04 PM PDT 24
Peak memory 197592 kb
Host smart-8adff91f-5f93-4cd3-8390-572468585a2b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941496723 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2941496723
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2556320906
Short name T821
Test name
Test status
Simulation time 45999711 ps
CPU time 2.21 seconds
Started Aug 09 07:01:01 PM PDT 24
Finished Aug 09 07:01:04 PM PDT 24
Peak memory 198792 kb
Host smart-6d68827d-73e5-497e-996e-5d55c2cfd614
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556320906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.2556320906
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3924131890
Short name T41
Test name
Test status
Simulation time 252986266 ps
CPU time 0.92 seconds
Started Aug 09 07:01:03 PM PDT 24
Finished Aug 09 07:01:04 PM PDT 24
Peak memory 197920 kb
Host smart-64d75024-e04f-429c-9318-6ef53d435d18
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924131890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3924131890
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.1967192519
Short name T732
Test name
Test status
Simulation time 197090180 ps
CPU time 0.6 seconds
Started Aug 09 07:01:40 PM PDT 24
Finished Aug 09 07:01:41 PM PDT 24
Peak memory 194500 kb
Host smart-b03a4a9e-05a5-4d4e-a337-3b1d3792718f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967192519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.1967192519
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2605792686
Short name T742
Test name
Test status
Simulation time 13754881 ps
CPU time 0.59 seconds
Started Aug 09 07:01:40 PM PDT 24
Finished Aug 09 07:01:40 PM PDT 24
Peak memory 194456 kb
Host smart-f736df68-d046-4a66-9ac8-1b14d50a027a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605792686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2605792686
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.390716777
Short name T808
Test name
Test status
Simulation time 16865437 ps
CPU time 0.61 seconds
Started Aug 09 07:01:40 PM PDT 24
Finished Aug 09 07:01:40 PM PDT 24
Peak memory 194552 kb
Host smart-35a0f6ce-d204-47f5-b582-59de576f4dcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390716777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.390716777
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.2062512273
Short name T818
Test name
Test status
Simulation time 52664312 ps
CPU time 0.63 seconds
Started Aug 09 07:01:43 PM PDT 24
Finished Aug 09 07:01:43 PM PDT 24
Peak memory 194432 kb
Host smart-f4fcd960-6f3a-44c2-8226-cdc2008f3415
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062512273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.2062512273
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.3559024491
Short name T768
Test name
Test status
Simulation time 53310766 ps
CPU time 0.66 seconds
Started Aug 09 07:01:41 PM PDT 24
Finished Aug 09 07:01:42 PM PDT 24
Peak memory 193664 kb
Host smart-f781f30d-adac-45b3-97e3-cbcda14391a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559024491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.3559024491
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.1664432991
Short name T731
Test name
Test status
Simulation time 22971241 ps
CPU time 0.6 seconds
Started Aug 09 07:01:39 PM PDT 24
Finished Aug 09 07:01:40 PM PDT 24
Peak memory 194508 kb
Host smart-9756a1f2-ef46-43ad-9990-0104321a026d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664432991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.1664432991
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.2616895681
Short name T734
Test name
Test status
Simulation time 32389469 ps
CPU time 0.57 seconds
Started Aug 09 07:01:38 PM PDT 24
Finished Aug 09 07:01:38 PM PDT 24
Peak memory 194464 kb
Host smart-00a9b22e-3d6e-43ad-9481-837c350ba3f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616895681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2616895681
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.2351935478
Short name T764
Test name
Test status
Simulation time 15254543 ps
CPU time 0.64 seconds
Started Aug 09 07:01:41 PM PDT 24
Finished Aug 09 07:01:42 PM PDT 24
Peak memory 195156 kb
Host smart-979122b0-ce5c-4534-959b-d8b3e759ff7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351935478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.2351935478
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.3928779896
Short name T814
Test name
Test status
Simulation time 15685720 ps
CPU time 0.62 seconds
Started Aug 09 07:01:41 PM PDT 24
Finished Aug 09 07:01:42 PM PDT 24
Peak memory 194468 kb
Host smart-682ed669-5ee8-468a-a6dc-d20b0005f8da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928779896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.3928779896
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.3473785886
Short name T785
Test name
Test status
Simulation time 100515388 ps
CPU time 0.64 seconds
Started Aug 09 07:01:38 PM PDT 24
Finished Aug 09 07:01:39 PM PDT 24
Peak memory 195244 kb
Host smart-dc1497c0-6e7c-4f05-abe2-a82b59effe50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473785886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.3473785886
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2803859131
Short name T88
Test name
Test status
Simulation time 18620254 ps
CPU time 0.86 seconds
Started Aug 09 07:01:05 PM PDT 24
Finished Aug 09 07:01:06 PM PDT 24
Peak memory 196632 kb
Host smart-5ba65fbb-961c-4640-bde6-b2b1577e3730
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803859131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.2803859131
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1744599233
Short name T83
Test name
Test status
Simulation time 933006275 ps
CPU time 1.57 seconds
Started Aug 09 07:01:10 PM PDT 24
Finished Aug 09 07:01:12 PM PDT 24
Peak memory 197368 kb
Host smart-3f34879c-7dab-4447-9d27-4d65ed9450e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744599233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.1744599233
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.672963635
Short name T833
Test name
Test status
Simulation time 18370171 ps
CPU time 0.66 seconds
Started Aug 09 07:01:12 PM PDT 24
Finished Aug 09 07:01:13 PM PDT 24
Peak memory 195556 kb
Host smart-76c54b5f-a625-48a3-95fe-a9f3a11cae59
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672963635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.672963635
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1757104952
Short name T841
Test name
Test status
Simulation time 23656049 ps
CPU time 0.76 seconds
Started Aug 09 07:01:04 PM PDT 24
Finished Aug 09 07:01:05 PM PDT 24
Peak memory 198576 kb
Host smart-93a3c7a8-4dc0-4387-8abd-8d4668686804
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757104952 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.1757104952
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2587024111
Short name T96
Test name
Test status
Simulation time 24709581 ps
CPU time 0.64 seconds
Started Aug 09 07:01:01 PM PDT 24
Finished Aug 09 07:01:02 PM PDT 24
Peak memory 195680 kb
Host smart-ccf63849-ce90-4f25-8b1f-9c4e66aff90c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587024111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2587024111
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3583603393
Short name T824
Test name
Test status
Simulation time 21996261 ps
CPU time 0.59 seconds
Started Aug 09 07:01:12 PM PDT 24
Finished Aug 09 07:01:13 PM PDT 24
Peak memory 194416 kb
Host smart-0561015a-33c3-432e-b4ac-37d2d040a96b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583603393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3583603393
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1134077050
Short name T101
Test name
Test status
Simulation time 32053524 ps
CPU time 0.67 seconds
Started Aug 09 07:01:04 PM PDT 24
Finished Aug 09 07:01:05 PM PDT 24
Peak memory 195584 kb
Host smart-88be915a-f4fd-445f-bd72-a5484d66dfa7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134077050 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.1134077050
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1630370844
Short name T757
Test name
Test status
Simulation time 263510011 ps
CPU time 2.85 seconds
Started Aug 09 07:01:10 PM PDT 24
Finished Aug 09 07:01:13 PM PDT 24
Peak memory 198812 kb
Host smart-dd3f85cd-51ab-40e3-b46f-5eb045f3ee26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630370844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.1630370844
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.899709859
Short name T846
Test name
Test status
Simulation time 139754655 ps
CPU time 0.86 seconds
Started Aug 09 07:01:01 PM PDT 24
Finished Aug 09 07:01:02 PM PDT 24
Peak memory 197836 kb
Host smart-3954a37c-ef63-4295-9579-540572679c2b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899709859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.899709859
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.4191636181
Short name T738
Test name
Test status
Simulation time 13092309 ps
CPU time 0.6 seconds
Started Aug 09 07:01:38 PM PDT 24
Finished Aug 09 07:01:39 PM PDT 24
Peak memory 194416 kb
Host smart-b1b4b13a-beae-4d22-b37f-2edc62f1fd54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191636181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.4191636181
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.1826658289
Short name T745
Test name
Test status
Simulation time 15137274 ps
CPU time 0.61 seconds
Started Aug 09 07:01:40 PM PDT 24
Finished Aug 09 07:01:40 PM PDT 24
Peak memory 194516 kb
Host smart-7dac6d6c-a6eb-498a-a61b-68b9d1497951
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826658289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.1826658289
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.2233548892
Short name T794
Test name
Test status
Simulation time 15449588 ps
CPU time 0.62 seconds
Started Aug 09 07:01:41 PM PDT 24
Finished Aug 09 07:01:42 PM PDT 24
Peak memory 193400 kb
Host smart-5927ed07-bd7c-48c0-b930-ddd41389a931
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233548892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.2233548892
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3921443463
Short name T775
Test name
Test status
Simulation time 15263043 ps
CPU time 0.61 seconds
Started Aug 09 07:01:41 PM PDT 24
Finished Aug 09 07:01:42 PM PDT 24
Peak memory 195232 kb
Host smart-d9a7103b-b298-49a4-b0a7-c417d7136db7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921443463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3921443463
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.2662764251
Short name T759
Test name
Test status
Simulation time 15635572 ps
CPU time 0.62 seconds
Started Aug 09 07:01:39 PM PDT 24
Finished Aug 09 07:01:39 PM PDT 24
Peak memory 194532 kb
Host smart-0818c7ad-64c3-42ba-8ecf-c9e887c93fc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662764251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.2662764251
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.1853489899
Short name T739
Test name
Test status
Simulation time 17988025 ps
CPU time 0.66 seconds
Started Aug 09 07:01:39 PM PDT 24
Finished Aug 09 07:01:40 PM PDT 24
Peak memory 194604 kb
Host smart-37af495c-05d7-4d9c-b0c4-e32432bf3f46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853489899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.1853489899
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3681431503
Short name T811
Test name
Test status
Simulation time 15894584 ps
CPU time 0.58 seconds
Started Aug 09 07:01:40 PM PDT 24
Finished Aug 09 07:01:41 PM PDT 24
Peak memory 194532 kb
Host smart-82e0cb0b-3f3e-422a-a215-792b691d13d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681431503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3681431503
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.3519065683
Short name T784
Test name
Test status
Simulation time 17308586 ps
CPU time 0.57 seconds
Started Aug 09 07:01:43 PM PDT 24
Finished Aug 09 07:01:43 PM PDT 24
Peak memory 194368 kb
Host smart-86c8167b-084c-412b-ab10-80479b50fe39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519065683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.3519065683
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1158119814
Short name T755
Test name
Test status
Simulation time 18277343 ps
CPU time 0.6 seconds
Started Aug 09 07:01:38 PM PDT 24
Finished Aug 09 07:01:39 PM PDT 24
Peak memory 195208 kb
Host smart-84508d1f-1178-4d5d-ae6b-2c6bbc4ec068
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158119814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1158119814
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.114498202
Short name T781
Test name
Test status
Simulation time 93239689 ps
CPU time 0.59 seconds
Started Aug 09 07:01:40 PM PDT 24
Finished Aug 09 07:01:41 PM PDT 24
Peak memory 194428 kb
Host smart-06e84121-17ca-4474-bc52-17a6a5da0b81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114498202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.114498202
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.646809913
Short name T95
Test name
Test status
Simulation time 55973441 ps
CPU time 0.74 seconds
Started Aug 09 07:01:10 PM PDT 24
Finished Aug 09 07:01:11 PM PDT 24
Peak memory 196448 kb
Host smart-6441da36-943e-424e-951e-d3eb2c22dd7d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646809913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.gpio_csr_aliasing.646809913
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.293259747
Short name T760
Test name
Test status
Simulation time 180173192 ps
CPU time 1.46 seconds
Started Aug 09 07:01:10 PM PDT 24
Finished Aug 09 07:01:12 PM PDT 24
Peak memory 197136 kb
Host smart-1d1499cf-01f2-40ae-b5c3-7a6fb2941856
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293259747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.293259747
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1581675699
Short name T798
Test name
Test status
Simulation time 13389787 ps
CPU time 0.59 seconds
Started Aug 09 07:01:12 PM PDT 24
Finished Aug 09 07:01:13 PM PDT 24
Peak memory 195096 kb
Host smart-b9f64eb6-315e-43bb-8998-d21179599bd9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581675699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1581675699
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.4100537782
Short name T727
Test name
Test status
Simulation time 23065263 ps
CPU time 1 seconds
Started Aug 09 07:01:12 PM PDT 24
Finished Aug 09 07:01:13 PM PDT 24
Peak memory 198544 kb
Host smart-6f5d5e5d-b7fc-40e2-9672-9f5c01f0f747
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100537782 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.4100537782
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1446262310
Short name T86
Test name
Test status
Simulation time 35286061 ps
CPU time 0.63 seconds
Started Aug 09 07:01:14 PM PDT 24
Finished Aug 09 07:01:14 PM PDT 24
Peak memory 195192 kb
Host smart-fd89463e-7b30-4427-9703-720df1a8090b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446262310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1446262310
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.850003571
Short name T756
Test name
Test status
Simulation time 12765175 ps
CPU time 0.58 seconds
Started Aug 09 07:01:09 PM PDT 24
Finished Aug 09 07:01:10 PM PDT 24
Peak memory 194512 kb
Host smart-ba429c28-4068-4704-9700-b71addcb6403
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850003571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.850003571
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1087126153
Short name T105
Test name
Test status
Simulation time 19227278 ps
CPU time 0.63 seconds
Started Aug 09 07:01:10 PM PDT 24
Finished Aug 09 07:01:11 PM PDT 24
Peak memory 196104 kb
Host smart-fef30a42-d366-4ec9-99ae-c03897af1945
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087126153 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.1087126153
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3104104547
Short name T790
Test name
Test status
Simulation time 346888356 ps
CPU time 2.2 seconds
Started Aug 09 07:01:12 PM PDT 24
Finished Aug 09 07:01:14 PM PDT 24
Peak memory 199020 kb
Host smart-ccbbde80-a351-483e-87af-992aa01b89e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104104547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.3104104547
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.124560133
Short name T46
Test name
Test status
Simulation time 51964143 ps
CPU time 0.88 seconds
Started Aug 09 07:01:10 PM PDT 24
Finished Aug 09 07:01:11 PM PDT 24
Peak memory 197912 kb
Host smart-2c560ca2-dc2e-4e6e-8b1b-494b327287be
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124560133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.gpio_tl_intg_err.124560133
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1687536242
Short name T735
Test name
Test status
Simulation time 48997208 ps
CPU time 0.6 seconds
Started Aug 09 07:01:41 PM PDT 24
Finished Aug 09 07:01:42 PM PDT 24
Peak memory 195124 kb
Host smart-9e7bb3ab-8a7f-4022-bfc5-581903257ced
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687536242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1687536242
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.150341744
Short name T773
Test name
Test status
Simulation time 17193709 ps
CPU time 0.64 seconds
Started Aug 09 07:01:41 PM PDT 24
Finished Aug 09 07:01:41 PM PDT 24
Peak memory 194588 kb
Host smart-d73c5d33-879d-4675-b66b-d74e76e4b19b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150341744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.150341744
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.1926921263
Short name T788
Test name
Test status
Simulation time 146418753 ps
CPU time 0.64 seconds
Started Aug 09 07:01:40 PM PDT 24
Finished Aug 09 07:01:41 PM PDT 24
Peak memory 195232 kb
Host smart-d550bf28-8515-4c22-9544-000f1524efa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926921263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.1926921263
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.1929208032
Short name T823
Test name
Test status
Simulation time 12460051 ps
CPU time 0.58 seconds
Started Aug 09 07:01:37 PM PDT 24
Finished Aug 09 07:01:38 PM PDT 24
Peak memory 194408 kb
Host smart-2431b561-deb4-4da5-ac2f-9616e955a383
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929208032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1929208032
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.4231074576
Short name T766
Test name
Test status
Simulation time 30473441 ps
CPU time 0.58 seconds
Started Aug 09 07:01:38 PM PDT 24
Finished Aug 09 07:01:39 PM PDT 24
Peak memory 194460 kb
Host smart-38f73586-f809-4096-8554-351835eea186
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231074576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.4231074576
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1742549914
Short name T736
Test name
Test status
Simulation time 17060826 ps
CPU time 0.62 seconds
Started Aug 09 07:01:40 PM PDT 24
Finished Aug 09 07:01:41 PM PDT 24
Peak memory 194520 kb
Host smart-538263b3-efcc-448c-be0a-75e614d0dab1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742549914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1742549914
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.1088508746
Short name T777
Test name
Test status
Simulation time 12256796 ps
CPU time 0.64 seconds
Started Aug 09 07:01:40 PM PDT 24
Finished Aug 09 07:01:41 PM PDT 24
Peak memory 194492 kb
Host smart-41b67b71-cde3-42c4-8ae5-e92080e732d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088508746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.1088508746
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.2578037109
Short name T776
Test name
Test status
Simulation time 12436157 ps
CPU time 0.59 seconds
Started Aug 09 07:01:37 PM PDT 24
Finished Aug 09 07:01:38 PM PDT 24
Peak memory 194476 kb
Host smart-09f2aeee-01bb-4a48-9557-71e32a75c830
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578037109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.2578037109
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.953626667
Short name T787
Test name
Test status
Simulation time 34346875 ps
CPU time 0.58 seconds
Started Aug 09 07:01:38 PM PDT 24
Finished Aug 09 07:01:38 PM PDT 24
Peak memory 194484 kb
Host smart-6b99582a-48b8-499d-bcbb-323ebb184dd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953626667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.953626667
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.1759391844
Short name T730
Test name
Test status
Simulation time 53743297 ps
CPU time 0.58 seconds
Started Aug 09 07:01:45 PM PDT 24
Finished Aug 09 07:01:46 PM PDT 24
Peak memory 194488 kb
Host smart-3caf7371-327b-4738-b3e9-9d525b0d061e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759391844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.1759391844
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1621351998
Short name T838
Test name
Test status
Simulation time 58019716 ps
CPU time 1.46 seconds
Started Aug 09 07:01:13 PM PDT 24
Finished Aug 09 07:01:14 PM PDT 24
Peak memory 198772 kb
Host smart-dab4cbf8-fe99-495c-bb8a-d4df5f7f2f2d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621351998 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1621351998
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.786641415
Short name T750
Test name
Test status
Simulation time 22230746 ps
CPU time 0.56 seconds
Started Aug 09 07:01:10 PM PDT 24
Finished Aug 09 07:01:11 PM PDT 24
Peak memory 195256 kb
Host smart-931aea9d-a139-49dc-a4dd-7e572055136a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786641415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_
csr_rw.786641415
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.2058890844
Short name T799
Test name
Test status
Simulation time 22882029 ps
CPU time 0.62 seconds
Started Aug 09 07:01:09 PM PDT 24
Finished Aug 09 07:01:10 PM PDT 24
Peak memory 194528 kb
Host smart-ca0ea7b8-c45f-4d96-bf55-22dbafb79d05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058890844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.2058890844
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3196530709
Short name T829
Test name
Test status
Simulation time 39385084 ps
CPU time 0.85 seconds
Started Aug 09 07:01:13 PM PDT 24
Finished Aug 09 07:01:14 PM PDT 24
Peak memory 197484 kb
Host smart-85761499-fe28-4500-a623-eea438cfb545
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196530709 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.3196530709
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.240042162
Short name T762
Test name
Test status
Simulation time 74640725 ps
CPU time 0.93 seconds
Started Aug 09 07:01:13 PM PDT 24
Finished Aug 09 07:01:14 PM PDT 24
Peak memory 198596 kb
Host smart-50d096e7-6422-48c9-b87e-fea7b7050f80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240042162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.240042162
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2116972078
Short name T42
Test name
Test status
Simulation time 227088532 ps
CPU time 1.43 seconds
Started Aug 09 07:01:10 PM PDT 24
Finished Aug 09 07:01:11 PM PDT 24
Peak memory 198716 kb
Host smart-862a4338-01c3-46e6-901a-73bc446c97e1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116972078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.2116972078
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2876906553
Short name T828
Test name
Test status
Simulation time 41138153 ps
CPU time 0.99 seconds
Started Aug 09 07:01:10 PM PDT 24
Finished Aug 09 07:01:12 PM PDT 24
Peak memory 198656 kb
Host smart-406cb277-63c3-4d29-b77c-46c375fb0d56
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876906553 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2876906553
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3069901463
Short name T87
Test name
Test status
Simulation time 17161163 ps
CPU time 0.57 seconds
Started Aug 09 07:01:12 PM PDT 24
Finished Aug 09 07:01:13 PM PDT 24
Peak memory 194008 kb
Host smart-ba67664b-e56b-4d1a-a129-e209d59a09ed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069901463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.3069901463
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.3043032805
Short name T845
Test name
Test status
Simulation time 16452659 ps
CPU time 0.63 seconds
Started Aug 09 07:01:14 PM PDT 24
Finished Aug 09 07:01:14 PM PDT 24
Peak memory 194504 kb
Host smart-ec1f792f-c50a-400d-aeae-6aa697190ceb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043032805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3043032805
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2453696898
Short name T812
Test name
Test status
Simulation time 35415299 ps
CPU time 0.94 seconds
Started Aug 09 07:01:11 PM PDT 24
Finished Aug 09 07:01:12 PM PDT 24
Peak memory 198576 kb
Host smart-eaeef2c8-ab96-478f-aa6a-94755bfabafa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453696898 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.2453696898
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.3166091464
Short name T752
Test name
Test status
Simulation time 24983532 ps
CPU time 1.12 seconds
Started Aug 09 07:01:13 PM PDT 24
Finished Aug 09 07:01:14 PM PDT 24
Peak memory 198740 kb
Host smart-ad2c0f78-5d4b-4ea5-94d7-e4c4260fa7cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166091464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.3166091464
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.335302461
Short name T110
Test name
Test status
Simulation time 75729598 ps
CPU time 1.07 seconds
Started Aug 09 07:01:10 PM PDT 24
Finished Aug 09 07:01:11 PM PDT 24
Peak memory 198724 kb
Host smart-5f6dea33-0c0d-438a-afd4-18ac6270c032
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335302461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.gpio_tl_intg_err.335302461
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.4229291469
Short name T807
Test name
Test status
Simulation time 58574378 ps
CPU time 1.35 seconds
Started Aug 09 07:01:11 PM PDT 24
Finished Aug 09 07:01:12 PM PDT 24
Peak memory 198804 kb
Host smart-165d5d9a-3c13-4276-b263-bcabb881fe28
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229291469 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.4229291469
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1328628112
Short name T91
Test name
Test status
Simulation time 104320746 ps
CPU time 0.59 seconds
Started Aug 09 07:01:11 PM PDT 24
Finished Aug 09 07:01:12 PM PDT 24
Peak memory 195552 kb
Host smart-f4a648ea-3e34-4797-ae79-b78fbdbaad19
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328628112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1328628112
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.3495141213
Short name T842
Test name
Test status
Simulation time 12178194 ps
CPU time 0.62 seconds
Started Aug 09 07:01:11 PM PDT 24
Finished Aug 09 07:01:12 PM PDT 24
Peak memory 194576 kb
Host smart-b07a119c-8db0-443c-9ecc-fdc64159f457
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495141213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.3495141213
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.4185177830
Short name T106
Test name
Test status
Simulation time 22248862 ps
CPU time 0.64 seconds
Started Aug 09 07:01:11 PM PDT 24
Finished Aug 09 07:01:12 PM PDT 24
Peak memory 195820 kb
Host smart-67f1bf73-a1bb-43a9-b8c1-1462dc4a60ea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185177830 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.4185177830
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3566910129
Short name T836
Test name
Test status
Simulation time 144010231 ps
CPU time 1.95 seconds
Started Aug 09 07:01:11 PM PDT 24
Finished Aug 09 07:01:13 PM PDT 24
Peak memory 198752 kb
Host smart-1ab8fcb3-f634-4f52-9f44-06e1c368391a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566910129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3566910129
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2636728207
Short name T33
Test name
Test status
Simulation time 167013952 ps
CPU time 1.16 seconds
Started Aug 09 07:01:10 PM PDT 24
Finished Aug 09 07:01:11 PM PDT 24
Peak memory 198684 kb
Host smart-cd75caee-9601-439e-b967-04b5bf6fd3a7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636728207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.2636728207
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3626835012
Short name T830
Test name
Test status
Simulation time 42584046 ps
CPU time 1.09 seconds
Started Aug 09 07:01:10 PM PDT 24
Finished Aug 09 07:01:11 PM PDT 24
Peak memory 198652 kb
Host smart-671c726b-30a2-47a8-b488-086238f27fc8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626835012 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3626835012
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.173161241
Short name T801
Test name
Test status
Simulation time 137519101 ps
CPU time 0.6 seconds
Started Aug 09 07:01:12 PM PDT 24
Finished Aug 09 07:01:13 PM PDT 24
Peak memory 196004 kb
Host smart-b58533a4-a0c5-402c-ac9e-4d2ec0a25e62
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173161241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_
csr_rw.173161241
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.1078976596
Short name T803
Test name
Test status
Simulation time 165606667 ps
CPU time 0.6 seconds
Started Aug 09 07:01:18 PM PDT 24
Finished Aug 09 07:01:19 PM PDT 24
Peak memory 195156 kb
Host smart-8e4c425c-3f1e-4e5f-b7ef-495c9b312e9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078976596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.1078976596
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2326645369
Short name T820
Test name
Test status
Simulation time 66794994 ps
CPU time 0.8 seconds
Started Aug 09 07:01:10 PM PDT 24
Finished Aug 09 07:01:10 PM PDT 24
Peak memory 196768 kb
Host smart-fb2c9298-274f-468e-a4ac-fbb1ae606127
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326645369 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.2326645369
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1333784032
Short name T782
Test name
Test status
Simulation time 245029052 ps
CPU time 1.41 seconds
Started Aug 09 07:01:19 PM PDT 24
Finished Aug 09 07:01:21 PM PDT 24
Peak memory 198856 kb
Host smart-976ce4b3-5b6e-4bc7-a687-52cae2405960
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333784032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.1333784032
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1081687946
Short name T31
Test name
Test status
Simulation time 461974224 ps
CPU time 1.34 seconds
Started Aug 09 07:01:18 PM PDT 24
Finished Aug 09 07:01:20 PM PDT 24
Peak memory 198816 kb
Host smart-e0969eda-9796-49ff-ac42-29acd7492f85
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081687946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.1081687946
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2569292063
Short name T751
Test name
Test status
Simulation time 21512065 ps
CPU time 0.78 seconds
Started Aug 09 07:01:19 PM PDT 24
Finished Aug 09 07:01:20 PM PDT 24
Peak memory 198608 kb
Host smart-b10d6d1f-5f33-4ca9-b74a-4dc54778e493
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569292063 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.2569292063
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3011056664
Short name T89
Test name
Test status
Simulation time 44393975 ps
CPU time 0.62 seconds
Started Aug 09 07:01:19 PM PDT 24
Finished Aug 09 07:01:20 PM PDT 24
Peak memory 196112 kb
Host smart-3e9ab476-8822-4736-90a6-53a9c69b827a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011056664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3011056664
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.1434077637
Short name T783
Test name
Test status
Simulation time 20093272 ps
CPU time 0.6 seconds
Started Aug 09 07:01:20 PM PDT 24
Finished Aug 09 07:01:21 PM PDT 24
Peak memory 195116 kb
Host smart-66d79107-c496-434c-932e-7961bedd9c85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434077637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.1434077637
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.785458904
Short name T104
Test name
Test status
Simulation time 122862654 ps
CPU time 0.61 seconds
Started Aug 09 07:01:19 PM PDT 24
Finished Aug 09 07:01:20 PM PDT 24
Peak memory 195880 kb
Host smart-a09790af-035c-49dd-b757-5ec1d495c3bd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785458904 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 9.gpio_same_csr_outstanding.785458904
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3954894053
Short name T765
Test name
Test status
Simulation time 182734270 ps
CPU time 1.72 seconds
Started Aug 09 07:01:18 PM PDT 24
Finished Aug 09 07:01:20 PM PDT 24
Peak memory 198788 kb
Host smart-ce3eb49c-4939-4fa3-9a03-978d2c5db642
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954894053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.3954894053
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.2283473770
Short name T682
Test name
Test status
Simulation time 164870553 ps
CPU time 0.68 seconds
Started Aug 09 07:02:04 PM PDT 24
Finished Aug 09 07:02:05 PM PDT 24
Peak memory 194716 kb
Host smart-4a6361a7-cfa2-4b56-bdad-048f1753d373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283473770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.2283473770
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.3786248173
Short name T394
Test name
Test status
Simulation time 709573346 ps
CPU time 23.24 seconds
Started Aug 09 07:02:04 PM PDT 24
Finished Aug 09 07:02:27 PM PDT 24
Peak memory 197348 kb
Host smart-00460593-50e5-4977-887d-8b33e4b55b61
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786248173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.3786248173
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.1103819081
Short name T287
Test name
Test status
Simulation time 170820351 ps
CPU time 1.04 seconds
Started Aug 09 07:02:05 PM PDT 24
Finished Aug 09 07:02:07 PM PDT 24
Peak memory 197068 kb
Host smart-d71977c5-3f4a-48a9-bd37-13e69d7156ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103819081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1103819081
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2767494232
Short name T206
Test name
Test status
Simulation time 113313089 ps
CPU time 1.13 seconds
Started Aug 09 07:02:04 PM PDT 24
Finished Aug 09 07:02:05 PM PDT 24
Peak memory 197096 kb
Host smart-c2b28675-b43d-4cb9-a845-5dcf9d2e5d91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767494232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2767494232
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.4001559814
Short name T699
Test name
Test status
Simulation time 256396281 ps
CPU time 2.71 seconds
Started Aug 09 07:02:06 PM PDT 24
Finished Aug 09 07:02:08 PM PDT 24
Peak memory 198508 kb
Host smart-b5a7e71e-637d-46df-8bf2-9eea23d9e94e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001559814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.4001559814
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.3826363796
Short name T349
Test name
Test status
Simulation time 136026788 ps
CPU time 2.52 seconds
Started Aug 09 07:02:07 PM PDT 24
Finished Aug 09 07:02:09 PM PDT 24
Peak memory 197764 kb
Host smart-b4664184-28fc-4c14-b994-66f0f6dd772f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826363796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
3826363796
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.2608620005
Short name T722
Test name
Test status
Simulation time 70651962 ps
CPU time 0.91 seconds
Started Aug 09 07:02:06 PM PDT 24
Finished Aug 09 07:02:07 PM PDT 24
Peak memory 197108 kb
Host smart-031266e5-6344-43f7-8dc3-a92c83104d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608620005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.2608620005
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.617525899
Short name T382
Test name
Test status
Simulation time 21041482 ps
CPU time 0.87 seconds
Started Aug 09 07:02:04 PM PDT 24
Finished Aug 09 07:02:05 PM PDT 24
Peak memory 197832 kb
Host smart-cdaedd38-a877-4b11-a80e-cf164c45771e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617525899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_
pulldown.617525899
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.829357955
Short name T649
Test name
Test status
Simulation time 223637849 ps
CPU time 2.25 seconds
Started Aug 09 07:02:08 PM PDT 24
Finished Aug 09 07:02:10 PM PDT 24
Peak memory 198544 kb
Host smart-5cc8bb11-f344-42b6-aefa-a9ca021a4e06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829357955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand
om_long_reg_writes_reg_reads.829357955
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.2608794922
Short name T47
Test name
Test status
Simulation time 115875975 ps
CPU time 0.87 seconds
Started Aug 09 07:02:08 PM PDT 24
Finished Aug 09 07:02:09 PM PDT 24
Peak memory 214316 kb
Host smart-d5732d02-17c2-4488-8b0f-420a73fcc2c7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608794922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2608794922
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.2595841943
Short name T566
Test name
Test status
Simulation time 1557686534 ps
CPU time 1.43 seconds
Started Aug 09 07:02:05 PM PDT 24
Finished Aug 09 07:02:07 PM PDT 24
Peak memory 196128 kb
Host smart-addb9ef9-e7b6-4490-9795-da24204d738e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595841943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.2595841943
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.2309000720
Short name T644
Test name
Test status
Simulation time 68007024 ps
CPU time 1.27 seconds
Started Aug 09 07:02:04 PM PDT 24
Finished Aug 09 07:02:05 PM PDT 24
Peak memory 198536 kb
Host smart-38069f7f-3c20-4ddf-b1dd-bc20f346499f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309000720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.2309000720
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.2902851723
Short name T661
Test name
Test status
Simulation time 57045158719 ps
CPU time 79.37 seconds
Started Aug 09 07:02:07 PM PDT 24
Finished Aug 09 07:03:27 PM PDT 24
Peak memory 198756 kb
Host smart-cd4fe07a-e080-495d-a536-2d20790cc2aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902851723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.2902851723
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.1644057903
Short name T78
Test name
Test status
Simulation time 20413940 ps
CPU time 0.58 seconds
Started Aug 09 07:02:17 PM PDT 24
Finished Aug 09 07:02:18 PM PDT 24
Peak memory 195188 kb
Host smart-f70fcf6e-dfca-468d-a786-279cfd86b3c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644057903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.1644057903
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3428360527
Short name T218
Test name
Test status
Simulation time 63820977 ps
CPU time 0.68 seconds
Started Aug 09 07:02:16 PM PDT 24
Finished Aug 09 07:02:17 PM PDT 24
Peak memory 194620 kb
Host smart-40b24f78-b59a-4285-a80e-cad5cd9004c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428360527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3428360527
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.91345855
Short name T199
Test name
Test status
Simulation time 497280843 ps
CPU time 9.38 seconds
Started Aug 09 07:02:14 PM PDT 24
Finished Aug 09 07:02:24 PM PDT 24
Peak memory 197192 kb
Host smart-41128ec4-0d98-4a73-824a-8bc7b59693eb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91345855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress.91345855
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1106704467
Short name T319
Test name
Test status
Simulation time 102750558 ps
CPU time 1.08 seconds
Started Aug 09 07:02:16 PM PDT 24
Finished Aug 09 07:02:17 PM PDT 24
Peak memory 197260 kb
Host smart-73492d7a-009b-4aaf-88ef-9e4732c0f4f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106704467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1106704467
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1334270354
Short name T320
Test name
Test status
Simulation time 21719013 ps
CPU time 0.67 seconds
Started Aug 09 07:02:16 PM PDT 24
Finished Aug 09 07:02:16 PM PDT 24
Peak memory 194736 kb
Host smart-422f8544-46d1-4096-a4e3-69ba4f9938f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334270354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1334270354
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.3360479414
Short name T656
Test name
Test status
Simulation time 60706508 ps
CPU time 2.01 seconds
Started Aug 09 07:02:16 PM PDT 24
Finished Aug 09 07:02:18 PM PDT 24
Peak memory 198824 kb
Host smart-77ce9614-4a65-40e5-9ded-88ae9179c850
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360479414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.3360479414
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.4163210544
Short name T122
Test name
Test status
Simulation time 91461989 ps
CPU time 1.17 seconds
Started Aug 09 07:02:17 PM PDT 24
Finished Aug 09 07:02:18 PM PDT 24
Peak memory 196884 kb
Host smart-4cd060e2-37e2-4dfb-aed4-14bf256ab6cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163210544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
4163210544
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2128190672
Short name T469
Test name
Test status
Simulation time 213240108 ps
CPU time 1.04 seconds
Started Aug 09 07:02:14 PM PDT 24
Finished Aug 09 07:02:15 PM PDT 24
Peak memory 196576 kb
Host smart-1049c683-8fb4-479d-b61b-7b2b6e3a6cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128190672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2128190672
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2938256840
Short name T131
Test name
Test status
Simulation time 33895357 ps
CPU time 0.75 seconds
Started Aug 09 07:02:15 PM PDT 24
Finished Aug 09 07:02:16 PM PDT 24
Peak memory 196036 kb
Host smart-db97fde5-84fc-4aeb-8535-fca884b57337
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938256840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2938256840
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.4173537141
Short name T698
Test name
Test status
Simulation time 5018264116 ps
CPU time 5.1 seconds
Started Aug 09 07:02:17 PM PDT 24
Finished Aug 09 07:02:22 PM PDT 24
Peak memory 198424 kb
Host smart-9afa5d05-37e5-4493-9a0b-0aca727f865e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173537141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.4173537141
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_smoke.3814237361
Short name T293
Test name
Test status
Simulation time 68259625 ps
CPU time 0.86 seconds
Started Aug 09 07:02:08 PM PDT 24
Finished Aug 09 07:02:09 PM PDT 24
Peak memory 195892 kb
Host smart-842e9f9a-407c-43bd-8710-6096464fad54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814237361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3814237361
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.3759399034
Short name T719
Test name
Test status
Simulation time 75438589 ps
CPU time 1.41 seconds
Started Aug 09 07:02:06 PM PDT 24
Finished Aug 09 07:02:08 PM PDT 24
Peak memory 198592 kb
Host smart-43e9927f-0b73-4db4-a3f8-aadb878cf425
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759399034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.3759399034
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.4125078574
Short name T10
Test name
Test status
Simulation time 8563173271 ps
CPU time 109.04 seconds
Started Aug 09 07:02:18 PM PDT 24
Finished Aug 09 07:04:07 PM PDT 24
Peak memory 198760 kb
Host smart-82192e78-e87a-49bb-9c8a-34a04f8e4c97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125078574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.4125078574
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.94065809
Short name T302
Test name
Test status
Simulation time 16599586 ps
CPU time 0.58 seconds
Started Aug 09 07:02:32 PM PDT 24
Finished Aug 09 07:02:33 PM PDT 24
Peak memory 195192 kb
Host smart-e524c2d1-d4bf-4efc-a64c-f620ff0d0c7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94065809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.94065809
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1192293026
Short name T431
Test name
Test status
Simulation time 22777660 ps
CPU time 0.78 seconds
Started Aug 09 07:02:33 PM PDT 24
Finished Aug 09 07:02:34 PM PDT 24
Peak memory 195752 kb
Host smart-a3eed2b5-eabb-4b45-961e-f8467a9886d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192293026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1192293026
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.3410304135
Short name T564
Test name
Test status
Simulation time 1017477106 ps
CPU time 28.07 seconds
Started Aug 09 07:02:35 PM PDT 24
Finished Aug 09 07:03:03 PM PDT 24
Peak memory 197320 kb
Host smart-f98b8c60-7eea-466a-8f9a-4cd5ea9a73a7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410304135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.3410304135
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.3662367042
Short name T187
Test name
Test status
Simulation time 136728147 ps
CPU time 0.88 seconds
Started Aug 09 07:02:33 PM PDT 24
Finished Aug 09 07:02:34 PM PDT 24
Peak memory 196920 kb
Host smart-c7695795-c6a6-45e8-9bc9-b84cb874077e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662367042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.3662367042
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.3803699213
Short name T657
Test name
Test status
Simulation time 376618081 ps
CPU time 1.35 seconds
Started Aug 09 07:02:34 PM PDT 24
Finished Aug 09 07:02:35 PM PDT 24
Peak memory 197724 kb
Host smart-bd12c7a0-d020-474d-b3a5-5142b7c16cb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803699213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.3803699213
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3448947114
Short name T225
Test name
Test status
Simulation time 89869041 ps
CPU time 3.47 seconds
Started Aug 09 07:02:32 PM PDT 24
Finished Aug 09 07:02:36 PM PDT 24
Peak memory 198592 kb
Host smart-5733c71a-6aec-43eb-bfe3-0c85ffc66743
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448947114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3448947114
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.3522779965
Short name T429
Test name
Test status
Simulation time 52518989 ps
CPU time 1.76 seconds
Started Aug 09 07:02:33 PM PDT 24
Finished Aug 09 07:02:35 PM PDT 24
Peak memory 197292 kb
Host smart-3f39c3c8-b676-4a71-9ca5-2446f5bc2054
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522779965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.3522779965
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.3670946852
Short name T536
Test name
Test status
Simulation time 37507720 ps
CPU time 0.89 seconds
Started Aug 09 07:02:35 PM PDT 24
Finished Aug 09 07:02:36 PM PDT 24
Peak memory 196984 kb
Host smart-299ea8e5-7449-4346-8f8c-7e288ad0dbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670946852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.3670946852
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.251698002
Short name T347
Test name
Test status
Simulation time 535658963 ps
CPU time 1.29 seconds
Started Aug 09 07:02:33 PM PDT 24
Finished Aug 09 07:02:34 PM PDT 24
Peak memory 197540 kb
Host smart-f910582d-8a43-44e3-af67-db8e7bbbd00c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251698002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup
_pulldown.251698002
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1084748631
Short name T26
Test name
Test status
Simulation time 41189760 ps
CPU time 2 seconds
Started Aug 09 07:02:30 PM PDT 24
Finished Aug 09 07:02:32 PM PDT 24
Peak memory 198492 kb
Host smart-34a39bda-953d-4510-ac0e-ddfcdd19b1b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084748631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1084748631
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.2597683027
Short name T359
Test name
Test status
Simulation time 28130567 ps
CPU time 0.89 seconds
Started Aug 09 07:02:33 PM PDT 24
Finished Aug 09 07:02:34 PM PDT 24
Peak memory 197312 kb
Host smart-726a3a74-d608-4186-847a-2a91d5102eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597683027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.2597683027
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.146411149
Short name T720
Test name
Test status
Simulation time 77621781 ps
CPU time 1.04 seconds
Started Aug 09 07:02:30 PM PDT 24
Finished Aug 09 07:02:32 PM PDT 24
Peak memory 196368 kb
Host smart-8bbb6660-6186-454b-b19f-69cc87389925
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146411149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.146411149
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.2942578131
Short name T270
Test name
Test status
Simulation time 64387325524 ps
CPU time 219.46 seconds
Started Aug 09 07:02:31 PM PDT 24
Finished Aug 09 07:06:10 PM PDT 24
Peak memory 198732 kb
Host smart-05833936-ab39-4f76-9860-42d0a5fff8e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942578131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.2942578131
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.810799445
Short name T580
Test name
Test status
Simulation time 22115588 ps
CPU time 0.58 seconds
Started Aug 09 07:02:33 PM PDT 24
Finished Aug 09 07:02:34 PM PDT 24
Peak memory 194672 kb
Host smart-28925e54-e2a7-437c-8a15-6b3941ffcd58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810799445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.810799445
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.1728067883
Short name T236
Test name
Test status
Simulation time 41641225 ps
CPU time 0.69 seconds
Started Aug 09 07:02:33 PM PDT 24
Finished Aug 09 07:02:33 PM PDT 24
Peak memory 195292 kb
Host smart-ac2366ca-2dbb-4b27-a29f-41e830d04ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728067883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.1728067883
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1000216813
Short name T68
Test name
Test status
Simulation time 3316306448 ps
CPU time 20.35 seconds
Started Aug 09 07:02:32 PM PDT 24
Finished Aug 09 07:02:53 PM PDT 24
Peak memory 197640 kb
Host smart-a1bfeba5-5109-4cc0-acca-42c18c0d196e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000216813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1000216813
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.2417748281
Short name T20
Test name
Test status
Simulation time 84404783 ps
CPU time 0.95 seconds
Started Aug 09 07:02:33 PM PDT 24
Finished Aug 09 07:02:34 PM PDT 24
Peak memory 197744 kb
Host smart-cf8be3f9-f701-4f81-bfc5-c11aa47c0fd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417748281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.2417748281
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.2426815033
Short name T500
Test name
Test status
Simulation time 241519110 ps
CPU time 0.76 seconds
Started Aug 09 07:02:36 PM PDT 24
Finished Aug 09 07:02:37 PM PDT 24
Peak memory 195840 kb
Host smart-749bb574-ad00-4811-b55e-9cd1bd904859
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426815033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.2426815033
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.2488941734
Short name T268
Test name
Test status
Simulation time 72527292 ps
CPU time 3.03 seconds
Started Aug 09 07:02:33 PM PDT 24
Finished Aug 09 07:02:36 PM PDT 24
Peak memory 198512 kb
Host smart-284351a2-d534-471d-bc18-fdf4c98bb1c8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488941734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.2488941734
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.4032990936
Short name T247
Test name
Test status
Simulation time 396192881 ps
CPU time 1.44 seconds
Started Aug 09 07:02:34 PM PDT 24
Finished Aug 09 07:02:36 PM PDT 24
Peak memory 196784 kb
Host smart-50575ef9-b85c-430a-8cec-2a46ceebdb1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032990936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.4032990936
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.178806910
Short name T374
Test name
Test status
Simulation time 55288742 ps
CPU time 1.2 seconds
Started Aug 09 07:02:32 PM PDT 24
Finished Aug 09 07:02:33 PM PDT 24
Peak memory 197180 kb
Host smart-21cb5ef7-8dd7-42cb-b802-c221189efab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178806910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.178806910
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.211046314
Short name T528
Test name
Test status
Simulation time 72793727 ps
CPU time 0.84 seconds
Started Aug 09 07:02:31 PM PDT 24
Finished Aug 09 07:02:32 PM PDT 24
Peak memory 197288 kb
Host smart-8108e6a8-e72a-4034-9d45-5ee77f33c28c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211046314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullup
_pulldown.211046314
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3270883813
Short name T441
Test name
Test status
Simulation time 199224665 ps
CPU time 2.47 seconds
Started Aug 09 07:02:36 PM PDT 24
Finished Aug 09 07:02:38 PM PDT 24
Peak memory 198468 kb
Host smart-00e21b53-7ded-431b-afa5-1b055723b211
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270883813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.3270883813
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.44559224
Short name T604
Test name
Test status
Simulation time 274206658 ps
CPU time 0.71 seconds
Started Aug 09 07:02:35 PM PDT 24
Finished Aug 09 07:02:35 PM PDT 24
Peak memory 194692 kb
Host smart-4211dcb3-6b3e-4609-83c6-cfb1d3ab98ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44559224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.44559224
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.1045620590
Short name T135
Test name
Test status
Simulation time 22932875 ps
CPU time 0.76 seconds
Started Aug 09 07:02:31 PM PDT 24
Finished Aug 09 07:02:32 PM PDT 24
Peak memory 195792 kb
Host smart-c4185435-2dc9-4a40-bf67-446ef1bdf6e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045620590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.1045620590
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.2675344934
Short name T458
Test name
Test status
Simulation time 13865659457 ps
CPU time 132.47 seconds
Started Aug 09 07:02:35 PM PDT 24
Finished Aug 09 07:04:47 PM PDT 24
Peak memory 198636 kb
Host smart-bca0109c-7226-4689-86af-b61ae6a9689d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675344934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.2675344934
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.2704702757
Short name T710
Test name
Test status
Simulation time 19680890 ps
CPU time 0.55 seconds
Started Aug 09 07:02:44 PM PDT 24
Finished Aug 09 07:02:45 PM PDT 24
Peak memory 194440 kb
Host smart-ad0affe1-332a-454c-ba65-3b3a91cecea2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704702757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.2704702757
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2147831801
Short name T521
Test name
Test status
Simulation time 180578833 ps
CPU time 0.89 seconds
Started Aug 09 07:02:39 PM PDT 24
Finished Aug 09 07:02:40 PM PDT 24
Peak memory 197088 kb
Host smart-624cfd02-f068-4a7c-a5cf-820a9d714af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147831801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2147831801
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.3698724694
Short name T433
Test name
Test status
Simulation time 600301578 ps
CPU time 18.23 seconds
Started Aug 09 07:02:40 PM PDT 24
Finished Aug 09 07:02:58 PM PDT 24
Peak memory 198508 kb
Host smart-efeb5793-6958-487b-bbc9-192b2603d9ab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698724694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.3698724694
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.2775539350
Short name T276
Test name
Test status
Simulation time 82293813 ps
CPU time 0.71 seconds
Started Aug 09 07:02:41 PM PDT 24
Finished Aug 09 07:02:41 PM PDT 24
Peak memory 195304 kb
Host smart-b268c0dc-3a3f-47b5-8e73-ed16f2b7cf70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775539350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.2775539350
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.953620839
Short name T498
Test name
Test status
Simulation time 38071134 ps
CPU time 1.04 seconds
Started Aug 09 07:02:40 PM PDT 24
Finished Aug 09 07:02:41 PM PDT 24
Peak memory 196392 kb
Host smart-81831fbf-1db7-41de-b267-5bd48b7f80d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953620839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.953620839
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.1338587377
Short name T537
Test name
Test status
Simulation time 125356327 ps
CPU time 2.87 seconds
Started Aug 09 07:02:38 PM PDT 24
Finished Aug 09 07:02:41 PM PDT 24
Peak memory 198724 kb
Host smart-9a9c7b21-97bc-40bb-9d5b-78e27e4d3a71
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338587377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.1338587377
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1599743432
Short name T179
Test name
Test status
Simulation time 321109183 ps
CPU time 1.95 seconds
Started Aug 09 07:02:39 PM PDT 24
Finished Aug 09 07:02:41 PM PDT 24
Peak memory 196572 kb
Host smart-618f4ec8-12ae-4fca-a546-2030cf0a37f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599743432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1599743432
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.1149208476
Short name T446
Test name
Test status
Simulation time 660789840 ps
CPU time 1.13 seconds
Started Aug 09 07:02:42 PM PDT 24
Finished Aug 09 07:02:43 PM PDT 24
Peak memory 196660 kb
Host smart-4b0529a2-e1dc-4e61-97f3-52b8f2be00f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149208476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.1149208476
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.1210804300
Short name T203
Test name
Test status
Simulation time 162604283 ps
CPU time 0.98 seconds
Started Aug 09 07:02:40 PM PDT 24
Finished Aug 09 07:02:41 PM PDT 24
Peak memory 197328 kb
Host smart-d658a0fa-6594-4ef2-a908-dfe30c35cd27
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210804300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.1210804300
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2407052437
Short name T258
Test name
Test status
Simulation time 555880843 ps
CPU time 4.73 seconds
Started Aug 09 07:02:39 PM PDT 24
Finished Aug 09 07:02:44 PM PDT 24
Peak memory 198584 kb
Host smart-db08a880-942f-4dc8-9796-0a203f244358
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407052437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2407052437
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.2288633145
Short name T697
Test name
Test status
Simulation time 50707490 ps
CPU time 1.06 seconds
Started Aug 09 07:02:40 PM PDT 24
Finished Aug 09 07:02:41 PM PDT 24
Peak memory 196964 kb
Host smart-84d91c2e-d758-4266-8c8a-daa39d0e350a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288633145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.2288633145
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2004796744
Short name T408
Test name
Test status
Simulation time 547048726 ps
CPU time 0.83 seconds
Started Aug 09 07:02:44 PM PDT 24
Finished Aug 09 07:02:45 PM PDT 24
Peak memory 195968 kb
Host smart-1f97f3dd-7cc0-400a-9f6a-d9192d9f32d9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004796744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2004796744
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.1572288324
Short name T129
Test name
Test status
Simulation time 6505752698 ps
CPU time 89.78 seconds
Started Aug 09 07:02:47 PM PDT 24
Finished Aug 09 07:04:16 PM PDT 24
Peak memory 198776 kb
Host smart-cc5ba601-d9c2-4b3e-8403-05fd94fe1292
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572288324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.1572288324
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.4142478001
Short name T354
Test name
Test status
Simulation time 76602999417 ps
CPU time 1741.89 seconds
Started Aug 09 07:02:43 PM PDT 24
Finished Aug 09 07:31:45 PM PDT 24
Peak memory 198836 kb
Host smart-fd9bc413-ebe5-496e-8dce-96f743b50b09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4142478001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.4142478001
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.825266432
Short name T525
Test name
Test status
Simulation time 15579057 ps
CPU time 0.62 seconds
Started Aug 09 07:02:41 PM PDT 24
Finished Aug 09 07:02:42 PM PDT 24
Peak memory 194928 kb
Host smart-02832c3d-14f5-4702-b66c-6fd15bceaf61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825266432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.825266432
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.2921150551
Short name T181
Test name
Test status
Simulation time 120058669 ps
CPU time 0.86 seconds
Started Aug 09 07:02:43 PM PDT 24
Finished Aug 09 07:02:44 PM PDT 24
Peak memory 195952 kb
Host smart-2e8f0f31-046d-4dcf-a723-50e77ce25c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921150551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.2921150551
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.1735432283
Short name T558
Test name
Test status
Simulation time 461100978 ps
CPU time 13.63 seconds
Started Aug 09 07:02:42 PM PDT 24
Finished Aug 09 07:02:56 PM PDT 24
Peak memory 197368 kb
Host smart-8e018c8c-ee0b-4d41-820d-71d502790d79
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735432283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.1735432283
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.1573601391
Short name T555
Test name
Test status
Simulation time 1045231646 ps
CPU time 0.88 seconds
Started Aug 09 07:02:42 PM PDT 24
Finished Aug 09 07:02:43 PM PDT 24
Peak memory 197160 kb
Host smart-3e84cee6-d8f5-4480-829b-e0e907fa9063
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573601391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1573601391
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.667556453
Short name T222
Test name
Test status
Simulation time 262461008 ps
CPU time 1.06 seconds
Started Aug 09 07:02:43 PM PDT 24
Finished Aug 09 07:02:44 PM PDT 24
Peak memory 196320 kb
Host smart-d998e2e1-f34e-4a48-87b4-1964e88d44de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667556453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.667556453
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.1543863446
Short name T388
Test name
Test status
Simulation time 335100803 ps
CPU time 2.11 seconds
Started Aug 09 07:02:42 PM PDT 24
Finished Aug 09 07:02:44 PM PDT 24
Peak memory 197096 kb
Host smart-6d5c45cb-4d53-4082-a1f0-a214281950e6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543863446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.1543863446
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.674904454
Short name T358
Test name
Test status
Simulation time 307589434 ps
CPU time 2.69 seconds
Started Aug 09 07:02:41 PM PDT 24
Finished Aug 09 07:02:43 PM PDT 24
Peak memory 197724 kb
Host smart-290d0631-0d78-4b19-aa69-622bd0bf7d60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674904454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.
674904454
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.115437428
Short name T210
Test name
Test status
Simulation time 148944589 ps
CPU time 1.23 seconds
Started Aug 09 07:02:41 PM PDT 24
Finished Aug 09 07:02:42 PM PDT 24
Peak memory 197520 kb
Host smart-87ee15de-5e5d-4d98-b052-14d16f6a63a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115437428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.115437428
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.1687030305
Short name T510
Test name
Test status
Simulation time 38110793 ps
CPU time 0.94 seconds
Started Aug 09 07:02:40 PM PDT 24
Finished Aug 09 07:02:41 PM PDT 24
Peak memory 196568 kb
Host smart-b577f012-19b4-421c-b3f9-aac729361d57
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687030305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.1687030305
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.961900654
Short name T718
Test name
Test status
Simulation time 2139839030 ps
CPU time 3.79 seconds
Started Aug 09 07:02:42 PM PDT 24
Finished Aug 09 07:02:46 PM PDT 24
Peak memory 198504 kb
Host smart-d02957ff-eba2-41d4-bbff-088327dc2492
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961900654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ran
dom_long_reg_writes_reg_reads.961900654
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2831220453
Short name T516
Test name
Test status
Simulation time 53184092 ps
CPU time 0.9 seconds
Started Aug 09 07:02:41 PM PDT 24
Finished Aug 09 07:02:42 PM PDT 24
Peak memory 196404 kb
Host smart-93e14a93-2675-4d83-840a-9f8010ab51f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831220453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2831220453
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.2936615105
Short name T449
Test name
Test status
Simulation time 44632593 ps
CPU time 1.15 seconds
Started Aug 09 07:02:40 PM PDT 24
Finished Aug 09 07:02:42 PM PDT 24
Peak memory 196448 kb
Host smart-682e789d-4940-4c4c-8fa7-11e869f8d434
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936615105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.2936615105
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1646117816
Short name T437
Test name
Test status
Simulation time 49793229966 ps
CPU time 169.99 seconds
Started Aug 09 07:02:42 PM PDT 24
Finished Aug 09 07:05:33 PM PDT 24
Peak memory 198652 kb
Host smart-00adb590-9a6e-446a-ac81-45f6763fd0bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646117816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1646117816
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.111193756
Short name T633
Test name
Test status
Simulation time 101731066 ps
CPU time 0.61 seconds
Started Aug 09 07:02:40 PM PDT 24
Finished Aug 09 07:02:40 PM PDT 24
Peak memory 195324 kb
Host smart-85f533a9-1312-4f5e-8307-e12ebbefdc77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111193756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.111193756
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.556584395
Short name T618
Test name
Test status
Simulation time 31374694 ps
CPU time 0.63 seconds
Started Aug 09 07:02:43 PM PDT 24
Finished Aug 09 07:02:43 PM PDT 24
Peak memory 194552 kb
Host smart-a8b29fd2-c9f5-46c6-b0ae-d238ed53fc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556584395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.556584395
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.3208645100
Short name T392
Test name
Test status
Simulation time 351995714 ps
CPU time 12.09 seconds
Started Aug 09 07:02:43 PM PDT 24
Finished Aug 09 07:02:56 PM PDT 24
Peak memory 197468 kb
Host smart-8680dab3-f498-4c57-98e8-36baf5bc1d69
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208645100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.3208645100
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.3261729943
Short name T6
Test name
Test status
Simulation time 107384473 ps
CPU time 0.6 seconds
Started Aug 09 07:02:40 PM PDT 24
Finished Aug 09 07:02:41 PM PDT 24
Peak memory 194904 kb
Host smart-ed3dafc3-af93-4691-96ef-98b17b64544a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261729943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.3261729943
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2427149685
Short name T56
Test name
Test status
Simulation time 107567441 ps
CPU time 0.88 seconds
Started Aug 09 07:02:40 PM PDT 24
Finished Aug 09 07:02:41 PM PDT 24
Peak memory 197336 kb
Host smart-4a8e34e6-3775-415a-9213-43dde6277e1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427149685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2427149685
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.4100177633
Short name T596
Test name
Test status
Simulation time 155044224 ps
CPU time 1.75 seconds
Started Aug 09 07:02:40 PM PDT 24
Finished Aug 09 07:02:42 PM PDT 24
Peak memory 198592 kb
Host smart-b74d8f10-540c-4057-9b0d-87fc4a677767
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100177633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.4100177633
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.2643252399
Short name T307
Test name
Test status
Simulation time 111203012 ps
CPU time 1.8 seconds
Started Aug 09 07:02:41 PM PDT 24
Finished Aug 09 07:02:43 PM PDT 24
Peak memory 197196 kb
Host smart-464cdbf9-f854-46c7-aea3-f26fc842d8a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643252399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.2643252399
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.3852617991
Short name T277
Test name
Test status
Simulation time 18356383 ps
CPU time 0.67 seconds
Started Aug 09 07:02:41 PM PDT 24
Finished Aug 09 07:02:42 PM PDT 24
Peak memory 194780 kb
Host smart-3c5b43fa-7b7e-469f-b63b-e24579efed07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852617991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3852617991
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.4037418171
Short name T295
Test name
Test status
Simulation time 20251793 ps
CPU time 0.65 seconds
Started Aug 09 07:02:41 PM PDT 24
Finished Aug 09 07:02:41 PM PDT 24
Peak memory 194820 kb
Host smart-442f3f1e-8950-491a-8326-794199353f9b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037418171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.4037418171
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.1738794217
Short name T197
Test name
Test status
Simulation time 754050127 ps
CPU time 6.26 seconds
Started Aug 09 07:02:39 PM PDT 24
Finished Aug 09 07:02:46 PM PDT 24
Peak memory 198524 kb
Host smart-30326ec8-5254-46a1-8621-0d0ee44664d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738794217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.1738794217
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.831784552
Short name T455
Test name
Test status
Simulation time 61873722 ps
CPU time 1.16 seconds
Started Aug 09 07:02:38 PM PDT 24
Finished Aug 09 07:02:39 PM PDT 24
Peak memory 196952 kb
Host smart-2a39a115-f6c7-4d0d-b6ac-47a2c21ed95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831784552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.831784552
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.43756173
Short name T355
Test name
Test status
Simulation time 62689578 ps
CPU time 1.18 seconds
Started Aug 09 07:02:43 PM PDT 24
Finished Aug 09 07:02:45 PM PDT 24
Peak memory 196304 kb
Host smart-de54f33d-9a8d-4508-aab0-db2b0f599fa5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43756173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.43756173
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2203410359
Short name T422
Test name
Test status
Simulation time 31670157576 ps
CPU time 121.18 seconds
Started Aug 09 07:02:43 PM PDT 24
Finished Aug 09 07:04:45 PM PDT 24
Peak memory 198728 kb
Host smart-4fcaf9ed-6cd7-4e70-a1b1-720697d42d86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203410359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2203410359
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.4196181629
Short name T574
Test name
Test status
Simulation time 41112512 ps
CPU time 0.57 seconds
Started Aug 09 07:02:46 PM PDT 24
Finished Aug 09 07:02:47 PM PDT 24
Peak memory 195168 kb
Host smart-b912d4d3-5765-4430-b5a4-1526a97e267c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196181629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.4196181629
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.3860142048
Short name T25
Test name
Test status
Simulation time 75569017 ps
CPU time 0.79 seconds
Started Aug 09 07:02:43 PM PDT 24
Finished Aug 09 07:02:44 PM PDT 24
Peak memory 195772 kb
Host smart-f465c962-c2b0-456e-aa13-f351ea208980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860142048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.3860142048
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2820282072
Short name T488
Test name
Test status
Simulation time 5073082646 ps
CPU time 23.64 seconds
Started Aug 09 07:02:49 PM PDT 24
Finished Aug 09 07:03:13 PM PDT 24
Peak memory 197392 kb
Host smart-58a1206e-38c8-4a90-9a5e-dddb9e041f66
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820282072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2820282072
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.4190733978
Short name T256
Test name
Test status
Simulation time 54617515 ps
CPU time 0.85 seconds
Started Aug 09 07:02:48 PM PDT 24
Finished Aug 09 07:02:49 PM PDT 24
Peak memory 196396 kb
Host smart-50fad9e4-9292-4243-9d0d-de5bbb284671
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190733978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.4190733978
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.3466128119
Short name T484
Test name
Test status
Simulation time 52252572 ps
CPU time 1.4 seconds
Started Aug 09 07:02:40 PM PDT 24
Finished Aug 09 07:02:42 PM PDT 24
Peak memory 196432 kb
Host smart-78d3f8ed-12a5-4961-87ae-474344ffdff5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466128119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.3466128119
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.3195221688
Short name T629
Test name
Test status
Simulation time 84110842 ps
CPU time 3.32 seconds
Started Aug 09 07:02:47 PM PDT 24
Finished Aug 09 07:02:51 PM PDT 24
Peak memory 198668 kb
Host smart-e87c8e9a-bb12-468f-9c7b-c000ad8ed67a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195221688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.3195221688
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.516914261
Short name T357
Test name
Test status
Simulation time 56446566 ps
CPU time 1.81 seconds
Started Aug 09 07:02:47 PM PDT 24
Finished Aug 09 07:02:49 PM PDT 24
Peak memory 197036 kb
Host smart-c61cbcf3-b65e-407a-b81f-5fa319c009d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516914261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger.
516914261
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.464519459
Short name T248
Test name
Test status
Simulation time 362120366 ps
CPU time 0.92 seconds
Started Aug 09 07:02:40 PM PDT 24
Finished Aug 09 07:02:42 PM PDT 24
Peak memory 197108 kb
Host smart-e7445c9a-5673-4c8e-813f-c88e82732bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464519459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.464519459
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.1579276958
Short name T289
Test name
Test status
Simulation time 60204743 ps
CPU time 1.21 seconds
Started Aug 09 07:02:44 PM PDT 24
Finished Aug 09 07:02:45 PM PDT 24
Peak memory 196640 kb
Host smart-7480ea5b-2dff-4aee-9e16-6bf10714c675
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579276958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.1579276958
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.2333480178
Short name T561
Test name
Test status
Simulation time 3858023175 ps
CPU time 6.75 seconds
Started Aug 09 07:02:48 PM PDT 24
Finished Aug 09 07:02:55 PM PDT 24
Peak memory 198684 kb
Host smart-96f1ff99-a6f4-40b8-9a6a-e735422ef2d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333480178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.2333480178
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.1074697339
Short name T188
Test name
Test status
Simulation time 311622163 ps
CPU time 1.1 seconds
Started Aug 09 07:02:43 PM PDT 24
Finished Aug 09 07:02:44 PM PDT 24
Peak memory 196092 kb
Host smart-a4598fb9-ca86-4cff-bb2e-f4ef19844ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074697339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.1074697339
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.3449161414
Short name T571
Test name
Test status
Simulation time 85539891 ps
CPU time 0.98 seconds
Started Aug 09 07:02:43 PM PDT 24
Finished Aug 09 07:02:44 PM PDT 24
Peak memory 196332 kb
Host smart-8dbfbb92-b559-49ad-b448-c04f8d67958d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449161414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.3449161414
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.281209878
Short name T126
Test name
Test status
Simulation time 60341761237 ps
CPU time 211.03 seconds
Started Aug 09 07:02:49 PM PDT 24
Finished Aug 09 07:06:21 PM PDT 24
Peak memory 198704 kb
Host smart-6dbdeb39-fd38-46cd-b383-ced6fe068886
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281209878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.g
pio_stress_all.281209878
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2269731817
Short name T462
Test name
Test status
Simulation time 11976333 ps
CPU time 0.58 seconds
Started Aug 09 07:02:49 PM PDT 24
Finished Aug 09 07:02:49 PM PDT 24
Peak memory 194456 kb
Host smart-667654ad-aedd-4a99-a69b-639fb9c0e4cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269731817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2269731817
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.627195982
Short name T640
Test name
Test status
Simulation time 55050626 ps
CPU time 0.94 seconds
Started Aug 09 07:02:49 PM PDT 24
Finished Aug 09 07:02:50 PM PDT 24
Peak memory 197164 kb
Host smart-c9d4ab45-e7fa-41b3-9960-7380360a9848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627195982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.627195982
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.1280191342
Short name T590
Test name
Test status
Simulation time 1327120157 ps
CPU time 6.5 seconds
Started Aug 09 07:02:48 PM PDT 24
Finished Aug 09 07:02:54 PM PDT 24
Peak memory 198568 kb
Host smart-5c988117-cdd4-4c69-b0e8-bbd32ec288e3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280191342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.1280191342
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.2464858482
Short name T21
Test name
Test status
Simulation time 54788024 ps
CPU time 0.7 seconds
Started Aug 09 07:02:48 PM PDT 24
Finished Aug 09 07:02:49 PM PDT 24
Peak memory 195880 kb
Host smart-84a6c35d-deef-4c61-95b0-2a7a82086b57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464858482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2464858482
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.4210095584
Short name T387
Test name
Test status
Simulation time 138233929 ps
CPU time 1.14 seconds
Started Aug 09 07:02:47 PM PDT 24
Finished Aug 09 07:02:48 PM PDT 24
Peak memory 196648 kb
Host smart-fbe2cb62-3fb3-4bad-834f-140507cdb6e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210095584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.4210095584
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3136232406
Short name T666
Test name
Test status
Simulation time 106837626 ps
CPU time 1.4 seconds
Started Aug 09 07:02:49 PM PDT 24
Finished Aug 09 07:02:50 PM PDT 24
Peak memory 198556 kb
Host smart-c1f5f593-8791-4454-bfca-452440702802
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136232406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3136232406
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.522372863
Short name T305
Test name
Test status
Simulation time 45496171 ps
CPU time 1.19 seconds
Started Aug 09 07:02:49 PM PDT 24
Finished Aug 09 07:02:50 PM PDT 24
Peak memory 197340 kb
Host smart-b7a9535b-c6bd-4282-83fc-bef7edd04de1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522372863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger.
522372863
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.2989727046
Short name T154
Test name
Test status
Simulation time 84854996 ps
CPU time 0.75 seconds
Started Aug 09 07:02:48 PM PDT 24
Finished Aug 09 07:02:49 PM PDT 24
Peak memory 195896 kb
Host smart-456703c4-90a9-4c34-87d8-43ea669830b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989727046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.2989727046
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.4074689635
Short name T608
Test name
Test status
Simulation time 20592817 ps
CPU time 0.66 seconds
Started Aug 09 07:02:47 PM PDT 24
Finished Aug 09 07:02:47 PM PDT 24
Peak memory 194884 kb
Host smart-5ac64a76-1b8e-4482-b356-27891afe396d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074689635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.4074689635
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.3532824351
Short name T119
Test name
Test status
Simulation time 44836327 ps
CPU time 2.01 seconds
Started Aug 09 07:02:46 PM PDT 24
Finished Aug 09 07:02:48 PM PDT 24
Peak memory 198556 kb
Host smart-1cb8bfe3-fa8c-4456-ab3f-2824b1a95044
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532824351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.3532824351
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.3536553963
Short name T178
Test name
Test status
Simulation time 44875909 ps
CPU time 1.29 seconds
Started Aug 09 07:02:47 PM PDT 24
Finished Aug 09 07:02:49 PM PDT 24
Peak memory 196076 kb
Host smart-9a475bb0-2cbb-41bc-88c0-1d3091cb2ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536553963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.3536553963
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.4061971253
Short name T554
Test name
Test status
Simulation time 28900237 ps
CPU time 0.92 seconds
Started Aug 09 07:02:47 PM PDT 24
Finished Aug 09 07:02:48 PM PDT 24
Peak memory 196328 kb
Host smart-5c42f729-36d0-48a6-b991-c54a9daa9ffd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061971253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.4061971253
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.480673033
Short name T523
Test name
Test status
Simulation time 5240783589 ps
CPU time 125.31 seconds
Started Aug 09 07:02:48 PM PDT 24
Finished Aug 09 07:04:54 PM PDT 24
Peak memory 198732 kb
Host smart-0bd0a8f5-1019-48cd-b790-b7dbaed1ef2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480673033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.480673033
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.1592863271
Short name T636
Test name
Test status
Simulation time 11572714 ps
CPU time 0.62 seconds
Started Aug 09 07:02:56 PM PDT 24
Finished Aug 09 07:02:57 PM PDT 24
Peak memory 195376 kb
Host smart-20e7d789-d6aa-4e1f-9122-7a20848c314c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592863271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.1592863271
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1143075275
Short name T170
Test name
Test status
Simulation time 30433527 ps
CPU time 0.76 seconds
Started Aug 09 07:02:51 PM PDT 24
Finished Aug 09 07:02:51 PM PDT 24
Peak memory 196528 kb
Host smart-c08450dc-d4e3-40fa-95d9-852bdd3f5574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143075275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1143075275
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.1083401175
Short name T556
Test name
Test status
Simulation time 1346472989 ps
CPU time 29.66 seconds
Started Aug 09 07:02:56 PM PDT 24
Finished Aug 09 07:03:26 PM PDT 24
Peak memory 197428 kb
Host smart-6032f41f-4d50-49cd-aa3a-83f72d8e100a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083401175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.1083401175
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.2446437592
Short name T594
Test name
Test status
Simulation time 85920942 ps
CPU time 0.99 seconds
Started Aug 09 07:02:56 PM PDT 24
Finished Aug 09 07:02:57 PM PDT 24
Peak memory 196968 kb
Host smart-ab501703-efd6-4027-b648-71e5f7f6b473
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446437592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.2446437592
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3112915598
Short name T157
Test name
Test status
Simulation time 60720334 ps
CPU time 0.71 seconds
Started Aug 09 07:02:48 PM PDT 24
Finished Aug 09 07:02:49 PM PDT 24
Peak memory 195892 kb
Host smart-d672f9c1-efd7-49a5-8b7a-f721a7af3e4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112915598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3112915598
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.3563937737
Short name T196
Test name
Test status
Simulation time 125822128 ps
CPU time 1.34 seconds
Started Aug 09 07:02:49 PM PDT 24
Finished Aug 09 07:02:50 PM PDT 24
Peak memory 197456 kb
Host smart-71613003-d223-441f-8260-639005909d7c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563937737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.3563937737
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.4192456242
Short name T281
Test name
Test status
Simulation time 839945768 ps
CPU time 1.6 seconds
Started Aug 09 07:02:48 PM PDT 24
Finished Aug 09 07:02:50 PM PDT 24
Peak memory 196684 kb
Host smart-0afe95ff-23e8-4f51-9d4f-3508d9eff50d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192456242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.4192456242
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3302128721
Short name T321
Test name
Test status
Simulation time 193123823 ps
CPU time 1.2 seconds
Started Aug 09 07:02:47 PM PDT 24
Finished Aug 09 07:02:48 PM PDT 24
Peak memory 197092 kb
Host smart-a44c35cc-7db2-4515-9b54-706c4524e17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302128721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3302128721
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.1777396447
Short name T274
Test name
Test status
Simulation time 57701266 ps
CPU time 0.77 seconds
Started Aug 09 07:02:48 PM PDT 24
Finished Aug 09 07:02:49 PM PDT 24
Peak memory 196024 kb
Host smart-87231d84-4e63-4517-8de5-eb910a3d0c65
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777396447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.1777396447
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3993723575
Short name T418
Test name
Test status
Simulation time 858281909 ps
CPU time 2.18 seconds
Started Aug 09 07:03:01 PM PDT 24
Finished Aug 09 07:03:04 PM PDT 24
Peak memory 198588 kb
Host smart-7dc02add-060f-4e48-89e6-70ccc7065092
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993723575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3993723575
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3325254441
Short name T167
Test name
Test status
Simulation time 128212690 ps
CPU time 1.14 seconds
Started Aug 09 07:02:47 PM PDT 24
Finished Aug 09 07:02:48 PM PDT 24
Peak memory 196848 kb
Host smart-2d5fdea2-1f08-410b-93b3-9059a5b36a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325254441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3325254441
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1723922668
Short name T650
Test name
Test status
Simulation time 37535063 ps
CPU time 1.12 seconds
Started Aug 09 07:02:47 PM PDT 24
Finished Aug 09 07:02:48 PM PDT 24
Peak memory 196184 kb
Host smart-ddd2005a-d3cf-4161-820b-3900af1f1b47
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723922668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1723922668
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.3399959861
Short name T54
Test name
Test status
Simulation time 4052612567 ps
CPU time 57.66 seconds
Started Aug 09 07:02:56 PM PDT 24
Finished Aug 09 07:03:54 PM PDT 24
Peak memory 198692 kb
Host smart-29be0a6e-0f6b-49d3-89eb-549cd4c1df9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399959861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.3399959861
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.282374594
Short name T375
Test name
Test status
Simulation time 85623561830 ps
CPU time 463.31 seconds
Started Aug 09 07:02:56 PM PDT 24
Finished Aug 09 07:10:40 PM PDT 24
Peak memory 198824 kb
Host smart-ac3053c1-fd37-4894-9352-b2f2a3081695
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=282374594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.282374594
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.1585512966
Short name T216
Test name
Test status
Simulation time 10204127 ps
CPU time 0.55 seconds
Started Aug 09 07:02:57 PM PDT 24
Finished Aug 09 07:02:57 PM PDT 24
Peak memory 194484 kb
Host smart-f08ec44d-0af7-420f-896d-c2f0652de31d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585512966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.1585512966
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2585185091
Short name T527
Test name
Test status
Simulation time 106288637 ps
CPU time 0.88 seconds
Started Aug 09 07:02:56 PM PDT 24
Finished Aug 09 07:02:58 PM PDT 24
Peak memory 196884 kb
Host smart-4ea27695-9ced-4d89-84d4-b800975ec515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585185091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2585185091
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.1810907418
Short name T19
Test name
Test status
Simulation time 719777183 ps
CPU time 25.44 seconds
Started Aug 09 07:02:56 PM PDT 24
Finished Aug 09 07:03:22 PM PDT 24
Peak memory 198604 kb
Host smart-b252f765-255b-4d0a-bded-ebd6fb5f168b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810907418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.1810907418
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.1525257513
Short name T530
Test name
Test status
Simulation time 309506939 ps
CPU time 0.64 seconds
Started Aug 09 07:02:56 PM PDT 24
Finished Aug 09 07:02:57 PM PDT 24
Peak memory 194948 kb
Host smart-b985edd7-582b-4a7e-b939-81e3b3e75b23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525257513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.1525257513
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2428826553
Short name T351
Test name
Test status
Simulation time 53821205 ps
CPU time 0.91 seconds
Started Aug 09 07:02:56 PM PDT 24
Finished Aug 09 07:02:57 PM PDT 24
Peak memory 197224 kb
Host smart-4a82500e-58e3-4810-a3f4-dc210f9bce42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428826553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2428826553
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.1407923532
Short name T678
Test name
Test status
Simulation time 26724687 ps
CPU time 1.03 seconds
Started Aug 09 07:02:58 PM PDT 24
Finished Aug 09 07:02:59 PM PDT 24
Peak memory 196836 kb
Host smart-748d4625-37db-4728-a02b-9d120a6bf3f2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407923532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.1407923532
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.2955329399
Short name T372
Test name
Test status
Simulation time 90826657 ps
CPU time 2.25 seconds
Started Aug 09 07:02:58 PM PDT 24
Finished Aug 09 07:03:00 PM PDT 24
Peak memory 197780 kb
Host smart-24d0ac83-13d9-4384-8f8a-38231cfdbb9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955329399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.2955329399
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.4052948371
Short name T156
Test name
Test status
Simulation time 47957541 ps
CPU time 1.04 seconds
Started Aug 09 07:02:57 PM PDT 24
Finished Aug 09 07:02:58 PM PDT 24
Peak memory 196608 kb
Host smart-194a7d5a-029b-4178-8313-0000ea9c6905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052948371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.4052948371
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1820188713
Short name T597
Test name
Test status
Simulation time 34260246 ps
CPU time 1.12 seconds
Started Aug 09 07:02:55 PM PDT 24
Finished Aug 09 07:02:56 PM PDT 24
Peak memory 197704 kb
Host smart-b58b09e6-9b69-460d-918f-6a93d6cd726d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820188713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1820188713
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1376649040
Short name T702
Test name
Test status
Simulation time 249392086 ps
CPU time 4.42 seconds
Started Aug 09 07:02:57 PM PDT 24
Finished Aug 09 07:03:02 PM PDT 24
Peak memory 198576 kb
Host smart-8721087b-0592-469d-a8c4-66907dd7399a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376649040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1376649040
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.3475836141
Short name T598
Test name
Test status
Simulation time 141648461 ps
CPU time 1.36 seconds
Started Aug 09 07:02:57 PM PDT 24
Finished Aug 09 07:02:59 PM PDT 24
Peak memory 197316 kb
Host smart-2345bcd1-8b80-4795-8c8e-da3fa6a6a96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475836141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.3475836141
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.4153077725
Short name T593
Test name
Test status
Simulation time 193285332 ps
CPU time 1.39 seconds
Started Aug 09 07:02:58 PM PDT 24
Finished Aug 09 07:03:00 PM PDT 24
Peak memory 197784 kb
Host smart-f2f4aaf4-1fa1-410a-8cee-3787c5ef5fc4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153077725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.4153077725
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.2325615928
Short name T406
Test name
Test status
Simulation time 12221261396 ps
CPU time 75.26 seconds
Started Aug 09 07:02:58 PM PDT 24
Finished Aug 09 07:04:13 PM PDT 24
Peak memory 198728 kb
Host smart-3a3347d1-25dc-4155-bfd9-2334af583a63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325615928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.2325615928
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.3275494900
Short name T365
Test name
Test status
Simulation time 14971992333 ps
CPU time 265.13 seconds
Started Aug 09 07:02:57 PM PDT 24
Finished Aug 09 07:07:22 PM PDT 24
Peak memory 198940 kb
Host smart-b18bf23c-1706-43ec-a8dc-7e8da0d6fb0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3275494900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.3275494900
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3668444921
Short name T405
Test name
Test status
Simulation time 21989582 ps
CPU time 0.6 seconds
Started Aug 09 07:02:56 PM PDT 24
Finished Aug 09 07:02:57 PM PDT 24
Peak memory 195376 kb
Host smart-e96b51d3-9e74-48fb-a9fe-40f74b37ef56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668444921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3668444921
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.1172689984
Short name T14
Test name
Test status
Simulation time 23437875 ps
CPU time 0.84 seconds
Started Aug 09 07:02:56 PM PDT 24
Finished Aug 09 07:02:58 PM PDT 24
Peak memory 195912 kb
Host smart-b1c70c1d-9f70-445a-8804-a7fa7f67324e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172689984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.1172689984
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.805846434
Short name T379
Test name
Test status
Simulation time 308787222 ps
CPU time 8.79 seconds
Started Aug 09 07:02:57 PM PDT 24
Finished Aug 09 07:03:06 PM PDT 24
Peak memory 197248 kb
Host smart-636ae8e6-1fc0-4cc4-b416-8505e3323be6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805846434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stres
s.805846434
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.2554836710
Short name T427
Test name
Test status
Simulation time 988768197 ps
CPU time 1.18 seconds
Started Aug 09 07:02:57 PM PDT 24
Finished Aug 09 07:02:58 PM PDT 24
Peak memory 197268 kb
Host smart-64d2fadd-4b1b-41d3-a8ee-227014e78786
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554836710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2554836710
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1011172498
Short name T224
Test name
Test status
Simulation time 73754327 ps
CPU time 1.37 seconds
Started Aug 09 07:02:58 PM PDT 24
Finished Aug 09 07:02:59 PM PDT 24
Peak memory 197428 kb
Host smart-692fc4a8-b991-400e-9d8f-b7e6dc3f05ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011172498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1011172498
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.3835429649
Short name T695
Test name
Test status
Simulation time 69662990 ps
CPU time 2.87 seconds
Started Aug 09 07:02:57 PM PDT 24
Finished Aug 09 07:03:00 PM PDT 24
Peak memory 198352 kb
Host smart-e9c23a19-ca9d-4640-aab8-afb415bd8913
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835429649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.3835429649
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.449812298
Short name T409
Test name
Test status
Simulation time 229928020 ps
CPU time 2.52 seconds
Started Aug 09 07:02:58 PM PDT 24
Finished Aug 09 07:03:01 PM PDT 24
Peak memory 197048 kb
Host smart-ab745b43-7c0f-4ffb-b34e-9da320ef1635
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449812298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger.
449812298
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.634925876
Short name T432
Test name
Test status
Simulation time 125505847 ps
CPU time 1.37 seconds
Started Aug 09 07:02:56 PM PDT 24
Finished Aug 09 07:02:58 PM PDT 24
Peak memory 196380 kb
Host smart-ebda2e99-4e96-4737-8f83-4eeaadbd4c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634925876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.634925876
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3363668406
Short name T421
Test name
Test status
Simulation time 65180487 ps
CPU time 1.25 seconds
Started Aug 09 07:02:57 PM PDT 24
Finished Aug 09 07:02:59 PM PDT 24
Peak memory 197168 kb
Host smart-4208fc24-021b-454a-9575-81c0b07e526c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363668406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3363668406
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.83312467
Short name T124
Test name
Test status
Simulation time 385360955 ps
CPU time 6.23 seconds
Started Aug 09 07:02:57 PM PDT 24
Finished Aug 09 07:03:03 PM PDT 24
Peak memory 198580 kb
Host smart-f2d20c02-7e10-4242-aa63-60be437d0a84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83312467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand
om_long_reg_writes_reg_reads.83312467
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.754483819
Short name T485
Test name
Test status
Simulation time 42660868 ps
CPU time 0.9 seconds
Started Aug 09 07:02:57 PM PDT 24
Finished Aug 09 07:02:58 PM PDT 24
Peak memory 195948 kb
Host smart-87c2313e-18f4-436e-8283-5d710b6a694d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754483819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.754483819
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.4162978960
Short name T232
Test name
Test status
Simulation time 67725727 ps
CPU time 1.24 seconds
Started Aug 09 07:02:56 PM PDT 24
Finished Aug 09 07:02:57 PM PDT 24
Peak memory 196832 kb
Host smart-705ea527-a1e0-4f80-b992-d87f9e0dc197
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162978960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.4162978960
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.1180702317
Short name T540
Test name
Test status
Simulation time 30355475432 ps
CPU time 124.6 seconds
Started Aug 09 07:02:57 PM PDT 24
Finished Aug 09 07:05:02 PM PDT 24
Peak memory 198712 kb
Host smart-68e71075-8ac0-4274-a443-057bdf0736e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180702317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.1180702317
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.1031307595
Short name T691
Test name
Test status
Simulation time 41460358925 ps
CPU time 888.7 seconds
Started Aug 09 07:02:57 PM PDT 24
Finished Aug 09 07:17:46 PM PDT 24
Peak memory 198828 kb
Host smart-79e3b1f5-5605-41d0-ad1a-ca5cbc2f8773
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1031307595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.1031307595
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.920534007
Short name T275
Test name
Test status
Simulation time 89709686 ps
CPU time 0.57 seconds
Started Aug 09 07:02:14 PM PDT 24
Finished Aug 09 07:02:15 PM PDT 24
Peak memory 194424 kb
Host smart-45b5128c-d3b3-4650-86eb-77bd5863a8a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920534007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.920534007
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.3653093794
Short name T259
Test name
Test status
Simulation time 167892243 ps
CPU time 0.84 seconds
Started Aug 09 07:02:16 PM PDT 24
Finished Aug 09 07:02:17 PM PDT 24
Peak memory 195872 kb
Host smart-c4d958be-1f29-45e5-bedf-eba8ca741ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653093794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.3653093794
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.2812971577
Short name T547
Test name
Test status
Simulation time 320005341 ps
CPU time 3.83 seconds
Started Aug 09 07:02:18 PM PDT 24
Finished Aug 09 07:02:22 PM PDT 24
Peak memory 196188 kb
Host smart-cb5b1d15-c049-4c18-9174-90828e3fd8ec
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812971577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.2812971577
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.1291829515
Short name T139
Test name
Test status
Simulation time 27705320 ps
CPU time 0.73 seconds
Started Aug 09 07:02:17 PM PDT 24
Finished Aug 09 07:02:18 PM PDT 24
Peak memory 196440 kb
Host smart-71b4bf26-c886-4e63-86d5-ccfa885261e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291829515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1291829515
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.1102144409
Short name T376
Test name
Test status
Simulation time 75756815 ps
CPU time 1.11 seconds
Started Aug 09 07:02:17 PM PDT 24
Finished Aug 09 07:02:18 PM PDT 24
Peak memory 196412 kb
Host smart-4fb96f04-f843-4c5f-be44-4116507c1f7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102144409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1102144409
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2876302358
Short name T400
Test name
Test status
Simulation time 29873095 ps
CPU time 1.28 seconds
Started Aug 09 07:02:16 PM PDT 24
Finished Aug 09 07:02:17 PM PDT 24
Peak memory 197056 kb
Host smart-08307054-4857-42c7-b61e-341a1703514b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876302358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2876302358
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.429459261
Short name T353
Test name
Test status
Simulation time 301929387 ps
CPU time 2.38 seconds
Started Aug 09 07:02:15 PM PDT 24
Finished Aug 09 07:02:17 PM PDT 24
Peak memory 197680 kb
Host smart-541f7cb0-b7c5-418b-b3d1-661686251a39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429459261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.429459261
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.957479850
Short name T180
Test name
Test status
Simulation time 70672995 ps
CPU time 0.74 seconds
Started Aug 09 07:02:16 PM PDT 24
Finished Aug 09 07:02:17 PM PDT 24
Peak memory 196628 kb
Host smart-aa89f519-fe50-4876-a5a5-95436f341494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957479850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.957479850
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1316384830
Short name T15
Test name
Test status
Simulation time 177598128 ps
CPU time 1.31 seconds
Started Aug 09 07:02:16 PM PDT 24
Finished Aug 09 07:02:17 PM PDT 24
Peak memory 197156 kb
Host smart-0e7010c8-3d86-4999-b254-0343392e533b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316384830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1316384830
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3067948393
Short name T503
Test name
Test status
Simulation time 327375067 ps
CPU time 5.4 seconds
Started Aug 09 07:02:14 PM PDT 24
Finished Aug 09 07:02:19 PM PDT 24
Peak memory 198564 kb
Host smart-73a3b525-b3ff-4359-aa3b-fa57a3ed07b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067948393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3067948393
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.502442495
Short name T36
Test name
Test status
Simulation time 883305428 ps
CPU time 1.43 seconds
Started Aug 09 07:02:13 PM PDT 24
Finished Aug 09 07:02:15 PM PDT 24
Peak memory 215584 kb
Host smart-7fdf770d-7bd6-474a-878a-9f9c2fd70c0b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502442495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.502442495
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.1708336748
Short name T592
Test name
Test status
Simulation time 34842536 ps
CPU time 0.83 seconds
Started Aug 09 07:02:15 PM PDT 24
Finished Aug 09 07:02:16 PM PDT 24
Peak memory 195648 kb
Host smart-52630250-037e-4806-8711-4b396c740a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708336748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.1708336748
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.1227509135
Short name T128
Test name
Test status
Simulation time 189079852 ps
CPU time 1.02 seconds
Started Aug 09 07:02:14 PM PDT 24
Finished Aug 09 07:02:15 PM PDT 24
Peak memory 196272 kb
Host smart-34fb91a8-3e70-4b97-887e-16b4bdda8a79
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227509135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.1227509135
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1645859494
Short name T137
Test name
Test status
Simulation time 5489399573 ps
CPU time 147.12 seconds
Started Aug 09 07:02:15 PM PDT 24
Finished Aug 09 07:04:43 PM PDT 24
Peak memory 198676 kb
Host smart-7e6d0c2c-92af-4d58-af63-0e2ec72288cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645859494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1645859494
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.179788828
Short name T38
Test name
Test status
Simulation time 13975087 ps
CPU time 0.6 seconds
Started Aug 09 07:03:10 PM PDT 24
Finished Aug 09 07:03:11 PM PDT 24
Peak memory 194676 kb
Host smart-d0d5d060-2ff5-4360-8c4a-95e84cf2be13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179788828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.179788828
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.2823636607
Short name T79
Test name
Test status
Simulation time 46162631 ps
CPU time 0.87 seconds
Started Aug 09 07:02:56 PM PDT 24
Finished Aug 09 07:02:57 PM PDT 24
Peak memory 197000 kb
Host smart-88a2513c-4af2-4788-8019-fb2766504dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823636607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.2823636607
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.4189128097
Short name T310
Test name
Test status
Simulation time 1664015643 ps
CPU time 21.99 seconds
Started Aug 09 07:03:13 PM PDT 24
Finished Aug 09 07:03:35 PM PDT 24
Peak memory 198592 kb
Host smart-95922da1-229d-4798-8865-6a69b34fdfac
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189128097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.4189128097
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2299901043
Short name T221
Test name
Test status
Simulation time 76742904 ps
CPU time 1.09 seconds
Started Aug 09 07:03:13 PM PDT 24
Finished Aug 09 07:03:15 PM PDT 24
Peak memory 197212 kb
Host smart-daa05f6d-9fe8-411d-8471-11027c161a75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299901043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2299901043
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1772359435
Short name T169
Test name
Test status
Simulation time 115383978 ps
CPU time 0.76 seconds
Started Aug 09 07:02:56 PM PDT 24
Finished Aug 09 07:02:57 PM PDT 24
Peak memory 196736 kb
Host smart-d41df773-2433-4520-a71d-71c263d07410
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772359435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1772359435
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.37547416
Short name T214
Test name
Test status
Simulation time 148870741 ps
CPU time 1.45 seconds
Started Aug 09 07:03:02 PM PDT 24
Finished Aug 09 07:03:03 PM PDT 24
Peak memory 196720 kb
Host smart-c722a792-265a-4ce7-a3b0-57ee1d295576
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37547416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger.37547416
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.2103109995
Short name T265
Test name
Test status
Simulation time 228793834 ps
CPU time 1.33 seconds
Started Aug 09 07:02:56 PM PDT 24
Finished Aug 09 07:02:58 PM PDT 24
Peak memory 198612 kb
Host smart-667558b4-a8cf-49d7-a558-a8f29211ae47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103109995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.2103109995
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.433178861
Short name T504
Test name
Test status
Simulation time 22655267 ps
CPU time 0.93 seconds
Started Aug 09 07:02:58 PM PDT 24
Finished Aug 09 07:02:59 PM PDT 24
Peak memory 196548 kb
Host smart-a6f865bb-a29c-4eaf-8223-2b8adf2ed81a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433178861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullup
_pulldown.433178861
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2405177632
Short name T435
Test name
Test status
Simulation time 472395177 ps
CPU time 5.9 seconds
Started Aug 09 07:03:12 PM PDT 24
Finished Aug 09 07:03:18 PM PDT 24
Peak memory 198576 kb
Host smart-f23a7b99-3a6f-4de3-af37-5f17d61110a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405177632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.2405177632
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.1243806243
Short name T606
Test name
Test status
Simulation time 123577116 ps
CPU time 0.77 seconds
Started Aug 09 07:02:54 PM PDT 24
Finished Aug 09 07:02:55 PM PDT 24
Peak memory 195700 kb
Host smart-b48c1d59-f50d-4b05-9238-b7c1d936efca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243806243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.1243806243
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3090334507
Short name T271
Test name
Test status
Simulation time 23798756 ps
CPU time 0.87 seconds
Started Aug 09 07:02:58 PM PDT 24
Finished Aug 09 07:02:59 PM PDT 24
Peak memory 195904 kb
Host smart-58b2a9d4-679e-4e1c-aa89-8e9c8adb1389
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090334507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3090334507
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1228336695
Short name T370
Test name
Test status
Simulation time 8002333428 ps
CPU time 109.18 seconds
Started Aug 09 07:03:11 PM PDT 24
Finished Aug 09 07:05:00 PM PDT 24
Peak memory 198644 kb
Host smart-c66cdec2-c2ae-460e-9be8-6d284bfffb35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228336695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1228336695
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1754135811
Short name T687
Test name
Test status
Simulation time 24352156 ps
CPU time 0.57 seconds
Started Aug 09 07:03:11 PM PDT 24
Finished Aug 09 07:03:11 PM PDT 24
Peak memory 194652 kb
Host smart-365d5d4b-9c06-4f57-8314-ab303433d71a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754135811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1754135811
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2438864508
Short name T114
Test name
Test status
Simulation time 18870286 ps
CPU time 0.72 seconds
Started Aug 09 07:03:09 PM PDT 24
Finished Aug 09 07:03:10 PM PDT 24
Peak memory 195588 kb
Host smart-cc98b51d-87b5-4613-8d1d-cfea8b75133c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438864508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.2438864508
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.2610955594
Short name T190
Test name
Test status
Simulation time 278475212 ps
CPU time 4.98 seconds
Started Aug 09 07:03:10 PM PDT 24
Finished Aug 09 07:03:16 PM PDT 24
Peak memory 196028 kb
Host smart-b939475c-1815-48d9-b76c-70319f737b15
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610955594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.2610955594
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.33825729
Short name T578
Test name
Test status
Simulation time 369794028 ps
CPU time 1.06 seconds
Started Aug 09 07:03:12 PM PDT 24
Finished Aug 09 07:03:13 PM PDT 24
Peak memory 196916 kb
Host smart-43ed7336-97c7-4390-94cc-b8df749ee814
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33825729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.33825729
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.29308042
Short name T285
Test name
Test status
Simulation time 80101384 ps
CPU time 1.04 seconds
Started Aug 09 07:03:12 PM PDT 24
Finished Aug 09 07:03:13 PM PDT 24
Peak memory 196548 kb
Host smart-c9971d91-bb34-4779-8018-c2ea4e79bdd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29308042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.29308042
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.4095683586
Short name T223
Test name
Test status
Simulation time 129999062 ps
CPU time 2.98 seconds
Started Aug 09 07:03:10 PM PDT 24
Finished Aug 09 07:03:13 PM PDT 24
Peak memory 198680 kb
Host smart-66c71dd3-f935-4d00-adf2-99ad4229cc95
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095683586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.4095683586
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.543002744
Short name T138
Test name
Test status
Simulation time 258171290 ps
CPU time 3.75 seconds
Started Aug 09 07:03:10 PM PDT 24
Finished Aug 09 07:03:14 PM PDT 24
Peak memory 197096 kb
Host smart-4bf89fd3-3474-4b07-a095-4a29291d594a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543002744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger.
543002744
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.3125798901
Short name T301
Test name
Test status
Simulation time 100961901 ps
CPU time 1.11 seconds
Started Aug 09 07:03:09 PM PDT 24
Finished Aug 09 07:03:10 PM PDT 24
Peak memory 196480 kb
Host smart-1188aa97-aae5-4cdb-8cc7-7eb9b8c598a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125798901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.3125798901
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3878908368
Short name T317
Test name
Test status
Simulation time 25855483 ps
CPU time 0.94 seconds
Started Aug 09 07:03:15 PM PDT 24
Finished Aug 09 07:03:16 PM PDT 24
Peak memory 196548 kb
Host smart-8af4157d-5901-4fcb-a04e-54b5ed4271f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878908368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3878908368
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.1516569619
Short name T670
Test name
Test status
Simulation time 41530921 ps
CPU time 1.82 seconds
Started Aug 09 07:03:11 PM PDT 24
Finished Aug 09 07:03:13 PM PDT 24
Peak memory 198588 kb
Host smart-102ca09a-7e40-4bae-be22-9bd4ef3eef8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516569619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.1516569619
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.2441554954
Short name T175
Test name
Test status
Simulation time 83933273 ps
CPU time 0.96 seconds
Started Aug 09 07:03:10 PM PDT 24
Finished Aug 09 07:03:11 PM PDT 24
Peak memory 197080 kb
Host smart-1fc75eea-eb61-43da-8f1e-011daf07a9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441554954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2441554954
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.1520812607
Short name T143
Test name
Test status
Simulation time 79138932 ps
CPU time 1 seconds
Started Aug 09 07:03:13 PM PDT 24
Finished Aug 09 07:03:14 PM PDT 24
Peak memory 197072 kb
Host smart-5d113df3-35be-48e2-bb8a-4652f1eecdf8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520812607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.1520812607
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.3279238033
Short name T419
Test name
Test status
Simulation time 36729196180 ps
CPU time 56.42 seconds
Started Aug 09 07:03:13 PM PDT 24
Finished Aug 09 07:04:10 PM PDT 24
Peak memory 198724 kb
Host smart-64889e97-d957-41e5-9e14-5b2f5b6a7c71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279238033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.3279238033
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.2388898728
Short name T474
Test name
Test status
Simulation time 81006036673 ps
CPU time 812.67 seconds
Started Aug 09 07:03:11 PM PDT 24
Finished Aug 09 07:16:43 PM PDT 24
Peak memory 198828 kb
Host smart-2deb62db-f250-47ec-989e-692066deb886
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2388898728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.2388898728
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.961034673
Short name T220
Test name
Test status
Simulation time 11394544 ps
CPU time 0.55 seconds
Started Aug 09 07:03:08 PM PDT 24
Finished Aug 09 07:03:09 PM PDT 24
Peak memory 195112 kb
Host smart-8e17e7eb-0f07-4817-ab73-3384cab1247c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961034673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.961034673
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.3207768064
Short name T557
Test name
Test status
Simulation time 40084542 ps
CPU time 0.78 seconds
Started Aug 09 07:03:13 PM PDT 24
Finished Aug 09 07:03:14 PM PDT 24
Peak memory 195896 kb
Host smart-e4aa1454-28e9-42c1-a042-4eb42d1a8ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207768064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.3207768064
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3207973480
Short name T471
Test name
Test status
Simulation time 188390545 ps
CPU time 3.55 seconds
Started Aug 09 07:03:09 PM PDT 24
Finished Aug 09 07:03:13 PM PDT 24
Peak memory 197016 kb
Host smart-695ec0c5-eda0-4fc2-bb65-dea11a19e33f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207973480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3207973480
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.1302552533
Short name T309
Test name
Test status
Simulation time 69372841 ps
CPU time 1.06 seconds
Started Aug 09 07:03:10 PM PDT 24
Finished Aug 09 07:03:11 PM PDT 24
Peak memory 198176 kb
Host smart-59f924c1-1e0e-4a29-ba39-6ceebfb011c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302552533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.1302552533
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1751595260
Short name T12
Test name
Test status
Simulation time 364973303 ps
CPU time 1.11 seconds
Started Aug 09 07:03:09 PM PDT 24
Finished Aug 09 07:03:10 PM PDT 24
Peak memory 197292 kb
Host smart-a4e276e3-7c34-4b0a-967b-a4b9ce2228bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751595260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1751595260
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2450528286
Short name T721
Test name
Test status
Simulation time 50067467 ps
CPU time 1.22 seconds
Started Aug 09 07:03:07 PM PDT 24
Finished Aug 09 07:03:08 PM PDT 24
Peak memory 198512 kb
Host smart-387d6ef5-cb6b-41b0-9826-7adc32efb8f7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450528286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.2450528286
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.3429302839
Short name T424
Test name
Test status
Simulation time 157845768 ps
CPU time 1.47 seconds
Started Aug 09 07:03:10 PM PDT 24
Finished Aug 09 07:03:11 PM PDT 24
Peak memory 196668 kb
Host smart-8ac5ccbf-2a30-42c7-a2d3-4a004816b8a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429302839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.3429302839
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.1856450612
Short name T209
Test name
Test status
Simulation time 35548520 ps
CPU time 0.94 seconds
Started Aug 09 07:03:09 PM PDT 24
Finished Aug 09 07:03:10 PM PDT 24
Peak memory 196508 kb
Host smart-0d4432c5-e034-45c1-9e1d-dc0daff4c950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856450612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.1856450612
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2053788913
Short name T50
Test name
Test status
Simulation time 93578959 ps
CPU time 1.03 seconds
Started Aug 09 07:03:14 PM PDT 24
Finished Aug 09 07:03:15 PM PDT 24
Peak memory 196628 kb
Host smart-0fb51992-cfd0-44c9-b9ee-14af32ec51a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053788913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.2053788913
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.1064168634
Short name T273
Test name
Test status
Simulation time 1581995113 ps
CPU time 3.19 seconds
Started Aug 09 07:03:09 PM PDT 24
Finished Aug 09 07:03:12 PM PDT 24
Peak memory 198508 kb
Host smart-75ec48ed-f547-4609-8d3f-9853ea1064fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064168634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.1064168634
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.3603364853
Short name T141
Test name
Test status
Simulation time 157522389 ps
CPU time 1.07 seconds
Started Aug 09 07:03:12 PM PDT 24
Finished Aug 09 07:03:13 PM PDT 24
Peak memory 196336 kb
Host smart-c8e1fcee-6a07-44e1-a4de-31d0bc63cc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603364853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.3603364853
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3243776378
Short name T412
Test name
Test status
Simulation time 313481801 ps
CPU time 1.5 seconds
Started Aug 09 07:03:11 PM PDT 24
Finished Aug 09 07:03:13 PM PDT 24
Peak memory 197360 kb
Host smart-614c037b-6f01-4830-9068-1fb6cd33ded1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243776378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3243776378
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.4172752313
Short name T142
Test name
Test status
Simulation time 11977358087 ps
CPU time 93.23 seconds
Started Aug 09 07:03:09 PM PDT 24
Finished Aug 09 07:04:43 PM PDT 24
Peak memory 198784 kb
Host smart-79713ea8-ecbb-440f-8662-1af301d1440e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172752313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.4172752313
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1338295547
Short name T249
Test name
Test status
Simulation time 99222745 ps
CPU time 0.56 seconds
Started Aug 09 07:03:13 PM PDT 24
Finished Aug 09 07:03:14 PM PDT 24
Peak memory 194480 kb
Host smart-dd9f2141-3057-40aa-a877-5aadfc1c3fb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338295547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1338295547
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.1723270241
Short name T683
Test name
Test status
Simulation time 56478498 ps
CPU time 0.81 seconds
Started Aug 09 07:03:14 PM PDT 24
Finished Aug 09 07:03:15 PM PDT 24
Peak memory 195904 kb
Host smart-46a33f57-b698-4f18-987d-5604896f83c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723270241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.1723270241
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.3398741514
Short name T393
Test name
Test status
Simulation time 2606023058 ps
CPU time 18.66 seconds
Started Aug 09 07:03:14 PM PDT 24
Finished Aug 09 07:03:33 PM PDT 24
Peak memory 197688 kb
Host smart-40dc892e-d9b6-42df-b846-cc1261c64c04
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398741514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.3398741514
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.2130658177
Short name T680
Test name
Test status
Simulation time 44942328 ps
CPU time 0.79 seconds
Started Aug 09 07:03:17 PM PDT 24
Finished Aug 09 07:03:18 PM PDT 24
Peak memory 196360 kb
Host smart-ce6dc6e3-dd55-47ce-8525-13916fd4ccae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130658177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.2130658177
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.360374882
Short name T217
Test name
Test status
Simulation time 94723026 ps
CPU time 0.73 seconds
Started Aug 09 07:03:13 PM PDT 24
Finished Aug 09 07:03:14 PM PDT 24
Peak memory 194976 kb
Host smart-669c5fb4-53e6-440d-925f-d27ea207005c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360374882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.360374882
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.995072790
Short name T311
Test name
Test status
Simulation time 193177650 ps
CPU time 2.19 seconds
Started Aug 09 07:03:14 PM PDT 24
Finished Aug 09 07:03:16 PM PDT 24
Peak memory 198808 kb
Host smart-757fa0e8-b8ae-4555-8319-284db4aebb7b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995072790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.gpio_intr_with_filter_rand_intr_event.995072790
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.4139163783
Short name T164
Test name
Test status
Simulation time 69935584 ps
CPU time 1.75 seconds
Started Aug 09 07:03:18 PM PDT 24
Finished Aug 09 07:03:20 PM PDT 24
Peak memory 196388 kb
Host smart-54fb102b-6c6f-4f34-a1ee-0ad2f1b0f551
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139163783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.4139163783
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.2753749759
Short name T326
Test name
Test status
Simulation time 107877755 ps
CPU time 1.21 seconds
Started Aug 09 07:03:14 PM PDT 24
Finished Aug 09 07:03:15 PM PDT 24
Peak memory 196664 kb
Host smart-80194616-d183-4246-875a-615c48e74d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753749759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.2753749759
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.3058226301
Short name T443
Test name
Test status
Simulation time 38336403 ps
CPU time 1.31 seconds
Started Aug 09 07:03:13 PM PDT 24
Finished Aug 09 07:03:15 PM PDT 24
Peak memory 197620 kb
Host smart-35e8e46a-afd8-419a-9ab5-4a3cf45940bd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058226301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.3058226301
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1434882103
Short name T483
Test name
Test status
Simulation time 66206179 ps
CPU time 1.22 seconds
Started Aug 09 07:03:18 PM PDT 24
Finished Aug 09 07:03:20 PM PDT 24
Peak memory 196708 kb
Host smart-e4d92286-60b7-44f1-98f4-d18f1685738f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434882103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.1434882103
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2359480450
Short name T647
Test name
Test status
Simulation time 39579765 ps
CPU time 1.19 seconds
Started Aug 09 07:03:08 PM PDT 24
Finished Aug 09 07:03:10 PM PDT 24
Peak memory 197260 kb
Host smart-22e773cd-3bbb-49fd-b87f-5d0f65b7f801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359480450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2359480450
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.333509790
Short name T539
Test name
Test status
Simulation time 141507857 ps
CPU time 0.87 seconds
Started Aug 09 07:03:09 PM PDT 24
Finished Aug 09 07:03:10 PM PDT 24
Peak memory 195920 kb
Host smart-431a850a-acb4-43b4-bd02-c6e7041e9de2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333509790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.333509790
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.1484536476
Short name T489
Test name
Test status
Simulation time 19129370282 ps
CPU time 220.23 seconds
Started Aug 09 07:03:12 PM PDT 24
Finished Aug 09 07:06:53 PM PDT 24
Peak memory 198780 kb
Host smart-6ece4647-1786-4ebd-b780-21d1b64ea1e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484536476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.1484536476
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.2407274222
Short name T286
Test name
Test status
Simulation time 11112602316 ps
CPU time 204.27 seconds
Started Aug 09 07:03:14 PM PDT 24
Finished Aug 09 07:06:38 PM PDT 24
Peak memory 198892 kb
Host smart-8bdadf8a-ef03-40d5-97e9-9c2eab17e4b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2407274222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.2407274222
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.4084157985
Short name T194
Test name
Test status
Simulation time 24867282 ps
CPU time 0.58 seconds
Started Aug 09 07:03:14 PM PDT 24
Finished Aug 09 07:03:15 PM PDT 24
Peak memory 195408 kb
Host smart-87f52dae-4141-47ee-866f-52e35a733133
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084157985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.4084157985
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1986487881
Short name T619
Test name
Test status
Simulation time 138868310 ps
CPU time 0.86 seconds
Started Aug 09 07:03:14 PM PDT 24
Finished Aug 09 07:03:15 PM PDT 24
Peak memory 197032 kb
Host smart-cae1a179-1fd0-48cc-924f-18722e93d8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986487881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1986487881
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.328359184
Short name T233
Test name
Test status
Simulation time 1050854024 ps
CPU time 30.99 seconds
Started Aug 09 07:03:14 PM PDT 24
Finished Aug 09 07:03:45 PM PDT 24
Peak memory 197384 kb
Host smart-5fe08057-aec2-4c5f-9a58-f85f85f14579
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328359184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stres
s.328359184
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.3101085957
Short name T645
Test name
Test status
Simulation time 48264916 ps
CPU time 0.83 seconds
Started Aug 09 07:03:19 PM PDT 24
Finished Aug 09 07:03:19 PM PDT 24
Peak memory 197028 kb
Host smart-cf6ea705-36d3-4751-9d5e-34bf540e53f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101085957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.3101085957
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.2592718905
Short name T123
Test name
Test status
Simulation time 64864025 ps
CPU time 1.02 seconds
Started Aug 09 07:03:18 PM PDT 24
Finished Aug 09 07:03:19 PM PDT 24
Peak memory 196296 kb
Host smart-bf167750-bfe4-4590-9445-a1c0383d10f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592718905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.2592718905
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3650493362
Short name T630
Test name
Test status
Simulation time 97557828 ps
CPU time 1.78 seconds
Started Aug 09 07:03:14 PM PDT 24
Finished Aug 09 07:03:16 PM PDT 24
Peak memory 197336 kb
Host smart-8e2c15e9-b347-4068-8635-3ce6335e8252
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650493362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3650493362
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.1888028491
Short name T350
Test name
Test status
Simulation time 102460887 ps
CPU time 3.04 seconds
Started Aug 09 07:03:14 PM PDT 24
Finished Aug 09 07:03:17 PM PDT 24
Peak memory 197724 kb
Host smart-f8fbeab3-2026-4317-9200-e7762b00f761
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888028491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.1888028491
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.1429057090
Short name T622
Test name
Test status
Simulation time 433942066 ps
CPU time 1.11 seconds
Started Aug 09 07:03:15 PM PDT 24
Finished Aug 09 07:03:16 PM PDT 24
Peak memory 196984 kb
Host smart-eac92ff2-61c8-4d63-b527-fed2c2bfc54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429057090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.1429057090
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.2581176850
Short name T507
Test name
Test status
Simulation time 76620557 ps
CPU time 0.93 seconds
Started Aug 09 07:03:17 PM PDT 24
Finished Aug 09 07:03:18 PM PDT 24
Peak memory 197088 kb
Host smart-401797c1-2b77-44ff-b9ed-31aeb59ba6e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581176850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.2581176850
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.192056096
Short name T253
Test name
Test status
Simulation time 227814348 ps
CPU time 3.8 seconds
Started Aug 09 07:03:13 PM PDT 24
Finished Aug 09 07:03:18 PM PDT 24
Peak memory 198504 kb
Host smart-a25da01f-4e1c-4744-b80e-f1559de2262e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192056096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ran
dom_long_reg_writes_reg_reads.192056096
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.618984882
Short name T671
Test name
Test status
Simulation time 48736741 ps
CPU time 1.02 seconds
Started Aug 09 07:03:20 PM PDT 24
Finished Aug 09 07:03:21 PM PDT 24
Peak memory 196192 kb
Host smart-dcf01e21-3149-435c-92de-ee277d8a69c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618984882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.618984882
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.1962437078
Short name T328
Test name
Test status
Simulation time 103058834 ps
CPU time 0.94 seconds
Started Aug 09 07:03:12 PM PDT 24
Finished Aug 09 07:03:13 PM PDT 24
Peak memory 196108 kb
Host smart-07f44004-2963-417a-8636-4678712fcabe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962437078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.1962437078
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3838601626
Short name T257
Test name
Test status
Simulation time 7604700535 ps
CPU time 54.76 seconds
Started Aug 09 07:03:14 PM PDT 24
Finished Aug 09 07:04:09 PM PDT 24
Peak memory 198712 kb
Host smart-d653464b-2096-4680-93dc-f7e918338a1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838601626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3838601626
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.2345628289
Short name T70
Test name
Test status
Simulation time 116772783847 ps
CPU time 2212.78 seconds
Started Aug 09 07:03:15 PM PDT 24
Finished Aug 09 07:40:08 PM PDT 24
Peak memory 198908 kb
Host smart-22a9651d-3afd-45b5-9c1e-4201f9dd3940
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2345628289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.2345628289
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1517300094
Short name T508
Test name
Test status
Simulation time 15970934 ps
CPU time 0.62 seconds
Started Aug 09 07:03:15 PM PDT 24
Finished Aug 09 07:03:16 PM PDT 24
Peak memory 195284 kb
Host smart-2822ac3a-57d6-4426-ad36-208a2111fecd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517300094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1517300094
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3553279406
Short name T632
Test name
Test status
Simulation time 30508486 ps
CPU time 0.87 seconds
Started Aug 09 07:03:13 PM PDT 24
Finished Aug 09 07:03:14 PM PDT 24
Peak memory 197108 kb
Host smart-18e08f3c-118a-4129-9d6f-8ee741e6f40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553279406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3553279406
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.1806620334
Short name T330
Test name
Test status
Simulation time 1441963480 ps
CPU time 15.62 seconds
Started Aug 09 07:03:17 PM PDT 24
Finished Aug 09 07:03:33 PM PDT 24
Peak memory 197460 kb
Host smart-48dc129c-e3dd-4528-8e4d-f9d3888d0203
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806620334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.1806620334
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.1507561543
Short name T384
Test name
Test status
Simulation time 205501912 ps
CPU time 0.91 seconds
Started Aug 09 07:03:14 PM PDT 24
Finished Aug 09 07:03:15 PM PDT 24
Peak memory 197656 kb
Host smart-b41678b8-71f0-4052-bb62-adfff6b3d94a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507561543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.1507561543
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2522962968
Short name T368
Test name
Test status
Simulation time 35787142 ps
CPU time 1.03 seconds
Started Aug 09 07:03:16 PM PDT 24
Finished Aug 09 07:03:17 PM PDT 24
Peak memory 197360 kb
Host smart-f6ba7e9e-7403-4a26-a473-ade182f977cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522962968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2522962968
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.3129085943
Short name T655
Test name
Test status
Simulation time 140438602 ps
CPU time 3.09 seconds
Started Aug 09 07:03:14 PM PDT 24
Finished Aug 09 07:03:18 PM PDT 24
Peak memory 198712 kb
Host smart-345cdbee-4207-4a2a-8fcc-7a1110add836
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129085943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.3129085943
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.4256410034
Short name T16
Test name
Test status
Simulation time 100004877 ps
CPU time 2.31 seconds
Started Aug 09 07:03:19 PM PDT 24
Finished Aug 09 07:03:21 PM PDT 24
Peak memory 197516 kb
Host smart-be809044-320c-49dc-9590-4d0430da5ba5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256410034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.4256410034
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.3067873105
Short name T466
Test name
Test status
Simulation time 202087145 ps
CPU time 1.28 seconds
Started Aug 09 07:03:14 PM PDT 24
Finished Aug 09 07:03:15 PM PDT 24
Peak memory 197628 kb
Host smart-6be6da2b-1c77-400b-b3ca-7bbe88d73427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067873105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.3067873105
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.4188434889
Short name T552
Test name
Test status
Simulation time 114421767 ps
CPU time 0.9 seconds
Started Aug 09 07:03:15 PM PDT 24
Finished Aug 09 07:03:16 PM PDT 24
Peak memory 196560 kb
Host smart-afefbc3e-4184-4637-a3fc-221dee593351
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188434889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.4188434889
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.3564411126
Short name T308
Test name
Test status
Simulation time 278412235 ps
CPU time 2.91 seconds
Started Aug 09 07:03:14 PM PDT 24
Finished Aug 09 07:03:17 PM PDT 24
Peak memory 198496 kb
Host smart-dc3933ba-b1a8-41f5-8500-890d8963db49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564411126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.3564411126
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.2844638882
Short name T344
Test name
Test status
Simulation time 99220366 ps
CPU time 1.42 seconds
Started Aug 09 07:03:19 PM PDT 24
Finished Aug 09 07:03:20 PM PDT 24
Peak memory 196796 kb
Host smart-288cdf55-ecda-497a-8c61-3164bbd25699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844638882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.2844638882
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.2324910621
Short name T416
Test name
Test status
Simulation time 69891125 ps
CPU time 0.87 seconds
Started Aug 09 07:03:16 PM PDT 24
Finished Aug 09 07:03:17 PM PDT 24
Peak memory 196244 kb
Host smart-d78d28cb-2ef4-4a39-a71c-588fcbfc3247
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324910621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.2324910621
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.3668761938
Short name T72
Test name
Test status
Simulation time 2675401831 ps
CPU time 36.69 seconds
Started Aug 09 07:03:14 PM PDT 24
Finished Aug 09 07:03:51 PM PDT 24
Peak memory 192412 kb
Host smart-e3606b08-5ca1-4386-b123-b73cad7befaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668761938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.3668761938
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.3470546128
Short name T712
Test name
Test status
Simulation time 13963060 ps
CPU time 0.57 seconds
Started Aug 09 07:03:19 PM PDT 24
Finished Aug 09 07:03:19 PM PDT 24
Peak memory 194388 kb
Host smart-a089a8f9-521a-4db2-bc6c-b1544fc218c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470546128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.3470546128
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.70998389
Short name T331
Test name
Test status
Simulation time 28008776 ps
CPU time 0.85 seconds
Started Aug 09 07:03:14 PM PDT 24
Finished Aug 09 07:03:15 PM PDT 24
Peak memory 197080 kb
Host smart-5f641b40-3d5b-444e-9aee-cf778de12977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70998389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.70998389
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1566616955
Short name T717
Test name
Test status
Simulation time 409188404 ps
CPU time 7.57 seconds
Started Aug 09 07:03:20 PM PDT 24
Finished Aug 09 07:03:28 PM PDT 24
Peak memory 198532 kb
Host smart-c6d61268-be9c-48d8-a431-54c31bcb6c86
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566616955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1566616955
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.3546166094
Short name T436
Test name
Test status
Simulation time 89891333 ps
CPU time 0.89 seconds
Started Aug 09 07:03:20 PM PDT 24
Finished Aug 09 07:03:21 PM PDT 24
Peak memory 196516 kb
Host smart-b905aeb8-2fda-4d76-82d1-f8e2e0417300
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546166094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.3546166094
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.1811668069
Short name T73
Test name
Test status
Simulation time 111038235 ps
CPU time 0.87 seconds
Started Aug 09 07:03:16 PM PDT 24
Finished Aug 09 07:03:17 PM PDT 24
Peak memory 197236 kb
Host smart-c7caf33a-b981-48c6-b2f9-e4786ec6fb19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811668069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.1811668069
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.1172611264
Short name T631
Test name
Test status
Simulation time 365992678 ps
CPU time 2.66 seconds
Started Aug 09 07:03:15 PM PDT 24
Finished Aug 09 07:03:18 PM PDT 24
Peak memory 198584 kb
Host smart-82301022-a778-464d-a925-ab6e5aeb657e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172611264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.1172611264
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.3589858666
Short name T411
Test name
Test status
Simulation time 117926392 ps
CPU time 1.46 seconds
Started Aug 09 07:03:19 PM PDT 24
Finished Aug 09 07:03:21 PM PDT 24
Peak memory 196672 kb
Host smart-8fc6708f-095e-4b03-bf50-6fd2216eb5bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589858666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.3589858666
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.479392465
Short name T191
Test name
Test status
Simulation time 151553283 ps
CPU time 0.82 seconds
Started Aug 09 07:03:15 PM PDT 24
Finished Aug 09 07:03:16 PM PDT 24
Peak memory 197108 kb
Host smart-9bdb4e55-0801-41ff-b75b-f1f8af91ce11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479392465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.479392465
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.1175369766
Short name T316
Test name
Test status
Simulation time 27458125 ps
CPU time 1.05 seconds
Started Aug 09 07:03:17 PM PDT 24
Finished Aug 09 07:03:18 PM PDT 24
Peak memory 196564 kb
Host smart-657b6907-9fc0-434e-88c4-b2b784a964fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175369766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.1175369766
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3853177710
Short name T148
Test name
Test status
Simulation time 82317530 ps
CPU time 1.22 seconds
Started Aug 09 07:03:14 PM PDT 24
Finished Aug 09 07:03:15 PM PDT 24
Peak memory 198724 kb
Host smart-616df1fc-e5ac-44bf-b0ff-5fead0c8a024
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853177710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3853177710
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.1685223003
Short name T568
Test name
Test status
Simulation time 184334899 ps
CPU time 1.17 seconds
Started Aug 09 07:03:16 PM PDT 24
Finished Aug 09 07:03:17 PM PDT 24
Peak memory 196972 kb
Host smart-86240f5a-5bce-4781-9d65-6412dda44caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685223003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.1685223003
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.181632320
Short name T177
Test name
Test status
Simulation time 270128828 ps
CPU time 1.32 seconds
Started Aug 09 07:03:18 PM PDT 24
Finished Aug 09 07:03:20 PM PDT 24
Peak memory 196280 kb
Host smart-3b8d3ca4-9a56-4db9-9dc5-c10ffbf6e79d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181632320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.181632320
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.1456863529
Short name T159
Test name
Test status
Simulation time 24832803403 ps
CPU time 155.34 seconds
Started Aug 09 07:03:17 PM PDT 24
Finished Aug 09 07:05:53 PM PDT 24
Peak memory 198648 kb
Host smart-425f09b5-701a-4f12-bea6-051352edfdc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456863529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.1456863529
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.2282995959
Short name T403
Test name
Test status
Simulation time 86781457970 ps
CPU time 1379.74 seconds
Started Aug 09 07:03:14 PM PDT 24
Finished Aug 09 07:26:14 PM PDT 24
Peak memory 198872 kb
Host smart-c4e96231-acb6-457e-9ef0-fb38d0991991
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2282995959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.2282995959
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.1540155902
Short name T601
Test name
Test status
Simulation time 13358637 ps
CPU time 0.58 seconds
Started Aug 09 07:03:21 PM PDT 24
Finished Aug 09 07:03:21 PM PDT 24
Peak memory 194492 kb
Host smart-c8c58516-a2f9-46b6-94e1-16d446da25da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540155902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.1540155902
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2488892983
Short name T509
Test name
Test status
Simulation time 83312687 ps
CPU time 0.76 seconds
Started Aug 09 07:03:16 PM PDT 24
Finished Aug 09 07:03:17 PM PDT 24
Peak memory 195840 kb
Host smart-cc5248aa-1efb-48e5-a47c-7fe1b1b13142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488892983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2488892983
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.3047861715
Short name T531
Test name
Test status
Simulation time 694075528 ps
CPU time 8.86 seconds
Started Aug 09 07:03:23 PM PDT 24
Finished Aug 09 07:03:32 PM PDT 24
Peak memory 197388 kb
Host smart-98fff8a7-aa9f-4d90-9944-aed0e80bcf34
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047861715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.3047861715
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.1819073522
Short name T701
Test name
Test status
Simulation time 216089084 ps
CPU time 0.96 seconds
Started Aug 09 07:03:20 PM PDT 24
Finished Aug 09 07:03:21 PM PDT 24
Peak memory 197188 kb
Host smart-1e380e30-7e22-4529-b9e2-9a6e27d87376
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819073522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.1819073522
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.2390684038
Short name T155
Test name
Test status
Simulation time 51949595 ps
CPU time 1.31 seconds
Started Aug 09 07:03:19 PM PDT 24
Finished Aug 09 07:03:20 PM PDT 24
Peak memory 197644 kb
Host smart-8fefd1b4-ce1d-4816-b4b6-98f1a74bb1bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390684038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.2390684038
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.956172233
Short name T628
Test name
Test status
Simulation time 68005693 ps
CPU time 2.57 seconds
Started Aug 09 07:03:25 PM PDT 24
Finished Aug 09 07:03:28 PM PDT 24
Peak memory 198624 kb
Host smart-ecf42838-a4e0-4345-bfc1-e7eeac8dd03a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956172233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.gpio_intr_with_filter_rand_intr_event.956172233
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.4226895059
Short name T55
Test name
Test status
Simulation time 573260171 ps
CPU time 2.21 seconds
Started Aug 09 07:03:20 PM PDT 24
Finished Aug 09 07:03:23 PM PDT 24
Peak memory 198628 kb
Host smart-47a9c95f-61e2-48a4-bbbb-2191a7708fd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226895059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.4226895059
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2595551019
Short name T53
Test name
Test status
Simulation time 70371395 ps
CPU time 1.34 seconds
Started Aug 09 07:03:18 PM PDT 24
Finished Aug 09 07:03:19 PM PDT 24
Peak memory 196412 kb
Host smart-acd48daa-779f-4395-bb4c-f210a42e3f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595551019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2595551019
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1296203039
Short name T674
Test name
Test status
Simulation time 51947800 ps
CPU time 1.01 seconds
Started Aug 09 07:03:15 PM PDT 24
Finished Aug 09 07:03:16 PM PDT 24
Peak memory 197236 kb
Host smart-c6ab256b-634f-4611-96a3-d3b181fad51d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296203039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.1296203039
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.4094004436
Short name T445
Test name
Test status
Simulation time 1630564967 ps
CPU time 5.39 seconds
Started Aug 09 07:03:22 PM PDT 24
Finished Aug 09 07:03:27 PM PDT 24
Peak memory 198460 kb
Host smart-69c0d5f7-5c07-40b3-9ef6-c40946f08cf6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094004436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.4094004436
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.311525784
Short name T49
Test name
Test status
Simulation time 53740443 ps
CPU time 1.08 seconds
Started Aug 09 07:03:18 PM PDT 24
Finished Aug 09 07:03:20 PM PDT 24
Peak memory 196304 kb
Host smart-27c98eb4-f7fa-4d9d-96f1-faf605e3a05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311525784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.311525784
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.3033508148
Short name T254
Test name
Test status
Simulation time 52391639 ps
CPU time 0.92 seconds
Started Aug 09 07:03:18 PM PDT 24
Finished Aug 09 07:03:19 PM PDT 24
Peak memory 196764 kb
Host smart-1a9ea7e3-7131-46a7-894c-a94d56445086
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033508148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.3033508148
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.300721449
Short name T213
Test name
Test status
Simulation time 27471845335 ps
CPU time 102.31 seconds
Started Aug 09 07:03:23 PM PDT 24
Finished Aug 09 07:05:06 PM PDT 24
Peak memory 198764 kb
Host smart-89811c78-9bbb-4f49-8193-5bbaa0ecfdba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300721449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.g
pio_stress_all.300721449
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.3055870764
Short name T494
Test name
Test status
Simulation time 21274928 ps
CPU time 0.61 seconds
Started Aug 09 07:03:24 PM PDT 24
Finished Aug 09 07:03:25 PM PDT 24
Peak memory 194444 kb
Host smart-c3c85f31-bb7e-4817-b867-c578d2f9500d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055870764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3055870764
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.3474906709
Short name T237
Test name
Test status
Simulation time 93948068 ps
CPU time 0.87 seconds
Started Aug 09 07:03:22 PM PDT 24
Finished Aug 09 07:03:23 PM PDT 24
Peak memory 196980 kb
Host smart-97f192db-f8fe-4921-84ab-e724da286761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474906709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.3474906709
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.2668667569
Short name T541
Test name
Test status
Simulation time 1328873612 ps
CPU time 17.59 seconds
Started Aug 09 07:03:27 PM PDT 24
Finished Aug 09 07:03:44 PM PDT 24
Peak memory 198496 kb
Host smart-cfb3a693-f4fa-4961-b9e5-1772b8b140bb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668667569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.2668667569
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.3822471090
Short name T524
Test name
Test status
Simulation time 29107460 ps
CPU time 0.72 seconds
Started Aug 09 07:03:22 PM PDT 24
Finished Aug 09 07:03:23 PM PDT 24
Peak memory 195124 kb
Host smart-39bfaee0-0b67-4b7c-8430-eae28103c003
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822471090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.3822471090
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.1644346144
Short name T314
Test name
Test status
Simulation time 151036011 ps
CPU time 1 seconds
Started Aug 09 07:03:21 PM PDT 24
Finished Aug 09 07:03:22 PM PDT 24
Peak memory 196396 kb
Host smart-472275ab-6f3b-4174-8322-674395c94e31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644346144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.1644346144
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.140119228
Short name T517
Test name
Test status
Simulation time 234993634 ps
CPU time 2.86 seconds
Started Aug 09 07:03:23 PM PDT 24
Finished Aug 09 07:03:26 PM PDT 24
Peak memory 198592 kb
Host smart-46d62899-450f-40ae-991e-8b6d247f53e2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140119228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.gpio_intr_with_filter_rand_intr_event.140119228
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.518361226
Short name T163
Test name
Test status
Simulation time 79383588 ps
CPU time 1.32 seconds
Started Aug 09 07:03:23 PM PDT 24
Finished Aug 09 07:03:24 PM PDT 24
Peak memory 196388 kb
Host smart-5887f873-edc2-494e-a501-5e4140c46227
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518361226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.
518361226
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.1530639352
Short name T272
Test name
Test status
Simulation time 36886705 ps
CPU time 0.91 seconds
Started Aug 09 07:03:21 PM PDT 24
Finished Aug 09 07:03:22 PM PDT 24
Peak memory 196520 kb
Host smart-407f7171-22ec-404f-95e4-989ee33f858d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530639352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.1530639352
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2926462162
Short name T231
Test name
Test status
Simulation time 46337265 ps
CPU time 0.84 seconds
Started Aug 09 07:03:19 PM PDT 24
Finished Aug 09 07:03:20 PM PDT 24
Peak memory 197664 kb
Host smart-4d73b8e4-0f62-46b3-a990-a1848b608da4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926462162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2926462162
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.1252694516
Short name T532
Test name
Test status
Simulation time 294359923 ps
CPU time 3.69 seconds
Started Aug 09 07:03:22 PM PDT 24
Finished Aug 09 07:03:26 PM PDT 24
Peak memory 198516 kb
Host smart-9666e375-13f6-44b3-9071-851b11094f32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252694516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.1252694516
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.434853368
Short name T284
Test name
Test status
Simulation time 81200999 ps
CPU time 0.94 seconds
Started Aug 09 07:03:22 PM PDT 24
Finished Aug 09 07:03:23 PM PDT 24
Peak memory 195816 kb
Host smart-28856244-c8f4-4b1e-8c1a-e362c03bb01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434853368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.434853368
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.1726114693
Short name T599
Test name
Test status
Simulation time 60890806 ps
CPU time 1.13 seconds
Started Aug 09 07:03:21 PM PDT 24
Finished Aug 09 07:03:22 PM PDT 24
Peak memory 196340 kb
Host smart-1119dd78-fd6f-40fd-8a49-af5ecec11454
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726114693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.1726114693
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.421489881
Short name T414
Test name
Test status
Simulation time 41915947815 ps
CPU time 131.89 seconds
Started Aug 09 07:03:22 PM PDT 24
Finished Aug 09 07:05:34 PM PDT 24
Peak memory 198780 kb
Host smart-66627475-d5be-48c8-be88-e444039a02cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421489881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.g
pio_stress_all.421489881
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.2329079064
Short name T685
Test name
Test status
Simulation time 191327581557 ps
CPU time 709.12 seconds
Started Aug 09 07:03:21 PM PDT 24
Finished Aug 09 07:15:10 PM PDT 24
Peak memory 207020 kb
Host smart-d35b2e2a-b070-47a3-b43f-472a6ec0767e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2329079064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.2329079064
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1780126486
Short name T288
Test name
Test status
Simulation time 38749102 ps
CPU time 0.57 seconds
Started Aug 09 07:03:23 PM PDT 24
Finished Aug 09 07:03:24 PM PDT 24
Peak memory 194452 kb
Host smart-0b81d022-9f29-4a8e-83e5-d313311c0547
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780126486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1780126486
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.4004417153
Short name T315
Test name
Test status
Simulation time 17663815 ps
CPU time 0.61 seconds
Started Aug 09 07:03:25 PM PDT 24
Finished Aug 09 07:03:26 PM PDT 24
Peak memory 194456 kb
Host smart-cec10e90-4749-42cc-ad56-850173dc7fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004417153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.4004417153
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.2189444565
Short name T491
Test name
Test status
Simulation time 614703334 ps
CPU time 10.26 seconds
Started Aug 09 07:03:21 PM PDT 24
Finished Aug 09 07:03:31 PM PDT 24
Peak memory 197604 kb
Host smart-fd6210f5-e983-45fe-821b-bab93a30da7d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189444565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.2189444565
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.302403789
Short name T23
Test name
Test status
Simulation time 302063944 ps
CPU time 0.99 seconds
Started Aug 09 07:03:22 PM PDT 24
Finished Aug 09 07:03:23 PM PDT 24
Peak memory 198220 kb
Host smart-450566de-162f-4b36-9ccb-26fee1ac60a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302403789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.302403789
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.349525459
Short name T385
Test name
Test status
Simulation time 37699275 ps
CPU time 1.04 seconds
Started Aug 09 07:03:27 PM PDT 24
Finished Aug 09 07:03:28 PM PDT 24
Peak memory 196544 kb
Host smart-6ddbc965-ccf0-4a91-920e-15f57bf79f15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349525459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.349525459
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.1831846729
Short name T160
Test name
Test status
Simulation time 62399914 ps
CPU time 1.46 seconds
Started Aug 09 07:03:22 PM PDT 24
Finished Aug 09 07:03:23 PM PDT 24
Peak memory 197296 kb
Host smart-be6e506e-04da-4221-90dc-f4d09fe4bb91
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831846729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.1831846729
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.985375388
Short name T152
Test name
Test status
Simulation time 105161775 ps
CPU time 1.76 seconds
Started Aug 09 07:03:27 PM PDT 24
Finished Aug 09 07:03:28 PM PDT 24
Peak memory 196684 kb
Host smart-bcc4e395-bb87-4b9d-9c9c-30eb83523928
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985375388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger.
985375388
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.2906470474
Short name T415
Test name
Test status
Simulation time 171270853 ps
CPU time 1.12 seconds
Started Aug 09 07:03:22 PM PDT 24
Finished Aug 09 07:03:23 PM PDT 24
Peak memory 197072 kb
Host smart-5174151f-606a-4625-acea-5acbd58b5bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906470474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.2906470474
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.4195616346
Short name T244
Test name
Test status
Simulation time 49276510 ps
CPU time 1.18 seconds
Started Aug 09 07:03:20 PM PDT 24
Finished Aug 09 07:03:21 PM PDT 24
Peak memory 197108 kb
Host smart-b9c62137-7424-4513-82ea-58173864cbb2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195616346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.4195616346
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.3767353979
Short name T67
Test name
Test status
Simulation time 51809276 ps
CPU time 2.25 seconds
Started Aug 09 07:03:25 PM PDT 24
Finished Aug 09 07:03:27 PM PDT 24
Peak memory 198556 kb
Host smart-b34779e0-1b24-4497-93a6-b40b68622e17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767353979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.3767353979
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.3969196591
Short name T166
Test name
Test status
Simulation time 248076838 ps
CPU time 1.47 seconds
Started Aug 09 07:03:22 PM PDT 24
Finished Aug 09 07:03:24 PM PDT 24
Peak memory 197304 kb
Host smart-81d3f935-2246-45d4-b050-e307df1f9193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969196591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.3969196591
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.2911071103
Short name T570
Test name
Test status
Simulation time 26327174 ps
CPU time 0.93 seconds
Started Aug 09 07:03:23 PM PDT 24
Finished Aug 09 07:03:24 PM PDT 24
Peak memory 197028 kb
Host smart-a66e95b4-27d5-48e5-8e34-70931f0d6f75
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911071103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.2911071103
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2208718906
Short name T7
Test name
Test status
Simulation time 12389471641 ps
CPU time 32.19 seconds
Started Aug 09 07:03:22 PM PDT 24
Finished Aug 09 07:03:54 PM PDT 24
Peak memory 198752 kb
Host smart-2b555dd7-81de-4ffa-bafb-a656f0ee064b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208718906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2208718906
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2762507702
Short name T473
Test name
Test status
Simulation time 14242773 ps
CPU time 0.6 seconds
Started Aug 09 07:02:15 PM PDT 24
Finished Aug 09 07:02:16 PM PDT 24
Peak memory 194416 kb
Host smart-b6c4f4ac-8d81-4f5c-9f34-b8a01d30106c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762507702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2762507702
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.1525252692
Short name T76
Test name
Test status
Simulation time 54412807 ps
CPU time 0.67 seconds
Started Aug 09 07:02:17 PM PDT 24
Finished Aug 09 07:02:18 PM PDT 24
Peak memory 194660 kb
Host smart-cccfd6a5-3a43-4d31-9d53-605fbea24e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525252692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.1525252692
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.2052995264
Short name T71
Test name
Test status
Simulation time 467313364 ps
CPU time 16.34 seconds
Started Aug 09 07:02:18 PM PDT 24
Finished Aug 09 07:02:34 PM PDT 24
Peak memory 198480 kb
Host smart-47827f5f-67e9-4b2b-b6a6-120a65c47168
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052995264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.2052995264
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.3087769763
Short name T610
Test name
Test status
Simulation time 54506134 ps
CPU time 0.84 seconds
Started Aug 09 07:02:17 PM PDT 24
Finished Aug 09 07:02:18 PM PDT 24
Peak memory 196268 kb
Host smart-eb9e3f65-4ec9-4bbd-9113-c25159169a4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087769763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.3087769763
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.1802317685
Short name T75
Test name
Test status
Simulation time 672314558 ps
CPU time 1.29 seconds
Started Aug 09 07:02:14 PM PDT 24
Finished Aug 09 07:02:16 PM PDT 24
Peak memory 196552 kb
Host smart-d94fedea-6a0d-42cb-9f30-baef818981f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802317685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.1802317685
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1679786526
Short name T120
Test name
Test status
Simulation time 59555545 ps
CPU time 1.45 seconds
Started Aug 09 07:02:16 PM PDT 24
Finished Aug 09 07:02:18 PM PDT 24
Peak memory 198732 kb
Host smart-3dca2139-4692-404e-9383-f61e27525d62
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679786526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1679786526
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.738305549
Short name T245
Test name
Test status
Simulation time 420211295 ps
CPU time 2.34 seconds
Started Aug 09 07:02:14 PM PDT 24
Finished Aug 09 07:02:17 PM PDT 24
Peak memory 198552 kb
Host smart-bc1fe668-70bb-41d2-aeee-1d213bcfc704
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738305549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.738305549
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1427922742
Short name T623
Test name
Test status
Simulation time 21726449 ps
CPU time 0.93 seconds
Started Aug 09 07:02:14 PM PDT 24
Finished Aug 09 07:02:15 PM PDT 24
Peak memory 197088 kb
Host smart-356a65df-b820-47bb-9835-2609590901df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427922742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1427922742
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2562526597
Short name T279
Test name
Test status
Simulation time 128235326 ps
CPU time 1.02 seconds
Started Aug 09 07:02:17 PM PDT 24
Finished Aug 09 07:02:18 PM PDT 24
Peak memory 196420 kb
Host smart-d9c7a16e-4b9b-468c-8a14-5bb6489c2353
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562526597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.2562526597
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.2301733424
Short name T290
Test name
Test status
Simulation time 2219301362 ps
CPU time 5.96 seconds
Started Aug 09 07:02:15 PM PDT 24
Finished Aug 09 07:02:21 PM PDT 24
Peak memory 198712 kb
Host smart-6d84c3e0-d326-4111-886c-11578706ef74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301733424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.2301733424
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.919649029
Short name T48
Test name
Test status
Simulation time 161157506 ps
CPU time 0.78 seconds
Started Aug 09 07:02:17 PM PDT 24
Finished Aug 09 07:02:18 PM PDT 24
Peak memory 214320 kb
Host smart-a7eb8f2f-fed3-43f2-86e6-bd483f3dc7f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919649029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.919649029
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.303999886
Short name T183
Test name
Test status
Simulation time 49219187 ps
CPU time 1.38 seconds
Started Aug 09 07:02:15 PM PDT 24
Finished Aug 09 07:02:17 PM PDT 24
Peak memory 197408 kb
Host smart-4a31eb32-937c-48db-87fc-7b8673ae242a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303999886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.303999886
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3644424437
Short name T294
Test name
Test status
Simulation time 144098378 ps
CPU time 1.04 seconds
Started Aug 09 07:02:16 PM PDT 24
Finished Aug 09 07:02:17 PM PDT 24
Peak memory 196828 kb
Host smart-a7e543b8-59bd-415b-8044-3ef2efd0f967
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644424437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3644424437
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.1865467454
Short name T559
Test name
Test status
Simulation time 4495063256 ps
CPU time 48.94 seconds
Started Aug 09 07:02:17 PM PDT 24
Finished Aug 09 07:03:06 PM PDT 24
Peak memory 198748 kb
Host smart-7dff8c73-ab2d-400a-8ee0-e463bd4eb641
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865467454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.1865467454
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.3848273934
Short name T62
Test name
Test status
Simulation time 223720395692 ps
CPU time 1511.99 seconds
Started Aug 09 07:02:15 PM PDT 24
Finished Aug 09 07:27:27 PM PDT 24
Peak memory 198836 kb
Host smart-d03a1f3e-a082-40af-a30f-32fd98b2357a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3848273934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.3848273934
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.1573698026
Short name T514
Test name
Test status
Simulation time 47518674 ps
CPU time 0.57 seconds
Started Aug 09 07:03:27 PM PDT 24
Finished Aug 09 07:03:28 PM PDT 24
Peak memory 194496 kb
Host smart-d8f9433a-5f77-4a86-9b93-8a6415f95161
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573698026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1573698026
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.519226134
Short name T324
Test name
Test status
Simulation time 59614269 ps
CPU time 0.9 seconds
Started Aug 09 07:03:24 PM PDT 24
Finished Aug 09 07:03:25 PM PDT 24
Peak memory 196536 kb
Host smart-bd5f1156-b9d1-4fb2-8726-cd119ac1079e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519226134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.519226134
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2312592566
Short name T477
Test name
Test status
Simulation time 625650193 ps
CPU time 8.35 seconds
Started Aug 09 07:03:30 PM PDT 24
Finished Aug 09 07:03:38 PM PDT 24
Peak memory 196036 kb
Host smart-6c79085a-c769-4ec2-9193-98698b20dc29
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312592566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2312592566
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.3086539949
Short name T511
Test name
Test status
Simulation time 239247738 ps
CPU time 0.66 seconds
Started Aug 09 07:03:34 PM PDT 24
Finished Aug 09 07:03:35 PM PDT 24
Peak memory 195036 kb
Host smart-846d8a7d-15b3-4f4a-babe-de66558e0f9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086539949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3086539949
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.2367048841
Short name T186
Test name
Test status
Simulation time 112978493 ps
CPU time 1.46 seconds
Started Aug 09 07:03:22 PM PDT 24
Finished Aug 09 07:03:24 PM PDT 24
Peak memory 197332 kb
Host smart-77cffded-0e27-487b-ae0c-831ecd9b997b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367048841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2367048841
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3297277642
Short name T373
Test name
Test status
Simulation time 238000696 ps
CPU time 2.6 seconds
Started Aug 09 07:03:30 PM PDT 24
Finished Aug 09 07:03:32 PM PDT 24
Peak memory 198560 kb
Host smart-85adbe64-33f3-4106-95ad-21fc0a0d3e63
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297277642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3297277642
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2175304508
Short name T227
Test name
Test status
Simulation time 370730897 ps
CPU time 2.93 seconds
Started Aug 09 07:03:31 PM PDT 24
Finished Aug 09 07:03:34 PM PDT 24
Peak memory 198584 kb
Host smart-4ab21418-7f40-4d60-93d8-3f3fb2ebacfc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175304508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2175304508
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.2190899976
Short name T318
Test name
Test status
Simulation time 53377215 ps
CPU time 1.06 seconds
Started Aug 09 07:03:20 PM PDT 24
Finished Aug 09 07:03:21 PM PDT 24
Peak memory 197088 kb
Host smart-00a9501e-cf2a-4fc1-b7f3-3b8107eb8904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190899976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.2190899976
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2058136055
Short name T238
Test name
Test status
Simulation time 34334066 ps
CPU time 0.67 seconds
Started Aug 09 07:03:23 PM PDT 24
Finished Aug 09 07:03:23 PM PDT 24
Peak memory 195568 kb
Host smart-0993ace7-c1a1-4880-b6bb-b18a0f731431
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058136055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2058136055
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2500286013
Short name T4
Test name
Test status
Simulation time 854296395 ps
CPU time 4.94 seconds
Started Aug 09 07:03:30 PM PDT 24
Finished Aug 09 07:03:35 PM PDT 24
Peak memory 198548 kb
Host smart-aea1faaa-274b-4eab-b222-d9bc2a3362d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500286013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2500286013
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.2465147311
Short name T292
Test name
Test status
Simulation time 128717934 ps
CPU time 1.27 seconds
Started Aug 09 07:03:22 PM PDT 24
Finished Aug 09 07:03:23 PM PDT 24
Peak memory 197264 kb
Host smart-d388b5fe-ecec-4ccd-8492-44e8691364fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465147311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.2465147311
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.1013471634
Short name T215
Test name
Test status
Simulation time 56017077 ps
CPU time 1.03 seconds
Started Aug 09 07:03:21 PM PDT 24
Finished Aug 09 07:03:22 PM PDT 24
Peak memory 196296 kb
Host smart-6bfa3e14-02bc-4aa0-b109-bd4d0d9d7738
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013471634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.1013471634
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.1220358572
Short name T230
Test name
Test status
Simulation time 12422475366 ps
CPU time 179 seconds
Started Aug 09 07:03:32 PM PDT 24
Finished Aug 09 07:06:31 PM PDT 24
Peak memory 198764 kb
Host smart-d85cf7c4-d140-4abc-a1fb-72e90eb5b737
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220358572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.1220358572
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.447417684
Short name T108
Test name
Test status
Simulation time 89161117318 ps
CPU time 575.92 seconds
Started Aug 09 07:03:29 PM PDT 24
Finished Aug 09 07:13:05 PM PDT 24
Peak memory 198888 kb
Host smart-8866d6ba-5beb-4c05-a9b6-89efabba500d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=447417684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.447417684
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.485867119
Short name T635
Test name
Test status
Simulation time 12969346 ps
CPU time 0.61 seconds
Started Aug 09 07:03:30 PM PDT 24
Finished Aug 09 07:03:30 PM PDT 24
Peak memory 194480 kb
Host smart-39f4e096-ffe8-4ae9-a941-d6df395fde28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485867119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.485867119
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.504755183
Short name T380
Test name
Test status
Simulation time 22803472 ps
CPU time 0.78 seconds
Started Aug 09 07:03:33 PM PDT 24
Finished Aug 09 07:03:34 PM PDT 24
Peak memory 195860 kb
Host smart-0bbbc00c-d119-40ca-84de-4edd39bcb525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504755183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.504755183
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1391167925
Short name T439
Test name
Test status
Simulation time 517517976 ps
CPU time 26.34 seconds
Started Aug 09 07:03:30 PM PDT 24
Finished Aug 09 07:03:56 PM PDT 24
Peak memory 198584 kb
Host smart-2def89ec-e8a2-4ac1-aca6-dfee5499a85e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391167925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1391167925
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.1679140556
Short name T684
Test name
Test status
Simulation time 126968118 ps
CPU time 0.9 seconds
Started Aug 09 07:03:30 PM PDT 24
Finished Aug 09 07:03:31 PM PDT 24
Peak memory 197656 kb
Host smart-52066ac1-99a5-4352-b9b0-aafe4f936aa3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679140556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.1679140556
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3986667755
Short name T345
Test name
Test status
Simulation time 281184669 ps
CPU time 1.31 seconds
Started Aug 09 07:03:29 PM PDT 24
Finished Aug 09 07:03:30 PM PDT 24
Peak memory 197716 kb
Host smart-8ae7ee32-f2ba-47a4-a5b1-a718f85e4724
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986667755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3986667755
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.471884797
Short name T24
Test name
Test status
Simulation time 185302403 ps
CPU time 1.92 seconds
Started Aug 09 07:03:31 PM PDT 24
Finished Aug 09 07:03:33 PM PDT 24
Peak memory 198536 kb
Host smart-d93c6f4d-9d24-4180-92f8-6546a83c9583
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471884797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.gpio_intr_with_filter_rand_intr_event.471884797
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.3792552856
Short name T715
Test name
Test status
Simulation time 109497001 ps
CPU time 2.44 seconds
Started Aug 09 07:03:32 PM PDT 24
Finished Aug 09 07:03:34 PM PDT 24
Peak memory 198504 kb
Host smart-602d4820-2145-41b4-a113-d7b48908e312
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792552856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.3792552856
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.3184790631
Short name T704
Test name
Test status
Simulation time 24342431 ps
CPU time 0.83 seconds
Started Aug 09 07:03:30 PM PDT 24
Finished Aug 09 07:03:31 PM PDT 24
Peak memory 196580 kb
Host smart-d7dd1933-b5ab-427f-982f-7d1547f914e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184790631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.3184790631
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.1441929133
Short name T479
Test name
Test status
Simulation time 35028347 ps
CPU time 0.89 seconds
Started Aug 09 07:03:34 PM PDT 24
Finished Aug 09 07:03:35 PM PDT 24
Peak memory 197184 kb
Host smart-828a80f8-3c4a-483b-83f3-a6a2853d97a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441929133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.1441929133
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2997387371
Short name T716
Test name
Test status
Simulation time 581606588 ps
CPU time 5.21 seconds
Started Aug 09 07:03:30 PM PDT 24
Finished Aug 09 07:03:35 PM PDT 24
Peak memory 198452 kb
Host smart-e4c55571-ee5d-4df0-9e5c-6e6058532f1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997387371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2997387371
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3783738050
Short name T609
Test name
Test status
Simulation time 123032449 ps
CPU time 0.86 seconds
Started Aug 09 07:03:33 PM PDT 24
Finished Aug 09 07:03:34 PM PDT 24
Peak memory 196948 kb
Host smart-b93c194e-2e9a-4d94-8374-bb0f5670c661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783738050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3783738050
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.3939779728
Short name T323
Test name
Test status
Simulation time 100876186 ps
CPU time 1.06 seconds
Started Aug 09 07:03:29 PM PDT 24
Finished Aug 09 07:03:30 PM PDT 24
Peak memory 197096 kb
Host smart-dfaea003-c1e3-4a16-817f-9898c021cb87
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939779728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.3939779728
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.2400799940
Short name T117
Test name
Test status
Simulation time 25509298084 ps
CPU time 177.69 seconds
Started Aug 09 07:03:32 PM PDT 24
Finished Aug 09 07:06:30 PM PDT 24
Peak memory 198760 kb
Host smart-cc09b728-bf90-42c5-9ef9-45e9b986523b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400799940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.2400799940
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.3932756104
Short name T565
Test name
Test status
Simulation time 13589967 ps
CPU time 0.57 seconds
Started Aug 09 07:03:29 PM PDT 24
Finished Aug 09 07:03:29 PM PDT 24
Peak memory 195200 kb
Host smart-40149b6a-04e7-4c54-8809-f3a6b3725600
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932756104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.3932756104
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2404858880
Short name T569
Test name
Test status
Simulation time 29988636 ps
CPU time 0.9 seconds
Started Aug 09 07:03:29 PM PDT 24
Finished Aug 09 07:03:30 PM PDT 24
Peak memory 196408 kb
Host smart-c092e41b-89ea-4f3b-90f5-ee3a996b40ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404858880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2404858880
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.1712801767
Short name T428
Test name
Test status
Simulation time 1136067793 ps
CPU time 7.45 seconds
Started Aug 09 07:03:29 PM PDT 24
Finished Aug 09 07:03:36 PM PDT 24
Peak memory 196080 kb
Host smart-848eb90b-3628-48b4-9946-965bd3b4bb37
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712801767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.1712801767
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1467236843
Short name T543
Test name
Test status
Simulation time 37985662 ps
CPU time 0.8 seconds
Started Aug 09 07:03:30 PM PDT 24
Finished Aug 09 07:03:31 PM PDT 24
Peak memory 197164 kb
Host smart-442ed00b-d30e-4e24-82b3-393b66357d26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467236843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1467236843
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.423311841
Short name T520
Test name
Test status
Simulation time 92853723 ps
CPU time 0.9 seconds
Started Aug 09 07:03:30 PM PDT 24
Finished Aug 09 07:03:31 PM PDT 24
Peak memory 197864 kb
Host smart-c5eb693c-70c2-4233-9900-6eea8cd71cb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423311841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.423311841
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.1175685537
Short name T575
Test name
Test status
Simulation time 240375362 ps
CPU time 2.7 seconds
Started Aug 09 07:03:32 PM PDT 24
Finished Aug 09 07:03:35 PM PDT 24
Peak memory 198496 kb
Host smart-4636491a-78a5-44fd-8ddd-0791679f71de
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175685537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.1175685537
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.250240719
Short name T386
Test name
Test status
Simulation time 243116824 ps
CPU time 1.77 seconds
Started Aug 09 07:03:28 PM PDT 24
Finished Aug 09 07:03:30 PM PDT 24
Peak memory 197012 kb
Host smart-26277c2d-8baf-44ae-80ba-2b307a576b93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250240719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.
250240719
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.387336922
Short name T280
Test name
Test status
Simulation time 34755785 ps
CPU time 0.85 seconds
Started Aug 09 07:03:29 PM PDT 24
Finished Aug 09 07:03:29 PM PDT 24
Peak memory 195776 kb
Host smart-0433b76a-a513-48ae-a7ea-31df85ef7056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387336922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.387336922
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.3528780556
Short name T342
Test name
Test status
Simulation time 155223938 ps
CPU time 1.25 seconds
Started Aug 09 07:03:32 PM PDT 24
Finished Aug 09 07:03:33 PM PDT 24
Peak memory 197480 kb
Host smart-9d86902d-3f98-4749-99ff-549f22ed5d88
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528780556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.3528780556
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_smoke.3020438695
Short name T251
Test name
Test status
Simulation time 112112580 ps
CPU time 1 seconds
Started Aug 09 07:03:31 PM PDT 24
Finished Aug 09 07:03:32 PM PDT 24
Peak memory 196392 kb
Host smart-6385af8b-3e23-458f-841d-28fa5c361639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020438695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.3020438695
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.974626223
Short name T413
Test name
Test status
Simulation time 107711516 ps
CPU time 0.98 seconds
Started Aug 09 07:03:30 PM PDT 24
Finished Aug 09 07:03:31 PM PDT 24
Peak memory 196300 kb
Host smart-9871f4eb-1709-498d-a21c-302cdf741ee0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974626223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.974626223
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.1989984012
Short name T147
Test name
Test status
Simulation time 1613494569 ps
CPU time 18.71 seconds
Started Aug 09 07:03:32 PM PDT 24
Finished Aug 09 07:03:51 PM PDT 24
Peak memory 198892 kb
Host smart-b8faf265-4765-469a-8f1e-f045f5017c74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989984012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.1989984012
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.3839589424
Short name T562
Test name
Test status
Simulation time 87262409320 ps
CPU time 1407.75 seconds
Started Aug 09 07:03:30 PM PDT 24
Finished Aug 09 07:26:58 PM PDT 24
Peak memory 198896 kb
Host smart-91098be6-fc22-412c-be35-551c46fd165c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3839589424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.3839589424
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.138932025
Short name T505
Test name
Test status
Simulation time 11965708 ps
CPU time 0.59 seconds
Started Aug 09 07:03:38 PM PDT 24
Finished Aug 09 07:03:39 PM PDT 24
Peak memory 194716 kb
Host smart-803ca5fb-04e5-4041-b7d5-0a625f6ce795
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138932025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.138932025
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.1416711488
Short name T459
Test name
Test status
Simulation time 29445342 ps
CPU time 0.68 seconds
Started Aug 09 07:03:39 PM PDT 24
Finished Aug 09 07:03:40 PM PDT 24
Peak memory 194680 kb
Host smart-84d81048-67e9-419c-a039-f6daccbd8d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416711488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.1416711488
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.796149948
Short name T264
Test name
Test status
Simulation time 647375798 ps
CPU time 15.49 seconds
Started Aug 09 07:03:38 PM PDT 24
Finished Aug 09 07:03:54 PM PDT 24
Peak memory 196044 kb
Host smart-5c9a234b-07e3-41a6-9c6a-ce6c75b926c1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796149948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stres
s.796149948
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.3850196395
Short name T624
Test name
Test status
Simulation time 243089514 ps
CPU time 0.99 seconds
Started Aug 09 07:03:40 PM PDT 24
Finished Aug 09 07:03:41 PM PDT 24
Peak memory 197060 kb
Host smart-e2cae19c-cd1e-4cc0-9e07-134bba5ced87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850196395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.3850196395
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.1396100487
Short name T300
Test name
Test status
Simulation time 33076343 ps
CPU time 0.7 seconds
Started Aug 09 07:03:37 PM PDT 24
Finished Aug 09 07:03:38 PM PDT 24
Peak memory 194904 kb
Host smart-0570ab58-318e-405c-a7c4-3dd8e21e20de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396100487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.1396100487
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.396888945
Short name T200
Test name
Test status
Simulation time 56486852 ps
CPU time 2.27 seconds
Started Aug 09 07:03:39 PM PDT 24
Finished Aug 09 07:03:41 PM PDT 24
Peak memory 196868 kb
Host smart-cf1211d9-d6d1-46c5-911f-9f38b6a82fe1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396888945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.gpio_intr_with_filter_rand_intr_event.396888945
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.778098881
Short name T118
Test name
Test status
Simulation time 111631988 ps
CPU time 1.8 seconds
Started Aug 09 07:03:38 PM PDT 24
Finished Aug 09 07:03:39 PM PDT 24
Peak memory 197344 kb
Host smart-d46779eb-4e4b-4de3-82cb-fa02ae43582a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778098881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.
778098881
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.3140045188
Short name T228
Test name
Test status
Simulation time 147448723 ps
CPU time 0.78 seconds
Started Aug 09 07:03:37 PM PDT 24
Finished Aug 09 07:03:38 PM PDT 24
Peak memory 196044 kb
Host smart-e2bd8aa6-72fb-4503-94d9-dc6071be3080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140045188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.3140045188
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.305349147
Short name T184
Test name
Test status
Simulation time 59033884 ps
CPU time 0.78 seconds
Started Aug 09 07:03:37 PM PDT 24
Finished Aug 09 07:03:38 PM PDT 24
Peak memory 195940 kb
Host smart-342f9d8a-fe4e-4133-8cb7-1ac620cac0ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305349147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup
_pulldown.305349147
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.191328625
Short name T266
Test name
Test status
Simulation time 130088384 ps
CPU time 2.09 seconds
Started Aug 09 07:03:38 PM PDT 24
Finished Aug 09 07:03:40 PM PDT 24
Peak memory 198548 kb
Host smart-201ecd0b-a449-42b2-ad25-7fc5011ea6a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191328625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ran
dom_long_reg_writes_reg_reads.191328625
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.1110115866
Short name T613
Test name
Test status
Simulation time 228943563 ps
CPU time 1.07 seconds
Started Aug 09 07:03:39 PM PDT 24
Finished Aug 09 07:03:41 PM PDT 24
Peak memory 196104 kb
Host smart-c5997d75-6814-412e-87f7-6508c4bb7718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110115866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.1110115866
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.2161055649
Short name T497
Test name
Test status
Simulation time 55242940 ps
CPU time 1.11 seconds
Started Aug 09 07:03:38 PM PDT 24
Finished Aug 09 07:03:39 PM PDT 24
Peak memory 196912 kb
Host smart-6c65ade2-8c37-4daa-9de5-9d42e4372835
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161055649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.2161055649
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.2702104608
Short name T444
Test name
Test status
Simulation time 15728215704 ps
CPU time 57.7 seconds
Started Aug 09 07:03:35 PM PDT 24
Finished Aug 09 07:04:33 PM PDT 24
Peak memory 198712 kb
Host smart-1c867cc6-ef76-4eb5-97dc-3504ff7aba96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702104608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.2702104608
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.2462356778
Short name T59
Test name
Test status
Simulation time 61647359170 ps
CPU time 1233.14 seconds
Started Aug 09 07:03:37 PM PDT 24
Finished Aug 09 07:24:10 PM PDT 24
Peak memory 198816 kb
Host smart-d7a631a9-657b-4563-8a58-accfbff6cef4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2462356778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.2462356778
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.152521583
Short name T396
Test name
Test status
Simulation time 31056348 ps
CPU time 0.57 seconds
Started Aug 09 07:03:37 PM PDT 24
Finished Aug 09 07:03:38 PM PDT 24
Peak memory 195188 kb
Host smart-83c2a1fa-6c8d-44ef-b043-4dade66e6c2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152521583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.152521583
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.589288692
Short name T625
Test name
Test status
Simulation time 44464763 ps
CPU time 0.82 seconds
Started Aug 09 07:03:37 PM PDT 24
Finished Aug 09 07:03:38 PM PDT 24
Peak memory 196808 kb
Host smart-4c9494f5-1bf6-4b38-a9af-5ebca820241b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589288692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.589288692
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.3091222237
Short name T480
Test name
Test status
Simulation time 77515150 ps
CPU time 3.93 seconds
Started Aug 09 07:03:39 PM PDT 24
Finished Aug 09 07:03:43 PM PDT 24
Peak memory 196832 kb
Host smart-bae9650b-3b46-4180-9187-e4325827d1ec
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091222237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.3091222237
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.1286930578
Short name T208
Test name
Test status
Simulation time 469740938 ps
CPU time 1.04 seconds
Started Aug 09 07:03:38 PM PDT 24
Finished Aug 09 07:03:39 PM PDT 24
Peak memory 198412 kb
Host smart-424014e1-05ca-4bc6-885b-9e0ea754416b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286930578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.1286930578
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.3777009133
Short name T267
Test name
Test status
Simulation time 51632181 ps
CPU time 1.01 seconds
Started Aug 09 07:03:37 PM PDT 24
Finished Aug 09 07:03:38 PM PDT 24
Peak memory 196544 kb
Host smart-26c72c20-109e-4ae6-b8d8-8188a0a8d5b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777009133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.3777009133
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1955880798
Short name T542
Test name
Test status
Simulation time 159232625 ps
CPU time 1.65 seconds
Started Aug 09 07:03:40 PM PDT 24
Finished Aug 09 07:03:41 PM PDT 24
Peak memory 197128 kb
Host smart-66703694-7a8a-4272-89d4-66ec07afef25
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955880798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1955880798
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2892651739
Short name T681
Test name
Test status
Simulation time 112420243 ps
CPU time 1.3 seconds
Started Aug 09 07:03:38 PM PDT 24
Finished Aug 09 07:03:39 PM PDT 24
Peak memory 197060 kb
Host smart-5dec503e-49de-47ba-8129-604d3fa8d239
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892651739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2892651739
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.2312250353
Short name T185
Test name
Test status
Simulation time 24138810 ps
CPU time 0.84 seconds
Started Aug 09 07:03:37 PM PDT 24
Finished Aug 09 07:03:38 PM PDT 24
Peak memory 197128 kb
Host smart-eb9805a7-736c-4b72-8e84-50284b745d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312250353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2312250353
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.3877162543
Short name T367
Test name
Test status
Simulation time 46524260 ps
CPU time 0.76 seconds
Started Aug 09 07:03:36 PM PDT 24
Finished Aug 09 07:03:37 PM PDT 24
Peak memory 195892 kb
Host smart-900de5d7-904d-4dd5-8d40-667dc93f0990
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877162543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.3877162543
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2635153122
Short name T440
Test name
Test status
Simulation time 291790581 ps
CPU time 2.65 seconds
Started Aug 09 07:03:37 PM PDT 24
Finished Aug 09 07:03:40 PM PDT 24
Peak memory 198496 kb
Host smart-e8ade027-6343-4c0c-a35d-f7db498bb7f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635153122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2635153122
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.1571898867
Short name T182
Test name
Test status
Simulation time 119562324 ps
CPU time 1.24 seconds
Started Aug 09 07:03:39 PM PDT 24
Finished Aug 09 07:03:41 PM PDT 24
Peak memory 196392 kb
Host smart-3507fe71-a04e-4cc2-93ea-91b015780dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571898867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.1571898867
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2388334565
Short name T402
Test name
Test status
Simulation time 31439463 ps
CPU time 0.94 seconds
Started Aug 09 07:03:37 PM PDT 24
Finished Aug 09 07:03:39 PM PDT 24
Peak memory 197040 kb
Host smart-0e844b69-ffc9-4543-8b72-01a646f9df41
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388334565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2388334565
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2921877453
Short name T5
Test name
Test status
Simulation time 57644118219 ps
CPU time 144.59 seconds
Started Aug 09 07:03:38 PM PDT 24
Finished Aug 09 07:06:03 PM PDT 24
Peak memory 198796 kb
Host smart-281642ef-be2e-45d1-b18c-386eb06b04dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921877453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2921877453
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.220279655
Short name T333
Test name
Test status
Simulation time 12232705 ps
CPU time 0.57 seconds
Started Aug 09 07:03:45 PM PDT 24
Finished Aug 09 07:03:46 PM PDT 24
Peak memory 195172 kb
Host smart-7f44dbd2-6418-46c0-8d82-f4a9f349f2ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220279655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.220279655
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.1366646411
Short name T475
Test name
Test status
Simulation time 98383888 ps
CPU time 0.65 seconds
Started Aug 09 07:03:36 PM PDT 24
Finished Aug 09 07:03:37 PM PDT 24
Peak memory 194440 kb
Host smart-1cad7e5c-0f4c-49cb-a6f6-8223ccde0f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366646411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.1366646411
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1236262053
Short name T679
Test name
Test status
Simulation time 638668207 ps
CPU time 23.17 seconds
Started Aug 09 07:03:38 PM PDT 24
Finished Aug 09 07:04:02 PM PDT 24
Peak memory 198596 kb
Host smart-a517d9c4-1dcf-470e-8588-e1fbb1816b84
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236262053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1236262053
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2020745103
Short name T193
Test name
Test status
Simulation time 83769033 ps
CPU time 1.06 seconds
Started Aug 09 07:03:39 PM PDT 24
Finished Aug 09 07:03:40 PM PDT 24
Peak memory 197228 kb
Host smart-be245724-2a84-4ef6-8500-672ad61526a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020745103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2020745103
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.2757937228
Short name T356
Test name
Test status
Simulation time 68095246 ps
CPU time 1 seconds
Started Aug 09 07:03:36 PM PDT 24
Finished Aug 09 07:03:37 PM PDT 24
Peak memory 196672 kb
Host smart-99380c2c-22a5-40f4-aa76-e84852682562
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757937228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.2757937228
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.1782257018
Short name T335
Test name
Test status
Simulation time 46759179 ps
CPU time 1.03 seconds
Started Aug 09 07:03:38 PM PDT 24
Finished Aug 09 07:03:39 PM PDT 24
Peak memory 196592 kb
Host smart-9c0136c8-b9da-481e-b5bd-e9b887820b57
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782257018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.1782257018
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.2866458071
Short name T297
Test name
Test status
Simulation time 55162226 ps
CPU time 1.36 seconds
Started Aug 09 07:03:36 PM PDT 24
Finished Aug 09 07:03:38 PM PDT 24
Peak memory 197860 kb
Host smart-a312b9ec-a998-4f6b-8ed5-aedfe2df4abb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866458071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.2866458071
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3086933080
Short name T426
Test name
Test status
Simulation time 16433205 ps
CPU time 0.71 seconds
Started Aug 09 07:03:36 PM PDT 24
Finished Aug 09 07:03:37 PM PDT 24
Peak memory 194872 kb
Host smart-91494fd8-a690-4880-a31c-ea9583a09a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086933080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3086933080
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.2792062935
Short name T442
Test name
Test status
Simulation time 32150984 ps
CPU time 1.08 seconds
Started Aug 09 07:03:38 PM PDT 24
Finished Aug 09 07:03:39 PM PDT 24
Peak memory 196360 kb
Host smart-898c1256-68a2-4755-bfaf-9b753389e36a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792062935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.2792062935
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.144779196
Short name T234
Test name
Test status
Simulation time 176336560 ps
CPU time 3.16 seconds
Started Aug 09 07:03:38 PM PDT 24
Finished Aug 09 07:03:41 PM PDT 24
Peak memory 198520 kb
Host smart-fd942e5e-3912-435a-9215-a8fa0e437893
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144779196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ran
dom_long_reg_writes_reg_reads.144779196
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2553348926
Short name T132
Test name
Test status
Simulation time 59727441 ps
CPU time 1.22 seconds
Started Aug 09 07:03:38 PM PDT 24
Finished Aug 09 07:03:39 PM PDT 24
Peak memory 196236 kb
Host smart-89bdf04a-d3c4-460e-b7ff-d72eacae8010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553348926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2553348926
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.4212441766
Short name T579
Test name
Test status
Simulation time 22621720 ps
CPU time 0.78 seconds
Started Aug 09 07:03:36 PM PDT 24
Finished Aug 09 07:03:37 PM PDT 24
Peak memory 196596 kb
Host smart-e2268848-7bac-4389-9a93-85f4052b925d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212441766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.4212441766
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.977590740
Short name T461
Test name
Test status
Simulation time 15802772445 ps
CPU time 113.87 seconds
Started Aug 09 07:03:36 PM PDT 24
Finished Aug 09 07:05:30 PM PDT 24
Peak memory 198708 kb
Host smart-22ad803e-31f3-48a5-9f5e-e4f5ee0874f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977590740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.g
pio_stress_all.977590740
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.3954737644
Short name T9
Test name
Test status
Simulation time 80189953626 ps
CPU time 776.15 seconds
Started Aug 09 07:03:38 PM PDT 24
Finished Aug 09 07:16:35 PM PDT 24
Peak memory 198852 kb
Host smart-8ec83c38-4135-46ea-87cc-295f340dc64d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3954737644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.3954737644
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.4258415332
Short name T37
Test name
Test status
Simulation time 18509609 ps
CPU time 0.62 seconds
Started Aug 09 07:03:58 PM PDT 24
Finished Aug 09 07:03:59 PM PDT 24
Peak memory 194508 kb
Host smart-f328d397-717e-4737-978c-0454f9aadc6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258415332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.4258415332
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.2893644039
Short name T348
Test name
Test status
Simulation time 144029491 ps
CPU time 0.83 seconds
Started Aug 09 07:03:44 PM PDT 24
Finished Aug 09 07:03:45 PM PDT 24
Peak memory 196640 kb
Host smart-c0199a47-e73d-494c-8da1-9816c6e4ff6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893644039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.2893644039
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.220288990
Short name T665
Test name
Test status
Simulation time 565941368 ps
CPU time 9.88 seconds
Started Aug 09 07:03:58 PM PDT 24
Finished Aug 09 07:04:08 PM PDT 24
Peak memory 198484 kb
Host smart-939a20f6-802d-47ee-85de-2069e7697ab6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220288990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stres
s.220288990
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.777530436
Short name T337
Test name
Test status
Simulation time 63306148 ps
CPU time 0.81 seconds
Started Aug 09 07:03:59 PM PDT 24
Finished Aug 09 07:04:00 PM PDT 24
Peak memory 196448 kb
Host smart-c4eba932-8168-400d-94a7-a434d3dbff83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777530436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.777530436
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.3755315033
Short name T360
Test name
Test status
Simulation time 39090526 ps
CPU time 0.84 seconds
Started Aug 09 07:03:46 PM PDT 24
Finished Aug 09 07:03:47 PM PDT 24
Peak memory 196872 kb
Host smart-f9b17865-a296-4a2e-8553-a84a9f0ae1c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755315033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.3755315033
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.668408936
Short name T17
Test name
Test status
Simulation time 98670269 ps
CPU time 2.89 seconds
Started Aug 09 07:03:58 PM PDT 24
Finished Aug 09 07:04:01 PM PDT 24
Peak memory 198692 kb
Host smart-02e9e062-71b0-4d62-9fcb-08075e9a90b3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668408936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.gpio_intr_with_filter_rand_intr_event.668408936
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.1074583668
Short name T346
Test name
Test status
Simulation time 325072903 ps
CPU time 2.76 seconds
Started Aug 09 07:03:49 PM PDT 24
Finished Aug 09 07:03:51 PM PDT 24
Peak memory 198648 kb
Host smart-2d06f2eb-3f02-4a11-9640-a4b1ed668738
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074583668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.1074583668
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.3161962056
Short name T239
Test name
Test status
Simulation time 121063686 ps
CPU time 0.83 seconds
Started Aug 09 07:03:45 PM PDT 24
Finished Aug 09 07:03:46 PM PDT 24
Peak memory 195992 kb
Host smart-eb00d5c9-2d01-4f87-a7df-acfd8f455c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161962056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.3161962056
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.3741335919
Short name T620
Test name
Test status
Simulation time 36360700 ps
CPU time 0.93 seconds
Started Aug 09 07:03:44 PM PDT 24
Finished Aug 09 07:03:45 PM PDT 24
Peak memory 196348 kb
Host smart-46603c10-a041-48e4-9a43-43131f4e7709
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741335919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.3741335919
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.3555226163
Short name T572
Test name
Test status
Simulation time 684680646 ps
CPU time 4.54 seconds
Started Aug 09 07:03:58 PM PDT 24
Finished Aug 09 07:04:03 PM PDT 24
Peak memory 198516 kb
Host smart-6c046159-c123-4805-b593-c4d67a3696a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555226163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.3555226163
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.4054754573
Short name T549
Test name
Test status
Simulation time 87066709 ps
CPU time 1.36 seconds
Started Aug 09 07:03:45 PM PDT 24
Finished Aug 09 07:03:47 PM PDT 24
Peak memory 198608 kb
Host smart-1eb02e6d-044c-4f49-9a03-46a0b56a0ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054754573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.4054754573
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.4071919483
Short name T410
Test name
Test status
Simulation time 267669126 ps
CPU time 1.17 seconds
Started Aug 09 07:03:45 PM PDT 24
Finished Aug 09 07:03:46 PM PDT 24
Peak memory 196080 kb
Host smart-3a343e1e-d573-4a82-b71e-9bd4427a56ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071919483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.4071919483
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.3558671673
Short name T2
Test name
Test status
Simulation time 17417130483 ps
CPU time 199.49 seconds
Started Aug 09 07:03:57 PM PDT 24
Finished Aug 09 07:07:17 PM PDT 24
Peak memory 198740 kb
Host smart-806f1fad-d296-4ad5-a68a-60a3ff5c83c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558671673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.3558671673
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.2153901239
Short name T107
Test name
Test status
Simulation time 250186069235 ps
CPU time 1848.93 seconds
Started Aug 09 07:03:57 PM PDT 24
Finished Aug 09 07:34:47 PM PDT 24
Peak memory 198852 kb
Host smart-3ec19e55-5aa5-4c30-9693-72b9604bd9b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2153901239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.2153901239
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.2741469722
Short name T371
Test name
Test status
Simulation time 29830660 ps
CPU time 0.55 seconds
Started Aug 09 07:03:56 PM PDT 24
Finished Aug 09 07:03:56 PM PDT 24
Peak memory 195144 kb
Host smart-6772a50e-d948-4275-af7f-595976fccc45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741469722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.2741469722
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.4134064487
Short name T707
Test name
Test status
Simulation time 31235653 ps
CPU time 0.68 seconds
Started Aug 09 07:03:57 PM PDT 24
Finished Aug 09 07:03:58 PM PDT 24
Peak memory 194564 kb
Host smart-89ce880c-ab77-4481-af86-2efd83835c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134064487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.4134064487
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.2116928324
Short name T173
Test name
Test status
Simulation time 471042232 ps
CPU time 24.09 seconds
Started Aug 09 07:03:55 PM PDT 24
Finished Aug 09 07:04:19 PM PDT 24
Peak memory 198540 kb
Host smart-276ed303-7084-47d4-a6a3-e1ec0ab0f808
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116928324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.2116928324
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.1962986513
Short name T22
Test name
Test status
Simulation time 78181700 ps
CPU time 0.63 seconds
Started Aug 09 07:03:56 PM PDT 24
Finished Aug 09 07:03:57 PM PDT 24
Peak memory 194996 kb
Host smart-1fe6cec9-769b-45ae-8c0d-ca71dd36f680
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962986513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.1962986513
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.484695485
Short name T659
Test name
Test status
Simulation time 108794222 ps
CPU time 1.36 seconds
Started Aug 09 07:03:57 PM PDT 24
Finished Aug 09 07:03:59 PM PDT 24
Peak memory 196304 kb
Host smart-b92a2762-5224-4a56-af61-03100666f67c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484695485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.484695485
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.1217839760
Short name T548
Test name
Test status
Simulation time 62179376 ps
CPU time 1.41 seconds
Started Aug 09 07:03:54 PM PDT 24
Finished Aug 09 07:03:55 PM PDT 24
Peak memory 197252 kb
Host smart-2da326a8-c497-4fec-862a-35147bc3a7ba
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217839760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.1217839760
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3192371922
Short name T617
Test name
Test status
Simulation time 84669542 ps
CPU time 1.48 seconds
Started Aug 09 07:03:57 PM PDT 24
Finished Aug 09 07:03:59 PM PDT 24
Peak memory 196376 kb
Host smart-a2800580-c372-4833-8a38-d3f3a91ee0a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192371922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3192371922
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.4009431159
Short name T526
Test name
Test status
Simulation time 21807143 ps
CPU time 0.92 seconds
Started Aug 09 07:03:59 PM PDT 24
Finished Aug 09 07:04:00 PM PDT 24
Peak memory 196596 kb
Host smart-0e5b070e-8c14-4891-8c7e-33a20246dd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009431159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.4009431159
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.576723557
Short name T291
Test name
Test status
Simulation time 118771735 ps
CPU time 1.09 seconds
Started Aug 09 07:03:59 PM PDT 24
Finished Aug 09 07:04:00 PM PDT 24
Peak memory 196400 kb
Host smart-44a35da4-3622-4919-9db6-8a1b4da7e120
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576723557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullup
_pulldown.576723557
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.344387241
Short name T64
Test name
Test status
Simulation time 483641803 ps
CPU time 4.09 seconds
Started Aug 09 07:03:57 PM PDT 24
Finished Aug 09 07:04:02 PM PDT 24
Peak memory 198512 kb
Host smart-7197fb39-214d-44cf-94be-25e0a76ac835
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344387241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ran
dom_long_reg_writes_reg_reads.344387241
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2893104946
Short name T176
Test name
Test status
Simulation time 46830665 ps
CPU time 0.96 seconds
Started Aug 09 07:03:55 PM PDT 24
Finished Aug 09 07:03:57 PM PDT 24
Peak memory 196300 kb
Host smart-d14ceec5-1924-4e0d-89e0-4ad569093907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893104946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2893104946
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.26346299
Short name T260
Test name
Test status
Simulation time 45234478 ps
CPU time 1.28 seconds
Started Aug 09 07:03:59 PM PDT 24
Finished Aug 09 07:04:00 PM PDT 24
Peak memory 198392 kb
Host smart-ad6d404c-3f41-482d-a233-522c7c31b559
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26346299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.26346299
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1569890272
Short name T369
Test name
Test status
Simulation time 9385599962 ps
CPU time 98.63 seconds
Started Aug 09 07:03:55 PM PDT 24
Finished Aug 09 07:05:33 PM PDT 24
Peak memory 198664 kb
Host smart-8148abfa-102e-4163-a8c2-bfb7d08784db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569890272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1569890272
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.3986505924
Short name T58
Test name
Test status
Simulation time 28418029163 ps
CPU time 729.41 seconds
Started Aug 09 07:03:55 PM PDT 24
Finished Aug 09 07:16:05 PM PDT 24
Peak memory 198884 kb
Host smart-e0bef4f6-1de1-445e-8b02-747c015592d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3986505924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.3986505924
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.4107321560
Short name T675
Test name
Test status
Simulation time 26320826 ps
CPU time 0.58 seconds
Started Aug 09 07:03:58 PM PDT 24
Finished Aug 09 07:03:59 PM PDT 24
Peak memory 194916 kb
Host smart-b8b27ae9-d514-42e9-8cad-1f0d7fd1f4ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107321560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.4107321560
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.3789382954
Short name T130
Test name
Test status
Simulation time 77102307 ps
CPU time 0.87 seconds
Started Aug 09 07:03:58 PM PDT 24
Finished Aug 09 07:03:59 PM PDT 24
Peak memory 196668 kb
Host smart-50795650-e5e8-48c5-8924-3e88d9659cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789382954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.3789382954
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.2148518743
Short name T298
Test name
Test status
Simulation time 689928049 ps
CPU time 5.64 seconds
Started Aug 09 07:03:56 PM PDT 24
Finished Aug 09 07:04:02 PM PDT 24
Peak memory 197332 kb
Host smart-d1eab640-8b5e-4ba1-a2a2-eef3fd3ff3c5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148518743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.2148518743
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.956060682
Short name T652
Test name
Test status
Simulation time 41533627 ps
CPU time 0.77 seconds
Started Aug 09 07:03:58 PM PDT 24
Finished Aug 09 07:03:59 PM PDT 24
Peak memory 196248 kb
Host smart-53296e36-9824-4fc3-a62c-174ac882a75b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956060682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.956060682
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2041998969
Short name T605
Test name
Test status
Simulation time 97900066 ps
CPU time 1.41 seconds
Started Aug 09 07:04:00 PM PDT 24
Finished Aug 09 07:04:02 PM PDT 24
Peak memory 198612 kb
Host smart-0b252d25-db54-4e26-895b-73945a1a90f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041998969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2041998969
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.2883086510
Short name T329
Test name
Test status
Simulation time 32404798 ps
CPU time 1.3 seconds
Started Aug 09 07:03:56 PM PDT 24
Finished Aug 09 07:03:58 PM PDT 24
Peak memory 196980 kb
Host smart-87a3e891-9417-4ed7-9884-4603ed36de21
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883086510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.2883086510
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.387504012
Short name T343
Test name
Test status
Simulation time 224270119 ps
CPU time 1.45 seconds
Started Aug 09 07:03:59 PM PDT 24
Finished Aug 09 07:04:01 PM PDT 24
Peak memory 197488 kb
Host smart-b70f0d29-5837-43cc-97df-1192f72bc365
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387504012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger.
387504012
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.3681191925
Short name T451
Test name
Test status
Simulation time 79573252 ps
CPU time 1.1 seconds
Started Aug 09 07:03:56 PM PDT 24
Finished Aug 09 07:03:57 PM PDT 24
Peak memory 197300 kb
Host smart-4b2676a8-7c37-4595-acaf-adc06063c1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681191925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3681191925
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3219654665
Short name T198
Test name
Test status
Simulation time 57442436 ps
CPU time 1.06 seconds
Started Aug 09 07:03:55 PM PDT 24
Finished Aug 09 07:03:56 PM PDT 24
Peak memory 197208 kb
Host smart-2f0e1e5c-e4cd-47cf-b5c2-52c0c4bf3b80
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219654665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.3219654665
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.3958717630
Short name T202
Test name
Test status
Simulation time 465917630 ps
CPU time 5.34 seconds
Started Aug 09 07:03:59 PM PDT 24
Finished Aug 09 07:04:04 PM PDT 24
Peak memory 198504 kb
Host smart-a811de01-b0de-43e5-a1ae-4d68e46f6bf3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958717630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.3958717630
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3124147935
Short name T711
Test name
Test status
Simulation time 91634142 ps
CPU time 1.24 seconds
Started Aug 09 07:03:58 PM PDT 24
Finished Aug 09 07:03:59 PM PDT 24
Peak memory 197136 kb
Host smart-ac284394-cc0c-4ec6-ba04-018a6c279aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124147935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3124147935
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1854720517
Short name T150
Test name
Test status
Simulation time 330494447 ps
CPU time 0.89 seconds
Started Aug 09 07:03:55 PM PDT 24
Finished Aug 09 07:03:56 PM PDT 24
Peak memory 196196 kb
Host smart-a7e16626-a2fa-4280-9026-03a2b7b27cbf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854720517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1854720517
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.2961693933
Short name T688
Test name
Test status
Simulation time 18286829569 ps
CPU time 54.59 seconds
Started Aug 09 07:03:59 PM PDT 24
Finished Aug 09 07:04:54 PM PDT 24
Peak memory 198760 kb
Host smart-bb7496fe-5890-4dee-8e98-9fa0d404ff38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961693933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.2961693933
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2610519748
Short name T512
Test name
Test status
Simulation time 13377569 ps
CPU time 0.59 seconds
Started Aug 09 07:03:57 PM PDT 24
Finished Aug 09 07:03:57 PM PDT 24
Peak memory 194504 kb
Host smart-9a76d482-d063-4b9e-9d3c-c57a610180fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610519748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2610519748
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.928532881
Short name T235
Test name
Test status
Simulation time 160469853 ps
CPU time 0.87 seconds
Started Aug 09 07:03:56 PM PDT 24
Finished Aug 09 07:03:57 PM PDT 24
Peak memory 197776 kb
Host smart-84990cd7-9f71-474e-a27a-c8341a285ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928532881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.928532881
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3952393636
Short name T690
Test name
Test status
Simulation time 990412874 ps
CPU time 15.88 seconds
Started Aug 09 07:03:57 PM PDT 24
Finished Aug 09 07:04:13 PM PDT 24
Peak memory 198568 kb
Host smart-3e326749-3f5f-4a1f-b492-f62479de9fe5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952393636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3952393636
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.480108774
Short name T69
Test name
Test status
Simulation time 35729804 ps
CPU time 0.73 seconds
Started Aug 09 07:03:56 PM PDT 24
Finished Aug 09 07:03:57 PM PDT 24
Peak memory 197080 kb
Host smart-4fb2bc0f-265e-4cfb-b565-790ad30a7252
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480108774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.480108774
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.1334333270
Short name T573
Test name
Test status
Simulation time 91665565 ps
CPU time 1.32 seconds
Started Aug 09 07:03:56 PM PDT 24
Finished Aug 09 07:03:57 PM PDT 24
Peak memory 196376 kb
Host smart-fb973ceb-b1da-41ae-a392-6126181649cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334333270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1334333270
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.2393857457
Short name T127
Test name
Test status
Simulation time 57952935 ps
CPU time 1.36 seconds
Started Aug 09 07:03:58 PM PDT 24
Finished Aug 09 07:03:59 PM PDT 24
Peak memory 197152 kb
Host smart-c2cdfb5d-ffd2-4fbe-8cbb-d4d34a32a428
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393857457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.2393857457
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.2215885499
Short name T642
Test name
Test status
Simulation time 88270373 ps
CPU time 1.99 seconds
Started Aug 09 07:03:55 PM PDT 24
Finished Aug 09 07:03:57 PM PDT 24
Peak memory 196744 kb
Host smart-811e4f9e-e2c0-4ead-b6bd-12955e7976b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215885499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.2215885499
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.158150175
Short name T296
Test name
Test status
Simulation time 17360238 ps
CPU time 0.76 seconds
Started Aug 09 07:03:58 PM PDT 24
Finished Aug 09 07:03:59 PM PDT 24
Peak memory 195980 kb
Host smart-32f04f9f-8053-4196-9819-0357562c70c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158150175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.158150175
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3453158479
Short name T660
Test name
Test status
Simulation time 289210421 ps
CPU time 1.12 seconds
Started Aug 09 07:03:56 PM PDT 24
Finished Aug 09 07:03:57 PM PDT 24
Peak memory 197644 kb
Host smart-d2e31037-0cb8-46be-9638-faf561ed1e03
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453158479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3453158479
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1648020200
Short name T8
Test name
Test status
Simulation time 855500597 ps
CPU time 2.77 seconds
Started Aug 09 07:03:58 PM PDT 24
Finished Aug 09 07:04:01 PM PDT 24
Peak memory 198792 kb
Host smart-e78b34a3-699c-40db-9fe7-cc14a77e3d44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648020200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1648020200
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1352651568
Short name T482
Test name
Test status
Simulation time 53238770 ps
CPU time 0.95 seconds
Started Aug 09 07:03:58 PM PDT 24
Finished Aug 09 07:03:59 PM PDT 24
Peak memory 196192 kb
Host smart-b92a0a5f-2d9c-4cbe-a51a-d70fb15b2de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352651568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1352651568
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.3083653068
Short name T560
Test name
Test status
Simulation time 183000860 ps
CPU time 1.35 seconds
Started Aug 09 07:04:00 PM PDT 24
Finished Aug 09 07:04:01 PM PDT 24
Peak memory 198560 kb
Host smart-9137a32c-04ff-47ca-95d1-e0efc1513730
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083653068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.3083653068
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3955291687
Short name T378
Test name
Test status
Simulation time 16380031416 ps
CPU time 112.81 seconds
Started Aug 09 07:03:59 PM PDT 24
Finished Aug 09 07:05:52 PM PDT 24
Peak memory 198660 kb
Host smart-694b3321-1acf-4eee-a126-e1c7efa39759
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955291687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3955291687
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.25313899
Short name T585
Test name
Test status
Simulation time 61653239160 ps
CPU time 1397.67 seconds
Started Aug 09 07:03:59 PM PDT 24
Finished Aug 09 07:27:17 PM PDT 24
Peak memory 198876 kb
Host smart-ef97598e-4480-407b-b3f9-e5810983220f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=25313899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.25313899
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2376467785
Short name T246
Test name
Test status
Simulation time 15400015 ps
CPU time 0.59 seconds
Started Aug 09 07:02:24 PM PDT 24
Finished Aug 09 07:02:24 PM PDT 24
Peak memory 195392 kb
Host smart-73036fb0-5cb0-47ec-8976-c99b72388800
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376467785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2376467785
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1826511509
Short name T363
Test name
Test status
Simulation time 27578380 ps
CPU time 0.75 seconds
Started Aug 09 07:02:23 PM PDT 24
Finished Aug 09 07:02:23 PM PDT 24
Peak memory 195756 kb
Host smart-c9574595-d33b-442b-acdf-d74037d84d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826511509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.1826511509
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.349337817
Short name T134
Test name
Test status
Simulation time 2076192179 ps
CPU time 30.57 seconds
Started Aug 09 07:02:25 PM PDT 24
Finished Aug 09 07:02:56 PM PDT 24
Peak memory 197492 kb
Host smart-0156c360-47e4-4824-b2bd-0d80d2c719a3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349337817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stress
.349337817
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.2627995513
Short name T457
Test name
Test status
Simulation time 225725179 ps
CPU time 0.99 seconds
Started Aug 09 07:02:29 PM PDT 24
Finished Aug 09 07:02:30 PM PDT 24
Peak memory 197524 kb
Host smart-933c7690-a67d-41d1-bc71-435aae00041b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627995513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2627995513
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.1545072959
Short name T669
Test name
Test status
Simulation time 136240115 ps
CPU time 1.07 seconds
Started Aug 09 07:02:23 PM PDT 24
Finished Aug 09 07:02:24 PM PDT 24
Peak memory 196700 kb
Host smart-8e6c5d9a-30ca-4250-86ba-d7141d570252
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545072959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.1545072959
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.4222118498
Short name T472
Test name
Test status
Simulation time 59490580 ps
CPU time 1.35 seconds
Started Aug 09 07:02:27 PM PDT 24
Finished Aug 09 07:02:29 PM PDT 24
Peak memory 198684 kb
Host smart-754a96e4-0d63-450f-a33d-7973ab7974f4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222118498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.4222118498
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.1714977883
Short name T322
Test name
Test status
Simulation time 112665028 ps
CPU time 1.6 seconds
Started Aug 09 07:02:30 PM PDT 24
Finished Aug 09 07:02:31 PM PDT 24
Peak memory 196312 kb
Host smart-a1cc9818-7cf2-4ca7-90df-d60d86114203
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714977883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
1714977883
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.2561733231
Short name T13
Test name
Test status
Simulation time 32721071 ps
CPU time 1.2 seconds
Started Aug 09 07:02:19 PM PDT 24
Finished Aug 09 07:02:21 PM PDT 24
Peak memory 197156 kb
Host smart-6b3e4386-12b9-43a5-a0f9-dd2dd7980d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561733231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.2561733231
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.3927690595
Short name T174
Test name
Test status
Simulation time 35816770 ps
CPU time 0.82 seconds
Started Aug 09 07:02:15 PM PDT 24
Finished Aug 09 07:02:16 PM PDT 24
Peak memory 196028 kb
Host smart-4a3c9b07-1fbb-4b3f-b335-7d753695c04d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927690595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.3927690595
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.3429303426
Short name T133
Test name
Test status
Simulation time 1763211764 ps
CPU time 4.29 seconds
Started Aug 09 07:02:27 PM PDT 24
Finished Aug 09 07:02:32 PM PDT 24
Peak memory 198560 kb
Host smart-405d8c03-52d8-4f0c-a7b8-62fbec553716
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429303426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.3429303426
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.1541433119
Short name T34
Test name
Test status
Simulation time 110204161 ps
CPU time 0.88 seconds
Started Aug 09 07:02:25 PM PDT 24
Finished Aug 09 07:02:26 PM PDT 24
Peak memory 214416 kb
Host smart-706b5018-3f60-4fe6-8575-1223474caf16
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541433119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.1541433119
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.3424263194
Short name T66
Test name
Test status
Simulation time 247757707 ps
CPU time 1.12 seconds
Started Aug 09 07:02:17 PM PDT 24
Finished Aug 09 07:02:18 PM PDT 24
Peak memory 196104 kb
Host smart-af33c541-6a6c-42cd-a39f-3f11de3ac81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424263194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.3424263194
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.4071951302
Short name T519
Test name
Test status
Simulation time 48512777 ps
CPU time 1.35 seconds
Started Aug 09 07:02:15 PM PDT 24
Finished Aug 09 07:02:17 PM PDT 24
Peak memory 197184 kb
Host smart-1ba19a85-2694-470f-a052-d104bdd80ca9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071951302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.4071951302
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.1918302883
Short name T361
Test name
Test status
Simulation time 10761730893 ps
CPU time 73.72 seconds
Started Aug 09 07:02:24 PM PDT 24
Finished Aug 09 07:03:38 PM PDT 24
Peak memory 198728 kb
Host smart-1fd3559b-2117-4e4d-a672-3013a4aa17fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918302883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.1918302883
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.643975131
Short name T60
Test name
Test status
Simulation time 19280049302 ps
CPU time 534.5 seconds
Started Aug 09 07:02:22 PM PDT 24
Finished Aug 09 07:11:17 PM PDT 24
Peak memory 198880 kb
Host smart-077cb281-0562-44b5-a14b-13127f24a146
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=643975131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.643975131
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.4059144805
Short name T499
Test name
Test status
Simulation time 39855749 ps
CPU time 0.59 seconds
Started Aug 09 07:03:58 PM PDT 24
Finished Aug 09 07:03:59 PM PDT 24
Peak memory 195120 kb
Host smart-0dbafbe7-7b97-4ce2-a61a-bc487a673ed1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059144805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.4059144805
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.2156776646
Short name T481
Test name
Test status
Simulation time 14410587 ps
CPU time 0.63 seconds
Started Aug 09 07:03:59 PM PDT 24
Finished Aug 09 07:03:59 PM PDT 24
Peak memory 194496 kb
Host smart-ed6535f9-7654-4c75-9968-700015ba2285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156776646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.2156776646
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.288236541
Short name T626
Test name
Test status
Simulation time 284052465 ps
CPU time 10.07 seconds
Started Aug 09 07:04:00 PM PDT 24
Finished Aug 09 07:04:10 PM PDT 24
Peak memory 196824 kb
Host smart-4ad29ba9-b59c-4338-9414-e0fffc9df914
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288236541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stres
s.288236541
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.2356053874
Short name T646
Test name
Test status
Simulation time 99491294 ps
CPU time 0.92 seconds
Started Aug 09 07:03:58 PM PDT 24
Finished Aug 09 07:03:59 PM PDT 24
Peak memory 197160 kb
Host smart-bc934935-af02-4a7a-a347-d8d78f115f82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356053874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.2356053874
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.245238724
Short name T151
Test name
Test status
Simulation time 85159475 ps
CPU time 0.7 seconds
Started Aug 09 07:03:58 PM PDT 24
Finished Aug 09 07:03:59 PM PDT 24
Peak memory 194836 kb
Host smart-70e0b0f6-2a42-4ea5-aff2-8d3be5f34ec4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245238724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.245238724
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.1807467721
Short name T448
Test name
Test status
Simulation time 85657786 ps
CPU time 3.35 seconds
Started Aug 09 07:03:57 PM PDT 24
Finished Aug 09 07:04:00 PM PDT 24
Peak memory 198684 kb
Host smart-067153c6-28a5-41ff-a249-5a43884539eb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807467721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.1807467721
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.198412014
Short name T639
Test name
Test status
Simulation time 123214697 ps
CPU time 2.91 seconds
Started Aug 09 07:03:56 PM PDT 24
Finished Aug 09 07:04:00 PM PDT 24
Peak memory 197872 kb
Host smart-dfc8187e-d10d-439a-9401-e6e98c090a11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198412014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.
198412014
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.821801720
Short name T299
Test name
Test status
Simulation time 14761297 ps
CPU time 0.71 seconds
Started Aug 09 07:03:58 PM PDT 24
Finished Aug 09 07:03:59 PM PDT 24
Peak memory 195840 kb
Host smart-c627a151-e7cf-4d40-bbd6-733e132a642a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821801720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.821801720
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3276679448
Short name T153
Test name
Test status
Simulation time 32112868 ps
CPU time 0.7 seconds
Started Aug 09 07:03:57 PM PDT 24
Finished Aug 09 07:03:58 PM PDT 24
Peak memory 195496 kb
Host smart-889b63db-ea82-450a-a2b7-38f802caddf8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276679448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.3276679448
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.1492051739
Short name T513
Test name
Test status
Simulation time 849909372 ps
CPU time 5.11 seconds
Started Aug 09 07:03:59 PM PDT 24
Finished Aug 09 07:04:04 PM PDT 24
Peak memory 198388 kb
Host smart-678e69a4-8239-413b-8668-99cb82514eac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492051739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.1492051739
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2917384468
Short name T486
Test name
Test status
Simulation time 232446279 ps
CPU time 1.31 seconds
Started Aug 09 07:03:58 PM PDT 24
Finished Aug 09 07:04:00 PM PDT 24
Peak memory 197492 kb
Host smart-10fda57a-5d08-4b08-8e12-ebe4b9730a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917384468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2917384468
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2938938272
Short name T496
Test name
Test status
Simulation time 212790211 ps
CPU time 1.3 seconds
Started Aug 09 07:03:57 PM PDT 24
Finished Aug 09 07:03:58 PM PDT 24
Peak memory 197440 kb
Host smart-c2c7d657-7331-44bd-af59-e4802ec1634d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938938272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2938938272
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3776163549
Short name T567
Test name
Test status
Simulation time 7848764769 ps
CPU time 98.37 seconds
Started Aug 09 07:03:57 PM PDT 24
Finished Aug 09 07:05:36 PM PDT 24
Peak memory 198652 kb
Host smart-6c1df114-6d92-4ac6-9d28-bf40b357db58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776163549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3776163549
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.1588274202
Short name T28
Test name
Test status
Simulation time 131118594859 ps
CPU time 2778.66 seconds
Started Aug 09 07:03:58 PM PDT 24
Finished Aug 09 07:50:17 PM PDT 24
Peak memory 198832 kb
Host smart-a8f0d887-9c89-462e-93ba-974843d2021c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1588274202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.1588274202
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.2820251874
Short name T506
Test name
Test status
Simulation time 13416368 ps
CPU time 0.6 seconds
Started Aug 09 07:04:04 PM PDT 24
Finished Aug 09 07:04:05 PM PDT 24
Peak memory 194484 kb
Host smart-2a21df33-efc0-4f34-a61c-9b854f4aca41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820251874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2820251874
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2874387333
Short name T553
Test name
Test status
Simulation time 44534402 ps
CPU time 0.99 seconds
Started Aug 09 07:04:07 PM PDT 24
Finished Aug 09 07:04:09 PM PDT 24
Peak memory 196564 kb
Host smart-7cc33b43-2fe2-4daa-a1ce-d1c3390379b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874387333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2874387333
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.2726943902
Short name T195
Test name
Test status
Simulation time 1983266230 ps
CPU time 26.63 seconds
Started Aug 09 07:04:05 PM PDT 24
Finished Aug 09 07:04:32 PM PDT 24
Peak memory 198424 kb
Host smart-da437081-cb01-4669-a52a-11268089d742
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726943902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.2726943902
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1637383684
Short name T587
Test name
Test status
Simulation time 93252073 ps
CPU time 1.03 seconds
Started Aug 09 07:04:06 PM PDT 24
Finished Aug 09 07:04:07 PM PDT 24
Peak memory 198272 kb
Host smart-39127fe2-25e0-4d25-b8da-05e93b13105b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637383684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1637383684
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.34282761
Short name T615
Test name
Test status
Simulation time 47283405 ps
CPU time 0.93 seconds
Started Aug 09 07:04:03 PM PDT 24
Finished Aug 09 07:04:04 PM PDT 24
Peak memory 196204 kb
Host smart-31bdc494-3b7d-4f08-8dd6-af56815bb97c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34282761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.34282761
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1713727122
Short name T643
Test name
Test status
Simulation time 292466763 ps
CPU time 2.75 seconds
Started Aug 09 07:04:04 PM PDT 24
Finished Aug 09 07:04:07 PM PDT 24
Peak memory 197036 kb
Host smart-a80150e2-4e17-419f-8dd9-50852b94282d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713727122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.1713727122
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2154572039
Short name T529
Test name
Test status
Simulation time 1829955945 ps
CPU time 3.25 seconds
Started Aug 09 07:04:07 PM PDT 24
Finished Aug 09 07:04:10 PM PDT 24
Peak memory 198568 kb
Host smart-fbede50a-6acd-4810-845a-098b910a383b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154572039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.2154572039
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.763069049
Short name T115
Test name
Test status
Simulation time 89998047 ps
CPU time 0.99 seconds
Started Aug 09 07:04:07 PM PDT 24
Finished Aug 09 07:04:08 PM PDT 24
Peak memory 196356 kb
Host smart-9ff74990-ecc7-4faa-a38f-440a95437b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763069049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.763069049
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.682675581
Short name T664
Test name
Test status
Simulation time 184571829 ps
CPU time 1.11 seconds
Started Aug 09 07:04:02 PM PDT 24
Finished Aug 09 07:04:03 PM PDT 24
Peak memory 196312 kb
Host smart-7421d3c6-c853-4af8-80b4-2e00aded7b41
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682675581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.682675581
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.3317479113
Short name T708
Test name
Test status
Simulation time 238419417 ps
CPU time 3.99 seconds
Started Aug 09 07:04:02 PM PDT 24
Finished Aug 09 07:04:06 PM PDT 24
Peak memory 198508 kb
Host smart-30b9e0e4-683e-48d8-920a-84e2084fbf03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317479113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.3317479113
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.3995209527
Short name T515
Test name
Test status
Simulation time 249354280 ps
CPU time 1.2 seconds
Started Aug 09 07:03:57 PM PDT 24
Finished Aug 09 07:03:59 PM PDT 24
Peak memory 197376 kb
Host smart-dacd4411-b518-4aba-a074-5812171c42a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995209527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.3995209527
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.2350373418
Short name T417
Test name
Test status
Simulation time 855813037 ps
CPU time 0.87 seconds
Started Aug 09 07:04:02 PM PDT 24
Finished Aug 09 07:04:03 PM PDT 24
Peak memory 195816 kb
Host smart-88b665fb-2718-4d3c-8e9d-ae06571f466e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350373418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.2350373418
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.381828538
Short name T165
Test name
Test status
Simulation time 4484057565 ps
CPU time 54.11 seconds
Started Aug 09 07:04:04 PM PDT 24
Finished Aug 09 07:04:58 PM PDT 24
Peak memory 198740 kb
Host smart-0f458d1e-0236-4799-b8f7-77ddad5e613d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381828538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.g
pio_stress_all.381828538
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.618124413
Short name T109
Test name
Test status
Simulation time 75310163206 ps
CPU time 1236.29 seconds
Started Aug 09 07:04:03 PM PDT 24
Finished Aug 09 07:24:40 PM PDT 24
Peak memory 198856 kb
Host smart-677d7680-4e9a-471f-b0f5-caa9e7b8b25c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=618124413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.618124413
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2955417233
Short name T673
Test name
Test status
Simulation time 23281391 ps
CPU time 0.6 seconds
Started Aug 09 07:04:06 PM PDT 24
Finished Aug 09 07:04:07 PM PDT 24
Peak memory 195140 kb
Host smart-7137e5a0-1cb2-453d-b02c-8ade3d111631
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955417233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2955417233
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.2919290619
Short name T667
Test name
Test status
Simulation time 37617173 ps
CPU time 0.84 seconds
Started Aug 09 07:04:04 PM PDT 24
Finished Aug 09 07:04:05 PM PDT 24
Peak memory 195892 kb
Host smart-d2564f30-63ed-4be9-b1cb-d051a27ea2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919290619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.2919290619
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.1632239090
Short name T703
Test name
Test status
Simulation time 961666911 ps
CPU time 15.62 seconds
Started Aug 09 07:04:03 PM PDT 24
Finished Aug 09 07:04:19 PM PDT 24
Peak memory 197592 kb
Host smart-470c4e04-6488-4e29-baf1-a6ae4b259900
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632239090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.1632239090
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.86354899
Short name T467
Test name
Test status
Simulation time 57750462 ps
CPU time 0.96 seconds
Started Aug 09 07:04:03 PM PDT 24
Finished Aug 09 07:04:05 PM PDT 24
Peak memory 198180 kb
Host smart-bf19fc27-711d-49bf-9016-0faaeed9170b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86354899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.86354899
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.339115517
Short name T332
Test name
Test status
Simulation time 156627327 ps
CPU time 1.18 seconds
Started Aug 09 07:04:02 PM PDT 24
Finished Aug 09 07:04:03 PM PDT 24
Peak memory 196348 kb
Host smart-f253c984-3ede-4a1a-8b78-ffd1430120a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339115517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.339115517
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3952695484
Short name T600
Test name
Test status
Simulation time 200002162 ps
CPU time 2.44 seconds
Started Aug 09 07:04:06 PM PDT 24
Finished Aug 09 07:04:09 PM PDT 24
Peak memory 196896 kb
Host smart-0d6fb359-d48d-43f1-b5ca-be25339387bc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952695484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3952695484
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.2406769939
Short name T476
Test name
Test status
Simulation time 199038684 ps
CPU time 1.43 seconds
Started Aug 09 07:04:02 PM PDT 24
Finished Aug 09 07:04:03 PM PDT 24
Peak memory 196640 kb
Host smart-1fe41706-ee90-422d-98fc-052bf354b6d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406769939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.2406769939
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3952615847
Short name T621
Test name
Test status
Simulation time 27807201 ps
CPU time 0.61 seconds
Started Aug 09 07:04:01 PM PDT 24
Finished Aug 09 07:04:01 PM PDT 24
Peak memory 194736 kb
Host smart-2a260706-cd73-4ff7-873e-b5dfd9a25409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952615847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3952615847
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1515927795
Short name T158
Test name
Test status
Simulation time 192499814 ps
CPU time 0.67 seconds
Started Aug 09 07:04:03 PM PDT 24
Finished Aug 09 07:04:04 PM PDT 24
Peak memory 194896 kb
Host smart-85de64c1-7f63-4a09-a0b0-00cb65110824
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515927795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1515927795
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2891963400
Short name T242
Test name
Test status
Simulation time 74574713 ps
CPU time 3.64 seconds
Started Aug 09 07:04:03 PM PDT 24
Finished Aug 09 07:04:07 PM PDT 24
Peak memory 198588 kb
Host smart-e4a8ba7f-5a29-4423-b378-b0e8bd1bea3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891963400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2891963400
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.1468904672
Short name T463
Test name
Test status
Simulation time 708688893 ps
CPU time 1.46 seconds
Started Aug 09 07:04:05 PM PDT 24
Finished Aug 09 07:04:07 PM PDT 24
Peak memory 197272 kb
Host smart-71cdf16a-4fb3-4050-80b4-5a01df7cb215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468904672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.1468904672
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.487635798
Short name T563
Test name
Test status
Simulation time 57804674 ps
CPU time 1.29 seconds
Started Aug 09 07:04:03 PM PDT 24
Finished Aug 09 07:04:05 PM PDT 24
Peak memory 198600 kb
Host smart-8ac4dcc3-cbef-49ab-b26b-83cce9cd0b18
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487635798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.487635798
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.1138652279
Short name T693
Test name
Test status
Simulation time 17990196155 ps
CPU time 39.69 seconds
Started Aug 09 07:04:05 PM PDT 24
Finished Aug 09 07:04:45 PM PDT 24
Peak memory 198704 kb
Host smart-9fba756d-0fd8-4154-860b-b11bc407bfc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138652279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.1138652279
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.2653548216
Short name T29
Test name
Test status
Simulation time 39056827928 ps
CPU time 536.03 seconds
Started Aug 09 07:04:07 PM PDT 24
Finished Aug 09 07:13:03 PM PDT 24
Peak memory 198896 kb
Host smart-3314506c-52bf-41bc-8849-ae00d2a1bd3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2653548216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.2653548216
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.367380294
Short name T534
Test name
Test status
Simulation time 11959321 ps
CPU time 0.6 seconds
Started Aug 09 07:04:03 PM PDT 24
Finished Aug 09 07:04:04 PM PDT 24
Peak memory 194452 kb
Host smart-e58a3d29-7e9f-466b-8d18-60024a159fba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367380294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.367380294
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.4213931272
Short name T576
Test name
Test status
Simulation time 63291278 ps
CPU time 0.68 seconds
Started Aug 09 07:04:05 PM PDT 24
Finished Aug 09 07:04:06 PM PDT 24
Peak memory 195356 kb
Host smart-4e1063f6-61dd-4e00-90d8-5522abe87a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213931272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.4213931272
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1311260255
Short name T434
Test name
Test status
Simulation time 675809308 ps
CPU time 18.96 seconds
Started Aug 09 07:04:03 PM PDT 24
Finished Aug 09 07:04:23 PM PDT 24
Peak memory 197560 kb
Host smart-043156f4-716e-4ae2-a2d9-af767f859b49
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311260255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1311260255
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.1358771713
Short name T501
Test name
Test status
Simulation time 463038880 ps
CPU time 1.02 seconds
Started Aug 09 07:04:05 PM PDT 24
Finished Aug 09 07:04:06 PM PDT 24
Peak memory 197280 kb
Host smart-3ef9d1ab-7329-4d67-a644-2fbde0dd4afa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358771713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.1358771713
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.1372240014
Short name T538
Test name
Test status
Simulation time 39799547 ps
CPU time 1.17 seconds
Started Aug 09 07:04:04 PM PDT 24
Finished Aug 09 07:04:05 PM PDT 24
Peak memory 196388 kb
Host smart-8dbabb23-95e6-492e-8db2-8dbd1a4fd521
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372240014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.1372240014
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.393202275
Short name T612
Test name
Test status
Simulation time 337732665 ps
CPU time 1.79 seconds
Started Aug 09 07:04:05 PM PDT 24
Finished Aug 09 07:04:07 PM PDT 24
Peak memory 198720 kb
Host smart-f803b9ef-ff19-421d-8d46-e5b590151b37
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393202275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.gpio_intr_with_filter_rand_intr_event.393202275
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.4078683438
Short name T381
Test name
Test status
Simulation time 460534321 ps
CPU time 2.4 seconds
Started Aug 09 07:04:03 PM PDT 24
Finished Aug 09 07:04:06 PM PDT 24
Peak memory 198596 kb
Host smart-cc33f4af-a403-4015-8840-eb7378061922
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078683438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.4078683438
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.3221518480
Short name T447
Test name
Test status
Simulation time 34490194 ps
CPU time 0.84 seconds
Started Aug 09 07:04:05 PM PDT 24
Finished Aug 09 07:04:06 PM PDT 24
Peak memory 196016 kb
Host smart-06d24d4e-aba1-40e0-81ed-a347893dfd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221518480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.3221518480
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3658991142
Short name T535
Test name
Test status
Simulation time 22414592 ps
CPU time 0.73 seconds
Started Aug 09 07:04:07 PM PDT 24
Finished Aug 09 07:04:08 PM PDT 24
Peak memory 194760 kb
Host smart-8bc2866d-d2aa-42bc-9ec4-52aa690477b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658991142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3658991142
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2295923442
Short name T383
Test name
Test status
Simulation time 190814214 ps
CPU time 5.82 seconds
Started Aug 09 07:04:04 PM PDT 24
Finished Aug 09 07:04:10 PM PDT 24
Peak memory 198604 kb
Host smart-55e61394-3714-4691-b41f-cc9041162818
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295923442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2295923442
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.984489881
Short name T391
Test name
Test status
Simulation time 337913997 ps
CPU time 1.19 seconds
Started Aug 09 07:04:05 PM PDT 24
Finished Aug 09 07:04:07 PM PDT 24
Peak memory 196320 kb
Host smart-36fdad7c-82b7-45a8-8c99-f843cf463e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984489881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.984489881
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1985853134
Short name T201
Test name
Test status
Simulation time 29479018 ps
CPU time 0.94 seconds
Started Aug 09 07:04:03 PM PDT 24
Finished Aug 09 07:04:04 PM PDT 24
Peak memory 197760 kb
Host smart-bc68af40-de8c-46dd-9ff9-6a9dc63616d6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985853134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1985853134
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.3661043912
Short name T255
Test name
Test status
Simulation time 14319073651 ps
CPU time 86.97 seconds
Started Aug 09 07:04:04 PM PDT 24
Finished Aug 09 07:05:31 PM PDT 24
Peak memory 198788 kb
Host smart-e86fbe8b-316a-4c4b-b49e-df40b21fb34d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661043912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.3661043912
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2153259859
Short name T306
Test name
Test status
Simulation time 63674395 ps
CPU time 0.57 seconds
Started Aug 09 07:04:05 PM PDT 24
Finished Aug 09 07:04:06 PM PDT 24
Peak memory 194468 kb
Host smart-3d1288c3-a0c8-4f1f-9736-b3fe5e38f85c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153259859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2153259859
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3586841951
Short name T252
Test name
Test status
Simulation time 61742839 ps
CPU time 0.76 seconds
Started Aug 09 07:04:06 PM PDT 24
Finished Aug 09 07:04:07 PM PDT 24
Peak memory 196556 kb
Host smart-3689322e-9bb5-4879-b3e1-de9be974de0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586841951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3586841951
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.3803794325
Short name T588
Test name
Test status
Simulation time 3597373169 ps
CPU time 24.03 seconds
Started Aug 09 07:04:06 PM PDT 24
Finished Aug 09 07:04:30 PM PDT 24
Peak memory 197204 kb
Host smart-c9b1dbf0-e64c-4d76-a82f-152750bb847d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803794325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.3803794325
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.599340405
Short name T398
Test name
Test status
Simulation time 128140863 ps
CPU time 0.91 seconds
Started Aug 09 07:04:07 PM PDT 24
Finished Aug 09 07:04:08 PM PDT 24
Peak memory 196516 kb
Host smart-e29c5ad8-620c-4e85-8551-8dc25b6938e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599340405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.599340405
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.3118784679
Short name T377
Test name
Test status
Simulation time 73407242 ps
CPU time 0.76 seconds
Started Aug 09 07:04:05 PM PDT 24
Finished Aug 09 07:04:06 PM PDT 24
Peak memory 196092 kb
Host smart-b5e4ee69-d8e7-41f9-a2c1-6318c51cfe83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118784679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.3118784679
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.320137871
Short name T583
Test name
Test status
Simulation time 27128166 ps
CPU time 0.94 seconds
Started Aug 09 07:04:03 PM PDT 24
Finished Aug 09 07:04:04 PM PDT 24
Peak memory 196704 kb
Host smart-502b11e3-73eb-4dfb-9544-f003a64d2cc5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320137871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.gpio_intr_with_filter_rand_intr_event.320137871
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.4060939313
Short name T589
Test name
Test status
Simulation time 1424387337 ps
CPU time 2.78 seconds
Started Aug 09 07:04:04 PM PDT 24
Finished Aug 09 07:04:07 PM PDT 24
Peak memory 196412 kb
Host smart-2bf9b0d7-ec14-40bb-a6dc-7dc1cd385db8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060939313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.4060939313
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3062031404
Short name T304
Test name
Test status
Simulation time 65333770 ps
CPU time 1.16 seconds
Started Aug 09 07:04:07 PM PDT 24
Finished Aug 09 07:04:08 PM PDT 24
Peak memory 197512 kb
Host smart-5c331ad3-060c-4496-9e85-0fae068841f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062031404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3062031404
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.986810590
Short name T582
Test name
Test status
Simulation time 33870773 ps
CPU time 0.85 seconds
Started Aug 09 07:04:03 PM PDT 24
Finished Aug 09 07:04:05 PM PDT 24
Peak memory 197112 kb
Host smart-99d3b0a0-fc3e-4217-9a1e-e3fb20722afc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986810590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.986810590
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.919835845
Short name T602
Test name
Test status
Simulation time 187549412 ps
CPU time 2.83 seconds
Started Aug 09 07:04:04 PM PDT 24
Finished Aug 09 07:04:07 PM PDT 24
Peak memory 198576 kb
Host smart-c4ec3cef-f7b8-4930-ae27-575fbd422214
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919835845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ran
dom_long_reg_writes_reg_reads.919835845
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.2776607284
Short name T700
Test name
Test status
Simulation time 200324960 ps
CPU time 1.07 seconds
Started Aug 09 07:04:01 PM PDT 24
Finished Aug 09 07:04:02 PM PDT 24
Peak memory 196104 kb
Host smart-115fc8fc-6a5f-46d6-bf98-b21158d8f261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776607284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.2776607284
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.972753369
Short name T283
Test name
Test status
Simulation time 67436415 ps
CPU time 1.16 seconds
Started Aug 09 07:04:07 PM PDT 24
Finished Aug 09 07:04:08 PM PDT 24
Peak memory 196104 kb
Host smart-c4c2f587-3d8c-4c9f-a1d5-a500b6c2fc90
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972753369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.972753369
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.4056416042
Short name T430
Test name
Test status
Simulation time 4627059954 ps
CPU time 110.29 seconds
Started Aug 09 07:04:05 PM PDT 24
Finished Aug 09 07:05:56 PM PDT 24
Peak memory 198684 kb
Host smart-b754a3f4-ea90-4236-8245-85fb9c4ff65c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056416042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.4056416042
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.771982805
Short name T312
Test name
Test status
Simulation time 17144385 ps
CPU time 0.6 seconds
Started Aug 09 07:04:15 PM PDT 24
Finished Aug 09 07:04:16 PM PDT 24
Peak memory 195164 kb
Host smart-a5e83171-37d4-420b-b73e-5236ca1fdb30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771982805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.771982805
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.1783407301
Short name T614
Test name
Test status
Simulation time 47472348 ps
CPU time 0.72 seconds
Started Aug 09 07:04:15 PM PDT 24
Finished Aug 09 07:04:16 PM PDT 24
Peak memory 196436 kb
Host smart-d026396e-0087-4ac5-854e-b7b16fd0600a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783407301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.1783407301
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.3732236418
Short name T204
Test name
Test status
Simulation time 869824352 ps
CPU time 16.35 seconds
Started Aug 09 07:04:10 PM PDT 24
Finished Aug 09 07:04:27 PM PDT 24
Peak memory 196796 kb
Host smart-88606902-e55d-487e-9aba-87d185c4c0aa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732236418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.3732236418
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.116478805
Short name T338
Test name
Test status
Simulation time 80753840 ps
CPU time 0.77 seconds
Started Aug 09 07:04:14 PM PDT 24
Finished Aug 09 07:04:15 PM PDT 24
Peak memory 196268 kb
Host smart-675916f7-b9e1-4900-afba-0b21d9693fbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116478805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.116478805
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.4228179528
Short name T144
Test name
Test status
Simulation time 82949239 ps
CPU time 0.84 seconds
Started Aug 09 07:04:08 PM PDT 24
Finished Aug 09 07:04:09 PM PDT 24
Peak memory 196168 kb
Host smart-7519a2b9-2987-45f3-b354-0a5c65d1357f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228179528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.4228179528
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1627755325
Short name T112
Test name
Test status
Simulation time 190882938 ps
CPU time 1.86 seconds
Started Aug 09 07:04:11 PM PDT 24
Finished Aug 09 07:04:13 PM PDT 24
Peak memory 196844 kb
Host smart-14cb2165-8123-409b-a348-31152e1902d9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627755325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1627755325
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.852173645
Short name T460
Test name
Test status
Simulation time 54983941 ps
CPU time 1.36 seconds
Started Aug 09 07:04:10 PM PDT 24
Finished Aug 09 07:04:12 PM PDT 24
Peak memory 197328 kb
Host smart-a1df0cc7-88e6-4bc1-8129-8087eccf1fa3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852173645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger.
852173645
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.4219573684
Short name T648
Test name
Test status
Simulation time 94008956 ps
CPU time 1.03 seconds
Started Aug 09 07:04:11 PM PDT 24
Finished Aug 09 07:04:12 PM PDT 24
Peak memory 196376 kb
Host smart-a0c87381-d895-46e1-9ce4-38f7ca262570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219573684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.4219573684
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.334368191
Short name T407
Test name
Test status
Simulation time 37712375 ps
CPU time 1.23 seconds
Started Aug 09 07:04:11 PM PDT 24
Finished Aug 09 07:04:12 PM PDT 24
Peak memory 197564 kb
Host smart-ef893b48-2e36-4ce0-a76d-48aa66d34608
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334368191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup
_pulldown.334368191
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2303979743
Short name T654
Test name
Test status
Simulation time 330637950 ps
CPU time 5.48 seconds
Started Aug 09 07:04:11 PM PDT 24
Finished Aug 09 07:04:17 PM PDT 24
Peak memory 198548 kb
Host smart-d35b9594-8def-416f-b1ef-11b5566468dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303979743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2303979743
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.3419494274
Short name T545
Test name
Test status
Simulation time 30781819 ps
CPU time 0.96 seconds
Started Aug 09 07:04:14 PM PDT 24
Finished Aug 09 07:04:15 PM PDT 24
Peak memory 196304 kb
Host smart-8b6fab42-f92d-4b02-b7ec-22c2b0333363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419494274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.3419494274
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.2995847693
Short name T493
Test name
Test status
Simulation time 91243756 ps
CPU time 1.36 seconds
Started Aug 09 07:04:10 PM PDT 24
Finished Aug 09 07:04:12 PM PDT 24
Peak memory 197376 kb
Host smart-49c9681f-1f35-4ab5-b505-e1dda57c7aaa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995847693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.2995847693
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.741636249
Short name T641
Test name
Test status
Simulation time 63519408756 ps
CPU time 170.58 seconds
Started Aug 09 07:04:11 PM PDT 24
Finished Aug 09 07:07:02 PM PDT 24
Peak memory 198768 kb
Host smart-9f8dded0-6690-4dac-a0ad-886f2432903a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741636249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.g
pio_stress_all.741636249
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.1865970798
Short name T63
Test name
Test status
Simulation time 326530550489 ps
CPU time 1548.76 seconds
Started Aug 09 07:04:12 PM PDT 24
Finished Aug 09 07:30:01 PM PDT 24
Peak memory 198904 kb
Host smart-71a425c0-9cb0-4d91-9692-193989ba7077
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1865970798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.1865970798
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.477425685
Short name T522
Test name
Test status
Simulation time 42879016 ps
CPU time 0.59 seconds
Started Aug 09 07:04:10 PM PDT 24
Finished Aug 09 07:04:11 PM PDT 24
Peak memory 195408 kb
Host smart-563b59bf-6787-4a8f-9005-99a1cd10ac37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477425685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.477425685
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.2093528839
Short name T189
Test name
Test status
Simulation time 19265558 ps
CPU time 0.7 seconds
Started Aug 09 07:04:11 PM PDT 24
Finished Aug 09 07:04:12 PM PDT 24
Peak memory 194772 kb
Host smart-694c3219-cd58-4eac-a687-e2d6433cb5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093528839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.2093528839
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.557375978
Short name T676
Test name
Test status
Simulation time 612670154 ps
CPU time 21.45 seconds
Started Aug 09 07:04:10 PM PDT 24
Finished Aug 09 07:04:31 PM PDT 24
Peak memory 197508 kb
Host smart-b9f4da4b-7ff8-454d-8b48-76199e3f6689
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557375978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stres
s.557375978
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.1696270957
Short name T581
Test name
Test status
Simulation time 66808064 ps
CPU time 0.63 seconds
Started Aug 09 07:04:15 PM PDT 24
Finished Aug 09 07:04:15 PM PDT 24
Peak memory 194936 kb
Host smart-dfadf347-d22d-433b-9193-376dd1955d60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696270957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.1696270957
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2870981346
Short name T495
Test name
Test status
Simulation time 464018070 ps
CPU time 1.02 seconds
Started Aug 09 07:04:10 PM PDT 24
Finished Aug 09 07:04:11 PM PDT 24
Peak memory 196304 kb
Host smart-631078ab-69ef-4ea2-a918-00f70b53d5b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870981346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2870981346
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.2846092750
Short name T149
Test name
Test status
Simulation time 159522697 ps
CPU time 3.86 seconds
Started Aug 09 07:04:15 PM PDT 24
Finished Aug 09 07:04:19 PM PDT 24
Peak memory 198552 kb
Host smart-5a3126df-68bd-4dcd-a959-cca02c270152
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846092750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.2846092750
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3693282458
Short name T551
Test name
Test status
Simulation time 66938493 ps
CPU time 1.42 seconds
Started Aug 09 07:04:15 PM PDT 24
Finished Aug 09 07:04:17 PM PDT 24
Peak memory 196604 kb
Host smart-018bab81-a3ae-46d1-90f5-26206fe5d8da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693282458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3693282458
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.2306763345
Short name T450
Test name
Test status
Simulation time 31833000 ps
CPU time 1.1 seconds
Started Aug 09 07:04:11 PM PDT 24
Finished Aug 09 07:04:12 PM PDT 24
Peak memory 198552 kb
Host smart-0c3d8d8a-b821-4e71-926a-1cb248cfaee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306763345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.2306763345
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.1980415277
Short name T653
Test name
Test status
Simulation time 76976540 ps
CPU time 0.88 seconds
Started Aug 09 07:04:12 PM PDT 24
Finished Aug 09 07:04:13 PM PDT 24
Peak memory 197188 kb
Host smart-f8c8f351-062f-4589-b45a-0c07e9a7ab68
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980415277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.1980415277
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.4218365349
Short name T336
Test name
Test status
Simulation time 1128119536 ps
CPU time 4.57 seconds
Started Aug 09 07:04:12 PM PDT 24
Finished Aug 09 07:04:17 PM PDT 24
Peak memory 198452 kb
Host smart-60a0d067-e82c-47cd-87bc-112cdeb414b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218365349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.4218365349
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.840018655
Short name T211
Test name
Test status
Simulation time 43856441 ps
CPU time 0.92 seconds
Started Aug 09 07:04:10 PM PDT 24
Finished Aug 09 07:04:11 PM PDT 24
Peak memory 196920 kb
Host smart-257fa14a-d800-4946-bb26-bd607aedeb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840018655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.840018655
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.500414147
Short name T627
Test name
Test status
Simulation time 85308910 ps
CPU time 1.34 seconds
Started Aug 09 07:04:15 PM PDT 24
Finished Aug 09 07:04:16 PM PDT 24
Peak memory 197292 kb
Host smart-f171d196-ad7a-4dfd-a141-016315b09ba1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500414147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.500414147
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.192375971
Short name T487
Test name
Test status
Simulation time 13192822573 ps
CPU time 96.68 seconds
Started Aug 09 07:04:11 PM PDT 24
Finished Aug 09 07:05:48 PM PDT 24
Peak memory 198724 kb
Host smart-f0b6e2da-0b5d-487f-af5b-7d41dc89b950
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192375971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.g
pio_stress_all.192375971
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.948539085
Short name T637
Test name
Test status
Simulation time 23065596110 ps
CPU time 578.2 seconds
Started Aug 09 07:04:14 PM PDT 24
Finished Aug 09 07:13:52 PM PDT 24
Peak memory 198852 kb
Host smart-042de4b2-6957-4615-8e1e-197bf4740849
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=948539085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.948539085
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.3114649424
Short name T399
Test name
Test status
Simulation time 42842192 ps
CPU time 0.57 seconds
Started Aug 09 07:04:17 PM PDT 24
Finished Aug 09 07:04:17 PM PDT 24
Peak memory 193980 kb
Host smart-483aa9b9-95fe-4772-b776-df41b5d54b0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114649424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.3114649424
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3413912881
Short name T125
Test name
Test status
Simulation time 28903176 ps
CPU time 0.78 seconds
Started Aug 09 07:04:11 PM PDT 24
Finished Aug 09 07:04:12 PM PDT 24
Peak memory 196416 kb
Host smart-6bb5b5aa-6b0e-4a12-81bf-a4d84286f958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413912881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3413912881
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.1980060972
Short name T229
Test name
Test status
Simulation time 1595263367 ps
CPU time 13.41 seconds
Started Aug 09 07:04:15 PM PDT 24
Finished Aug 09 07:04:29 PM PDT 24
Peak memory 196092 kb
Host smart-64a0b021-6ea7-45fa-8d83-939289ff0aff
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980060972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.1980060972
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.27312947
Short name T603
Test name
Test status
Simulation time 121619812 ps
CPU time 0.74 seconds
Started Aug 09 07:04:24 PM PDT 24
Finished Aug 09 07:04:25 PM PDT 24
Peak memory 195136 kb
Host smart-c91d77fb-f75b-4473-8bd4-8fab20799678
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27312947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.27312947
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.978905409
Short name T677
Test name
Test status
Simulation time 105499532 ps
CPU time 0.92 seconds
Started Aug 09 07:04:14 PM PDT 24
Finished Aug 09 07:04:15 PM PDT 24
Peak memory 197284 kb
Host smart-0f5a0874-e3b3-4e0b-b772-df5e34ffc57e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978905409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.978905409
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.4122377695
Short name T706
Test name
Test status
Simulation time 255863157 ps
CPU time 1.89 seconds
Started Aug 09 07:04:11 PM PDT 24
Finished Aug 09 07:04:13 PM PDT 24
Peak memory 198628 kb
Host smart-c03ca23c-aad6-4e08-a1a9-3c88a28895bd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122377695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.4122377695
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1787343296
Short name T550
Test name
Test status
Simulation time 958494295 ps
CPU time 2.87 seconds
Started Aug 09 07:04:12 PM PDT 24
Finished Aug 09 07:04:15 PM PDT 24
Peak memory 198596 kb
Host smart-d1108170-7aab-4e9e-8419-80dc38651a5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787343296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1787343296
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.450579608
Short name T672
Test name
Test status
Simulation time 59160040 ps
CPU time 1.43 seconds
Started Aug 09 07:04:10 PM PDT 24
Finished Aug 09 07:04:12 PM PDT 24
Peak memory 197580 kb
Host smart-7f1bc5fd-711c-4d1d-ae2e-2e599c0fa769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450579608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.450579608
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1734532272
Short name T278
Test name
Test status
Simulation time 25959023 ps
CPU time 0.73 seconds
Started Aug 09 07:04:11 PM PDT 24
Finished Aug 09 07:04:12 PM PDT 24
Peak memory 195988 kb
Host smart-3bf92308-87c2-4ca2-9633-6b4bf923c6ee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734532272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1734532272
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.1120332545
Short name T261
Test name
Test status
Simulation time 139146903 ps
CPU time 2.61 seconds
Started Aug 09 07:04:17 PM PDT 24
Finished Aug 09 07:04:20 PM PDT 24
Peak memory 198564 kb
Host smart-05b6278d-0afd-4b25-a602-bc37734ed0a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120332545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.1120332545
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.4226829594
Short name T464
Test name
Test status
Simulation time 37681421 ps
CPU time 0.92 seconds
Started Aug 09 07:04:12 PM PDT 24
Finished Aug 09 07:04:13 PM PDT 24
Peak memory 196952 kb
Host smart-e654b649-60cb-4193-9def-9986ddce9476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226829594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.4226829594
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2268725294
Short name T172
Test name
Test status
Simulation time 113991131 ps
CPU time 1.04 seconds
Started Aug 09 07:04:14 PM PDT 24
Finished Aug 09 07:04:15 PM PDT 24
Peak memory 196364 kb
Host smart-bd592a8a-db5c-4739-a350-fa7007da4bda
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268725294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.2268725294
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1403786694
Short name T168
Test name
Test status
Simulation time 11810024618 ps
CPU time 165.76 seconds
Started Aug 09 07:04:19 PM PDT 24
Finished Aug 09 07:07:05 PM PDT 24
Peak memory 198720 kb
Host smart-a86aca8a-a46d-4756-91ef-4bf0694dff37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403786694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1403786694
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.3096032047
Short name T453
Test name
Test status
Simulation time 17047050 ps
CPU time 0.64 seconds
Started Aug 09 07:04:18 PM PDT 24
Finished Aug 09 07:04:19 PM PDT 24
Peak memory 195432 kb
Host smart-2bb75b7e-ec9f-498d-ac19-a40a14598b53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096032047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.3096032047
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.3514231086
Short name T18
Test name
Test status
Simulation time 41538238 ps
CPU time 0.88 seconds
Started Aug 09 07:04:17 PM PDT 24
Finished Aug 09 07:04:18 PM PDT 24
Peak memory 196212 kb
Host smart-9a9dd20d-d469-41f9-9072-415748730fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514231086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.3514231086
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.509162379
Short name T404
Test name
Test status
Simulation time 422546657 ps
CPU time 4.05 seconds
Started Aug 09 07:04:18 PM PDT 24
Finished Aug 09 07:04:22 PM PDT 24
Peak memory 196144 kb
Host smart-9861d344-56c7-4458-a59e-e41115993aba
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509162379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stres
s.509162379
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2776137651
Short name T468
Test name
Test status
Simulation time 127198710 ps
CPU time 1.16 seconds
Started Aug 09 07:04:18 PM PDT 24
Finished Aug 09 07:04:19 PM PDT 24
Peak memory 197164 kb
Host smart-cc803547-ca25-48fa-afd2-a30033c85ec4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776137651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2776137651
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.2681489766
Short name T456
Test name
Test status
Simulation time 319579845 ps
CPU time 0.91 seconds
Started Aug 09 07:04:19 PM PDT 24
Finished Aug 09 07:04:20 PM PDT 24
Peak memory 197228 kb
Host smart-28d5bc3c-9159-4d8e-9b10-f55656690256
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681489766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.2681489766
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.4061487315
Short name T339
Test name
Test status
Simulation time 288315942 ps
CPU time 2.9 seconds
Started Aug 09 07:04:20 PM PDT 24
Finished Aug 09 07:04:23 PM PDT 24
Peak memory 196864 kb
Host smart-f352d79a-6a7e-4080-9a7f-a142449d3009
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061487315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.4061487315
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.981914952
Short name T366
Test name
Test status
Simulation time 494690274 ps
CPU time 2.43 seconds
Started Aug 09 07:04:17 PM PDT 24
Finished Aug 09 07:04:20 PM PDT 24
Peak memory 196428 kb
Host smart-e062e266-c67a-4c02-861f-416fa351b119
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981914952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger.
981914952
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.3450890228
Short name T591
Test name
Test status
Simulation time 33110320 ps
CPU time 0.91 seconds
Started Aug 09 07:04:17 PM PDT 24
Finished Aug 09 07:04:18 PM PDT 24
Peak memory 196624 kb
Host smart-82978aec-7a25-4232-b726-df29cd5ced71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450890228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.3450890228
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.4159566632
Short name T709
Test name
Test status
Simulation time 57561270 ps
CPU time 1.12 seconds
Started Aug 09 07:04:20 PM PDT 24
Finished Aug 09 07:04:21 PM PDT 24
Peak memory 197336 kb
Host smart-54a559ab-09a1-4fd1-ab54-653380ef0f5b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159566632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.4159566632
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.231408352
Short name T207
Test name
Test status
Simulation time 70810800 ps
CPU time 3.08 seconds
Started Aug 09 07:04:19 PM PDT 24
Finished Aug 09 07:04:22 PM PDT 24
Peak memory 198504 kb
Host smart-5ff4952a-80b5-43d7-a462-b1c42e0dcf84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231408352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ran
dom_long_reg_writes_reg_reads.231408352
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.311409886
Short name T250
Test name
Test status
Simulation time 222234026 ps
CPU time 1.08 seconds
Started Aug 09 07:04:21 PM PDT 24
Finished Aug 09 07:04:22 PM PDT 24
Peak memory 195808 kb
Host smart-71558121-13bd-4caf-a055-55f4826ebe8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311409886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.311409886
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2544052298
Short name T161
Test name
Test status
Simulation time 67753372 ps
CPU time 1.09 seconds
Started Aug 09 07:04:21 PM PDT 24
Finished Aug 09 07:04:22 PM PDT 24
Peak memory 195456 kb
Host smart-b344a3ea-d30c-44e0-999b-e6461efa7d8d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544052298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2544052298
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.3585396658
Short name T140
Test name
Test status
Simulation time 5838688219 ps
CPU time 38.07 seconds
Started Aug 09 07:04:17 PM PDT 24
Finished Aug 09 07:04:56 PM PDT 24
Peak memory 198712 kb
Host smart-6c74b789-b31f-427e-9f0d-7cc1f6179a4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585396658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.3585396658
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.1480437246
Short name T686
Test name
Test status
Simulation time 46048866028 ps
CPU time 903.56 seconds
Started Aug 09 07:04:17 PM PDT 24
Finished Aug 09 07:19:21 PM PDT 24
Peak memory 198832 kb
Host smart-c05346b9-d934-4ea8-93fb-d2f3916f83e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1480437246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.1480437246
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.2853330517
Short name T269
Test name
Test status
Simulation time 48267402 ps
CPU time 0.58 seconds
Started Aug 09 07:04:24 PM PDT 24
Finished Aug 09 07:04:25 PM PDT 24
Peak memory 194556 kb
Host smart-672c6597-ebb7-470e-b746-a4a2874b2ff5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853330517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.2853330517
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.2506891016
Short name T658
Test name
Test status
Simulation time 23044813 ps
CPU time 0.8 seconds
Started Aug 09 07:04:18 PM PDT 24
Finished Aug 09 07:04:20 PM PDT 24
Peak memory 195848 kb
Host smart-e40dc9ec-bb09-4fac-bdde-13a239aec09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506891016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.2506891016
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.35026867
Short name T577
Test name
Test status
Simulation time 381153459 ps
CPU time 4.88 seconds
Started Aug 09 07:04:17 PM PDT 24
Finished Aug 09 07:04:22 PM PDT 24
Peak memory 196816 kb
Host smart-16bced32-2daf-4eb7-8583-b1d495016e70
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35026867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stress
.35026867
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2042297600
Short name T362
Test name
Test status
Simulation time 157035399 ps
CPU time 0.89 seconds
Started Aug 09 07:04:24 PM PDT 24
Finished Aug 09 07:04:25 PM PDT 24
Peak memory 196604 kb
Host smart-5925bc95-29f4-4258-a115-b702632ef0a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042297600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2042297600
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.672868706
Short name T705
Test name
Test status
Simulation time 25434641 ps
CPU time 0.78 seconds
Started Aug 09 07:04:18 PM PDT 24
Finished Aug 09 07:04:19 PM PDT 24
Peak memory 196056 kb
Host smart-1f739259-5c02-4580-919e-51bba1aa2b68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672868706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.672868706
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.714049369
Short name T364
Test name
Test status
Simulation time 25440915 ps
CPU time 1.05 seconds
Started Aug 09 07:04:18 PM PDT 24
Finished Aug 09 07:04:19 PM PDT 24
Peak memory 197244 kb
Host smart-09067ca0-dff7-46e9-b8a1-a77bbd867a01
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714049369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.gpio_intr_with_filter_rand_intr_event.714049369
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3424085512
Short name T714
Test name
Test status
Simulation time 62092573 ps
CPU time 2.01 seconds
Started Aug 09 07:04:17 PM PDT 24
Finished Aug 09 07:04:19 PM PDT 24
Peak memory 198664 kb
Host smart-782ebac5-6927-4344-9c28-ce4edaff8dcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424085512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3424085512
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1595437281
Short name T51
Test name
Test status
Simulation time 155137624 ps
CPU time 0.97 seconds
Started Aug 09 07:04:19 PM PDT 24
Finished Aug 09 07:04:20 PM PDT 24
Peak memory 196616 kb
Host smart-49b37ae5-5a2e-4f50-98bf-1306b0c3053a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595437281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1595437281
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1979178483
Short name T546
Test name
Test status
Simulation time 241032176 ps
CPU time 1.45 seconds
Started Aug 09 07:04:19 PM PDT 24
Finished Aug 09 07:04:20 PM PDT 24
Peak memory 198584 kb
Host smart-2d6a6e73-07b3-440a-8536-af98d13250ee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979178483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.1979178483
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1845755323
Short name T490
Test name
Test status
Simulation time 5299562434 ps
CPU time 5.21 seconds
Started Aug 09 07:04:24 PM PDT 24
Finished Aug 09 07:04:29 PM PDT 24
Peak memory 198552 kb
Host smart-e6fb167e-2aaa-41b0-ad72-8a1c94f1297c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845755323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.1845755323
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.4102184942
Short name T212
Test name
Test status
Simulation time 65823505 ps
CPU time 1.16 seconds
Started Aug 09 07:04:20 PM PDT 24
Finished Aug 09 07:04:21 PM PDT 24
Peak memory 196240 kb
Host smart-35187ccb-04d3-49ce-a2d6-0fd96c064ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102184942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.4102184942
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.1029242826
Short name T57
Test name
Test status
Simulation time 128595450 ps
CPU time 1.17 seconds
Started Aug 09 07:04:19 PM PDT 24
Finished Aug 09 07:04:20 PM PDT 24
Peak memory 196980 kb
Host smart-676c3ccb-7a7d-4ec6-8ec5-a7b16a8c4f2e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029242826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.1029242826
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.956167831
Short name T52
Test name
Test status
Simulation time 3382103116 ps
CPU time 51.26 seconds
Started Aug 09 07:04:16 PM PDT 24
Finished Aug 09 07:05:07 PM PDT 24
Peak memory 198688 kb
Host smart-3bc3bf4e-bd74-4c33-8726-ba667f41bb18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956167831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.g
pio_stress_all.956167831
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.2892729226
Short name T39
Test name
Test status
Simulation time 34552801 ps
CPU time 0.58 seconds
Started Aug 09 07:02:26 PM PDT 24
Finished Aug 09 07:02:27 PM PDT 24
Peak memory 194652 kb
Host smart-1965f69f-82c8-4f09-9766-35fac6efd0f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892729226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.2892729226
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2264580012
Short name T696
Test name
Test status
Simulation time 30189676 ps
CPU time 0.65 seconds
Started Aug 09 07:02:25 PM PDT 24
Finished Aug 09 07:02:26 PM PDT 24
Peak memory 194600 kb
Host smart-8130ea46-c69f-4f4c-940a-2e35c1e90207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264580012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2264580012
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.4039627197
Short name T262
Test name
Test status
Simulation time 4863827431 ps
CPU time 17.99 seconds
Started Aug 09 07:02:29 PM PDT 24
Finished Aug 09 07:02:47 PM PDT 24
Peak memory 197640 kb
Host smart-8557b72f-3a32-42a3-98c2-f60a88da709d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039627197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.4039627197
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.575259019
Short name T340
Test name
Test status
Simulation time 45254002 ps
CPU time 0.74 seconds
Started Aug 09 07:02:23 PM PDT 24
Finished Aug 09 07:02:23 PM PDT 24
Peak memory 197060 kb
Host smart-a30e5284-b1ac-475c-97bc-2323206d0524
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575259019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.575259019
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.13689780
Short name T162
Test name
Test status
Simulation time 47599906 ps
CPU time 0.85 seconds
Started Aug 09 07:02:25 PM PDT 24
Finished Aug 09 07:02:26 PM PDT 24
Peak memory 196136 kb
Host smart-89ea47b7-9b10-4503-82f2-00249eb1bb48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13689780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.13689780
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2036680930
Short name T544
Test name
Test status
Simulation time 26818496 ps
CPU time 1.22 seconds
Started Aug 09 07:02:25 PM PDT 24
Finished Aug 09 07:02:26 PM PDT 24
Peak memory 197296 kb
Host smart-fadfa842-57ff-478d-bbe7-8a217746c37e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036680930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2036680930
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.219528464
Short name T452
Test name
Test status
Simulation time 110635150 ps
CPU time 2.2 seconds
Started Aug 09 07:02:26 PM PDT 24
Finished Aug 09 07:02:29 PM PDT 24
Peak memory 197744 kb
Host smart-7f31b307-e267-4bd5-bbc7-841547da2490
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219528464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.219528464
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.329456906
Short name T282
Test name
Test status
Simulation time 60352919 ps
CPU time 0.65 seconds
Started Aug 09 07:02:27 PM PDT 24
Finished Aug 09 07:02:28 PM PDT 24
Peak memory 194888 kb
Host smart-f9867d66-b523-4305-beb5-a9aa21c3b1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329456906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.329456906
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3580279865
Short name T423
Test name
Test status
Simulation time 66462376 ps
CPU time 0.72 seconds
Started Aug 09 07:02:26 PM PDT 24
Finished Aug 09 07:02:27 PM PDT 24
Peak memory 195520 kb
Host smart-ee66297d-f456-4ebb-bf4f-af9bee2dcaa4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580279865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3580279865
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2366849114
Short name T352
Test name
Test status
Simulation time 31575845 ps
CPU time 1.47 seconds
Started Aug 09 07:02:22 PM PDT 24
Finished Aug 09 07:02:24 PM PDT 24
Peak memory 198512 kb
Host smart-56364667-e7b8-4059-bfea-93eeae5f1f31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366849114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.2366849114
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1092233430
Short name T113
Test name
Test status
Simulation time 56464943 ps
CPU time 1.1 seconds
Started Aug 09 07:02:22 PM PDT 24
Finished Aug 09 07:02:24 PM PDT 24
Peak memory 196420 kb
Host smart-b75c7afe-3a49-42f8-a6e2-fe3b0e6bb39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092233430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1092233430
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3381300714
Short name T74
Test name
Test status
Simulation time 106549382 ps
CPU time 1.45 seconds
Started Aug 09 07:02:25 PM PDT 24
Finished Aug 09 07:02:26 PM PDT 24
Peak memory 197356 kb
Host smart-8c7d4dc8-3853-41c7-9246-049570988da8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381300714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3381300714
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1451143960
Short name T634
Test name
Test status
Simulation time 20889037324 ps
CPU time 203.78 seconds
Started Aug 09 07:02:25 PM PDT 24
Finished Aug 09 07:05:49 PM PDT 24
Peak memory 198752 kb
Host smart-6d8fc60b-a0a3-43c2-9ea4-9d4332ef4c3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451143960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1451143960
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.3674609224
Short name T61
Test name
Test status
Simulation time 184124547406 ps
CPU time 902.76 seconds
Started Aug 09 07:02:22 PM PDT 24
Finished Aug 09 07:17:25 PM PDT 24
Peak memory 198900 kb
Host smart-ce611ef4-4cd6-431b-aa59-0873bd965e55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3674609224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.3674609224
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.1423759317
Short name T243
Test name
Test status
Simulation time 22902314 ps
CPU time 0.57 seconds
Started Aug 09 07:02:25 PM PDT 24
Finished Aug 09 07:02:25 PM PDT 24
Peak memory 194420 kb
Host smart-1d72aa35-e880-4cdc-b1c0-dccc02889f44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423759317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.1423759317
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.509191756
Short name T533
Test name
Test status
Simulation time 94743268 ps
CPU time 0.94 seconds
Started Aug 09 07:02:22 PM PDT 24
Finished Aug 09 07:02:23 PM PDT 24
Peak memory 197288 kb
Host smart-ea68188b-4525-4fe9-8b6d-18ffa68dce78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509191756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.509191756
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.295676578
Short name T334
Test name
Test status
Simulation time 628213271 ps
CPU time 22.33 seconds
Started Aug 09 07:02:24 PM PDT 24
Finished Aug 09 07:02:46 PM PDT 24
Peak memory 198604 kb
Host smart-430d8028-6698-4f19-a926-96e8aac71c97
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295676578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress
.295676578
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.944043414
Short name T241
Test name
Test status
Simulation time 185674898 ps
CPU time 0.99 seconds
Started Aug 09 07:02:24 PM PDT 24
Finished Aug 09 07:02:25 PM PDT 24
Peak memory 198480 kb
Host smart-6f72b16f-e1de-4e00-9d76-e9d7b626047f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944043414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.944043414
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.244276311
Short name T327
Test name
Test status
Simulation time 190487455 ps
CPU time 0.97 seconds
Started Aug 09 07:02:27 PM PDT 24
Finished Aug 09 07:02:28 PM PDT 24
Peak memory 197152 kb
Host smart-d06ea27e-cba2-4adf-ae52-9580e876abe9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244276311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.244276311
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.268378709
Short name T145
Test name
Test status
Simulation time 99856914 ps
CPU time 2.2 seconds
Started Aug 09 07:02:24 PM PDT 24
Finished Aug 09 07:02:26 PM PDT 24
Peak memory 198764 kb
Host smart-b529ef4a-f49a-4cf9-be53-e5c66cf95005
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268378709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.gpio_intr_with_filter_rand_intr_event.268378709
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1081503881
Short name T226
Test name
Test status
Simulation time 40900328 ps
CPU time 1.44 seconds
Started Aug 09 07:02:30 PM PDT 24
Finished Aug 09 07:02:31 PM PDT 24
Peak memory 196304 kb
Host smart-9936fcf5-f78b-401a-91f3-5c1f980a95d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081503881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1081503881
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.4144549669
Short name T584
Test name
Test status
Simulation time 229052056 ps
CPU time 1.02 seconds
Started Aug 09 07:02:26 PM PDT 24
Finished Aug 09 07:02:27 PM PDT 24
Peak memory 197324 kb
Host smart-b9ec7082-5203-4611-887b-ddceb25864c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144549669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.4144549669
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.3500402032
Short name T478
Test name
Test status
Simulation time 18519543 ps
CPU time 0.72 seconds
Started Aug 09 07:02:25 PM PDT 24
Finished Aug 09 07:02:26 PM PDT 24
Peak memory 195908 kb
Host smart-b5a018ee-3386-4173-9315-9114cb97515f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500402032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.3500402032
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.913661183
Short name T146
Test name
Test status
Simulation time 158595136 ps
CPU time 3.54 seconds
Started Aug 09 07:02:26 PM PDT 24
Finished Aug 09 07:02:30 PM PDT 24
Peak memory 198504 kb
Host smart-20186648-a5c8-4f2a-93e6-48056d8c33ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913661183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.913661183
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.687696977
Short name T638
Test name
Test status
Simulation time 251553204 ps
CPU time 0.97 seconds
Started Aug 09 07:02:26 PM PDT 24
Finished Aug 09 07:02:27 PM PDT 24
Peak memory 196944 kb
Host smart-51298ecb-7917-41c9-9156-f2630a0075fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687696977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.687696977
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.3761468532
Short name T325
Test name
Test status
Simulation time 55767813 ps
CPU time 1.12 seconds
Started Aug 09 07:02:22 PM PDT 24
Finished Aug 09 07:02:24 PM PDT 24
Peak memory 196924 kb
Host smart-f08f4974-612f-4862-9d10-02320908ed18
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761468532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.3761468532
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.145894706
Short name T425
Test name
Test status
Simulation time 4228497458 ps
CPU time 88.65 seconds
Started Aug 09 07:02:25 PM PDT 24
Finished Aug 09 07:03:54 PM PDT 24
Peak memory 192704 kb
Host smart-36d375e6-a78b-43ea-b270-e001282b9a5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145894706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gp
io_stress_all.145894706
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.1162072513
Short name T454
Test name
Test status
Simulation time 12301951 ps
CPU time 0.59 seconds
Started Aug 09 07:02:30 PM PDT 24
Finished Aug 09 07:02:30 PM PDT 24
Peak memory 194416 kb
Host smart-632c0598-3a0d-4d43-adac-e5b8e9ea190c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162072513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.1162072513
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3168290835
Short name T390
Test name
Test status
Simulation time 62638598 ps
CPU time 0.81 seconds
Started Aug 09 07:02:22 PM PDT 24
Finished Aug 09 07:02:23 PM PDT 24
Peak memory 195984 kb
Host smart-1b056e81-4aa7-42e0-b6b4-59933e632a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168290835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3168290835
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1012251498
Short name T694
Test name
Test status
Simulation time 1963892089 ps
CPU time 24.25 seconds
Started Aug 09 07:02:23 PM PDT 24
Finished Aug 09 07:02:47 PM PDT 24
Peak memory 197688 kb
Host smart-81f1af38-a665-498a-a04e-f9ee3892cb63
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012251498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1012251498
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.3707457199
Short name T595
Test name
Test status
Simulation time 45824036 ps
CPU time 0.65 seconds
Started Aug 09 07:02:26 PM PDT 24
Finished Aug 09 07:02:27 PM PDT 24
Peak memory 194932 kb
Host smart-552039c0-fdfe-42a1-9f3e-1a40f7fd3121
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707457199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.3707457199
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.4163648483
Short name T420
Test name
Test status
Simulation time 36216874 ps
CPU time 1.08 seconds
Started Aug 09 07:02:27 PM PDT 24
Finished Aug 09 07:02:28 PM PDT 24
Peak memory 197212 kb
Host smart-4f775228-c45c-46f8-981b-810df52f3293
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163648483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.4163648483
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3453866323
Short name T662
Test name
Test status
Simulation time 672736547 ps
CPU time 2.36 seconds
Started Aug 09 07:02:27 PM PDT 24
Finished Aug 09 07:02:29 PM PDT 24
Peak memory 198592 kb
Host smart-beb118a7-200c-4c53-8fb6-398b838ccb02
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453866323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3453866323
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.2576203655
Short name T651
Test name
Test status
Simulation time 153062815 ps
CPU time 3.09 seconds
Started Aug 09 07:02:22 PM PDT 24
Finished Aug 09 07:02:25 PM PDT 24
Peak memory 197672 kb
Host smart-e9287ce6-2ead-49fb-aaba-13b90be19c1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576203655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
2576203655
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.1002925043
Short name T303
Test name
Test status
Simulation time 318921605 ps
CPU time 1.06 seconds
Started Aug 09 07:02:25 PM PDT 24
Finished Aug 09 07:02:26 PM PDT 24
Peak memory 196520 kb
Host smart-280a7e99-1a8d-4b84-857d-d48fd78c7cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002925043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.1002925043
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.2379984980
Short name T518
Test name
Test status
Simulation time 132123213 ps
CPU time 0.93 seconds
Started Aug 09 07:02:24 PM PDT 24
Finished Aug 09 07:02:25 PM PDT 24
Peak memory 196580 kb
Host smart-3b264c76-5e8c-4fcb-a64e-8441d7818da6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379984980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.2379984980
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.231489937
Short name T3
Test name
Test status
Simulation time 902128565 ps
CPU time 4.87 seconds
Started Aug 09 07:02:25 PM PDT 24
Finished Aug 09 07:02:30 PM PDT 24
Peak memory 198536 kb
Host smart-a08fc6be-dcf8-43d9-be27-7fc37653ce22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231489937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand
om_long_reg_writes_reg_reads.231489937
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1229581928
Short name T465
Test name
Test status
Simulation time 58685447 ps
CPU time 1.07 seconds
Started Aug 09 07:02:23 PM PDT 24
Finished Aug 09 07:02:24 PM PDT 24
Peak memory 196908 kb
Host smart-d04b8e33-99b5-41b6-b52d-a1bb2593da68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229581928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1229581928
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2230808548
Short name T502
Test name
Test status
Simulation time 78280789 ps
CPU time 1.1 seconds
Started Aug 09 07:02:25 PM PDT 24
Finished Aug 09 07:02:26 PM PDT 24
Peak memory 196784 kb
Host smart-4e3de449-fc2f-4fc8-a407-a6d5bba57fb8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230808548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2230808548
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.911741848
Short name T713
Test name
Test status
Simulation time 9019027897 ps
CPU time 33.92 seconds
Started Aug 09 07:02:27 PM PDT 24
Finished Aug 09 07:03:01 PM PDT 24
Peak memory 198740 kb
Host smart-629de52c-9df5-460a-b631-994824bbb564
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911741848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.911741848
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.3572178616
Short name T77
Test name
Test status
Simulation time 36267372 ps
CPU time 0.57 seconds
Started Aug 09 07:02:35 PM PDT 24
Finished Aug 09 07:02:35 PM PDT 24
Peak memory 194444 kb
Host smart-ddef138b-f012-4528-95b4-5fa1d01b1ca0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572178616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.3572178616
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.783875576
Short name T611
Test name
Test status
Simulation time 28280028 ps
CPU time 0.67 seconds
Started Aug 09 07:02:31 PM PDT 24
Finished Aug 09 07:02:31 PM PDT 24
Peak memory 194564 kb
Host smart-95cac58c-8858-4ced-b2fa-663837de4cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783875576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.783875576
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.4108078167
Short name T395
Test name
Test status
Simulation time 535361035 ps
CPU time 16.19 seconds
Started Aug 09 07:02:30 PM PDT 24
Finished Aug 09 07:02:47 PM PDT 24
Peak memory 197500 kb
Host smart-49710212-7db3-4a64-9211-b8998c01e182
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108078167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.4108078167
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1898014787
Short name T263
Test name
Test status
Simulation time 301969170 ps
CPU time 0.91 seconds
Started Aug 09 07:02:32 PM PDT 24
Finished Aug 09 07:02:33 PM PDT 24
Peak memory 197320 kb
Host smart-1b81393c-43da-4f37-85e0-a703fdccc3fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898014787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1898014787
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.3260975478
Short name T689
Test name
Test status
Simulation time 186729343 ps
CPU time 1.37 seconds
Started Aug 09 07:02:34 PM PDT 24
Finished Aug 09 07:02:36 PM PDT 24
Peak memory 197644 kb
Host smart-9c4c23ab-7577-42fd-bd6f-83cb23574d54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260975478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.3260975478
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1656625049
Short name T492
Test name
Test status
Simulation time 411828823 ps
CPU time 3.17 seconds
Started Aug 09 07:02:32 PM PDT 24
Finished Aug 09 07:02:35 PM PDT 24
Peak memory 198640 kb
Host smart-27545f15-5266-424d-90f5-eb515dcca881
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656625049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1656625049
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2997446024
Short name T663
Test name
Test status
Simulation time 202862615 ps
CPU time 1.42 seconds
Started Aug 09 07:02:31 PM PDT 24
Finished Aug 09 07:02:33 PM PDT 24
Peak memory 196604 kb
Host smart-ce349bd7-ce38-4479-b306-5f47ea6fded0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997446024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2997446024
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.1891111117
Short name T192
Test name
Test status
Simulation time 22299766 ps
CPU time 0.8 seconds
Started Aug 09 07:02:35 PM PDT 24
Finished Aug 09 07:02:36 PM PDT 24
Peak memory 197120 kb
Host smart-9790769a-3e4b-403a-a63b-415b606efbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891111117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.1891111117
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1921883711
Short name T616
Test name
Test status
Simulation time 113769457 ps
CPU time 1.33 seconds
Started Aug 09 07:02:35 PM PDT 24
Finished Aug 09 07:02:36 PM PDT 24
Peak memory 198620 kb
Host smart-b9842a42-5903-4996-adb9-30b09ca7bdb5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921883711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.1921883711
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1098184580
Short name T171
Test name
Test status
Simulation time 575029404 ps
CPU time 5.9 seconds
Started Aug 09 07:02:32 PM PDT 24
Finished Aug 09 07:02:38 PM PDT 24
Peak memory 198568 kb
Host smart-3f68ffb3-6942-4f9c-b740-feee728af5e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098184580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1098184580
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.2477195925
Short name T692
Test name
Test status
Simulation time 196303844 ps
CPU time 1.17 seconds
Started Aug 09 07:02:29 PM PDT 24
Finished Aug 09 07:02:30 PM PDT 24
Peak memory 196400 kb
Host smart-cd0e43ac-e50d-42c4-81ee-29ab4af99a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477195925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.2477195925
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.234204253
Short name T470
Test name
Test status
Simulation time 226017076 ps
CPU time 1.31 seconds
Started Aug 09 07:02:32 PM PDT 24
Finished Aug 09 07:02:33 PM PDT 24
Peak memory 197400 kb
Host smart-ed2be403-b3ae-4307-a9ef-00dae08981b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234204253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.234204253
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.1557457021
Short name T205
Test name
Test status
Simulation time 22941005471 ps
CPU time 138.83 seconds
Started Aug 09 07:02:30 PM PDT 24
Finished Aug 09 07:04:49 PM PDT 24
Peak memory 198768 kb
Host smart-871cf5a4-ee75-4011-8e14-7577891c413c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557457021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.1557457021
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.108940286
Short name T313
Test name
Test status
Simulation time 60400527246 ps
CPU time 1999.56 seconds
Started Aug 09 07:02:33 PM PDT 24
Finished Aug 09 07:35:53 PM PDT 24
Peak memory 198848 kb
Host smart-2d5c4741-0928-4a86-8b95-16164c62f735
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=108940286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.108940286
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.2737760481
Short name T341
Test name
Test status
Simulation time 162390723 ps
CPU time 0.57 seconds
Started Aug 09 07:02:31 PM PDT 24
Finished Aug 09 07:02:32 PM PDT 24
Peak memory 194676 kb
Host smart-599730b1-a186-4eba-ab8f-1794b022f613
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737760481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2737760481
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2058087175
Short name T121
Test name
Test status
Simulation time 22665459 ps
CPU time 0.59 seconds
Started Aug 09 07:02:30 PM PDT 24
Finished Aug 09 07:02:30 PM PDT 24
Peak memory 194400 kb
Host smart-1e3d5aeb-34df-4342-b2fb-fc4b0efe02f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058087175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2058087175
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.798815096
Short name T401
Test name
Test status
Simulation time 463127737 ps
CPU time 22.46 seconds
Started Aug 09 07:02:33 PM PDT 24
Finished Aug 09 07:02:56 PM PDT 24
Peak memory 198568 kb
Host smart-046450f9-d6e9-4955-9adf-d139328dc52b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798815096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stress
.798815096
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.363062717
Short name T668
Test name
Test status
Simulation time 172504864 ps
CPU time 1.01 seconds
Started Aug 09 07:02:34 PM PDT 24
Finished Aug 09 07:02:35 PM PDT 24
Peak memory 197052 kb
Host smart-d8612593-0f1d-49d2-8136-cbd76d27253b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363062717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.363062717
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.158903066
Short name T438
Test name
Test status
Simulation time 112859743 ps
CPU time 0.91 seconds
Started Aug 09 07:02:35 PM PDT 24
Finished Aug 09 07:02:36 PM PDT 24
Peak memory 196612 kb
Host smart-aaa9b7db-cb6e-4ae2-bfd1-5ba59874fb3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158903066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.158903066
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1478485735
Short name T136
Test name
Test status
Simulation time 321063238 ps
CPU time 3.27 seconds
Started Aug 09 07:02:33 PM PDT 24
Finished Aug 09 07:02:36 PM PDT 24
Peak memory 198720 kb
Host smart-6f5bee79-438c-4ec9-91ab-c732b816174d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478485735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1478485735
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.2450080981
Short name T11
Test name
Test status
Simulation time 61258666 ps
CPU time 0.95 seconds
Started Aug 09 07:02:33 PM PDT 24
Finished Aug 09 07:02:34 PM PDT 24
Peak memory 196032 kb
Host smart-035c065e-f5f5-4a8e-8994-9eca971ab16b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450080981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
2450080981
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.1830593375
Short name T607
Test name
Test status
Simulation time 107318543 ps
CPU time 1.1 seconds
Started Aug 09 07:02:31 PM PDT 24
Finished Aug 09 07:02:33 PM PDT 24
Peak memory 196616 kb
Host smart-13b9e4f4-6743-4cf1-bd7e-9e0f3e968cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830593375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1830593375
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2785985722
Short name T116
Test name
Test status
Simulation time 185378232 ps
CPU time 1.13 seconds
Started Aug 09 07:02:32 PM PDT 24
Finished Aug 09 07:02:34 PM PDT 24
Peak memory 196568 kb
Host smart-3f66b1dc-b388-4cf3-9cb5-71dc2e6e3a39
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785985722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.2785985722
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.249261371
Short name T389
Test name
Test status
Simulation time 112737327 ps
CPU time 5.19 seconds
Started Aug 09 07:02:31 PM PDT 24
Finished Aug 09 07:02:36 PM PDT 24
Peak memory 198596 kb
Host smart-26025eb7-b0c1-4b06-8cea-4a9c5e049114
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249261371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.249261371
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.3608234398
Short name T219
Test name
Test status
Simulation time 95815524 ps
CPU time 0.73 seconds
Started Aug 09 07:02:33 PM PDT 24
Finished Aug 09 07:02:34 PM PDT 24
Peak memory 195692 kb
Host smart-cc69bf2a-6116-4866-885f-9888ab277344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608234398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.3608234398
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1647570706
Short name T586
Test name
Test status
Simulation time 90554625 ps
CPU time 0.97 seconds
Started Aug 09 07:02:31 PM PDT 24
Finished Aug 09 07:02:32 PM PDT 24
Peak memory 196108 kb
Host smart-601b26c3-f3b7-4459-82f5-b3040bbf479c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647570706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1647570706
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.1979518510
Short name T397
Test name
Test status
Simulation time 41340018531 ps
CPU time 274.21 seconds
Started Aug 09 07:02:32 PM PDT 24
Finished Aug 09 07:07:06 PM PDT 24
Peak memory 198724 kb
Host smart-9529355e-6bff-4539-b6ea-09f5bc4c08b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979518510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.1979518510
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.4112658223
Short name T932
Test name
Test status
Simulation time 294136893 ps
CPU time 1.49 seconds
Started Aug 09 07:01:49 PM PDT 24
Finished Aug 09 07:01:51 PM PDT 24
Peak memory 196752 kb
Host smart-4122bd94-b2e7-4f8a-b362-c4ba661f87d1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4112658223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.4112658223
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.672529010
Short name T865
Test name
Test status
Simulation time 190939493 ps
CPU time 0.99 seconds
Started Aug 09 07:01:51 PM PDT 24
Finished Aug 09 07:01:52 PM PDT 24
Peak memory 196468 kb
Host smart-f582e6cb-ca43-44ae-9040-2f48a270ea14
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672529010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.672529010
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.102292581
Short name T881
Test name
Test status
Simulation time 101644080 ps
CPU time 1.65 seconds
Started Aug 09 07:01:46 PM PDT 24
Finished Aug 09 07:01:48 PM PDT 24
Peak memory 197952 kb
Host smart-b19208da-e7d1-4534-8771-3b9fda34aa83
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=102292581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.102292581
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3802615451
Short name T921
Test name
Test status
Simulation time 82811393 ps
CPU time 1.32 seconds
Started Aug 09 07:01:50 PM PDT 24
Finished Aug 09 07:01:51 PM PDT 24
Peak memory 196628 kb
Host smart-114252d6-8b78-44a4-92dc-e53a5a407b3c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802615451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3802615451
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.656965760
Short name T890
Test name
Test status
Simulation time 120089345 ps
CPU time 0.92 seconds
Started Aug 09 07:01:49 PM PDT 24
Finished Aug 09 07:01:50 PM PDT 24
Peak memory 194672 kb
Host smart-71eb4dc6-ce97-4bdb-86aa-80dfc628f393
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=656965760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.656965760
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3212487261
Short name T855
Test name
Test status
Simulation time 42830554 ps
CPU time 1.19 seconds
Started Aug 09 07:01:48 PM PDT 24
Finished Aug 09 07:01:49 PM PDT 24
Peak memory 196528 kb
Host smart-4e3c6784-650b-4166-8cb3-56babe9f4c47
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212487261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3212487261
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3023083582
Short name T924
Test name
Test status
Simulation time 66242082 ps
CPU time 1.29 seconds
Started Aug 09 07:01:46 PM PDT 24
Finished Aug 09 07:01:47 PM PDT 24
Peak memory 198040 kb
Host smart-89c3a776-6bd9-40f2-9319-9747669fd320
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3023083582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.3023083582
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.518995990
Short name T913
Test name
Test status
Simulation time 247469678 ps
CPU time 1.32 seconds
Started Aug 09 07:01:51 PM PDT 24
Finished Aug 09 07:01:52 PM PDT 24
Peak memory 196452 kb
Host smart-9058e10c-682e-4522-bcde-91ae739f3728
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518995990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.518995990
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1934348655
Short name T893
Test name
Test status
Simulation time 43427916 ps
CPU time 1.1 seconds
Started Aug 09 07:01:48 PM PDT 24
Finished Aug 09 07:01:50 PM PDT 24
Peak memory 196396 kb
Host smart-454c5f3d-80f4-4dd1-b03f-b3d0c955fc34
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1934348655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.1934348655
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1496124278
Short name T885
Test name
Test status
Simulation time 346873498 ps
CPU time 0.74 seconds
Started Aug 09 07:01:49 PM PDT 24
Finished Aug 09 07:01:50 PM PDT 24
Peak memory 195400 kb
Host smart-657948fd-47e9-4cb5-bcd5-0505efc5ed3e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496124278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1496124278
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1024452859
Short name T920
Test name
Test status
Simulation time 72923133 ps
CPU time 1.2 seconds
Started Aug 09 07:01:49 PM PDT 24
Finished Aug 09 07:01:51 PM PDT 24
Peak memory 196724 kb
Host smart-77547764-3186-425a-b753-b02f642ff25d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1024452859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.1024452859
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4225926392
Short name T848
Test name
Test status
Simulation time 150887287 ps
CPU time 1.31 seconds
Started Aug 09 07:01:51 PM PDT 24
Finished Aug 09 07:01:52 PM PDT 24
Peak memory 197932 kb
Host smart-d0c18341-053f-4536-9bbb-c178687974af
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225926392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4225926392
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.596262423
Short name T871
Test name
Test status
Simulation time 189523114 ps
CPU time 1.07 seconds
Started Aug 09 07:01:49 PM PDT 24
Finished Aug 09 07:01:51 PM PDT 24
Peak memory 196176 kb
Host smart-250c8653-4589-4fb0-af37-76f54232e4a4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=596262423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.596262423
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.401821227
Short name T875
Test name
Test status
Simulation time 143318094 ps
CPU time 1.29 seconds
Started Aug 09 07:01:51 PM PDT 24
Finished Aug 09 07:01:53 PM PDT 24
Peak memory 194752 kb
Host smart-2fd9faf5-d67c-429f-bef6-80f7ccdc03ed
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401821227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.401821227
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.806822527
Short name T853
Test name
Test status
Simulation time 78895214 ps
CPU time 0.83 seconds
Started Aug 09 07:01:50 PM PDT 24
Finished Aug 09 07:01:51 PM PDT 24
Peak memory 196544 kb
Host smart-595cc0d9-3bb1-45a9-9a19-a541f6989753
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=806822527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.806822527
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.216082472
Short name T942
Test name
Test status
Simulation time 262112468 ps
CPU time 1.26 seconds
Started Aug 09 07:01:47 PM PDT 24
Finished Aug 09 07:01:48 PM PDT 24
Peak memory 196632 kb
Host smart-7f285100-f092-46a7-b97e-1e8ee7871e26
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216082472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.216082472
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1735521097
Short name T937
Test name
Test status
Simulation time 191982352 ps
CPU time 1.38 seconds
Started Aug 09 07:01:48 PM PDT 24
Finished Aug 09 07:01:50 PM PDT 24
Peak memory 196896 kb
Host smart-358111f7-0dc6-48db-92a2-1ed939e95e0d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1735521097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.1735521097
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2855255502
Short name T897
Test name
Test status
Simulation time 255278785 ps
CPU time 1.04 seconds
Started Aug 09 07:01:49 PM PDT 24
Finished Aug 09 07:01:50 PM PDT 24
Peak memory 195912 kb
Host smart-ebf9c917-7038-49de-879b-d69ecda8f954
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855255502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2855255502
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2470196517
Short name T862
Test name
Test status
Simulation time 217249275 ps
CPU time 1.18 seconds
Started Aug 09 07:01:49 PM PDT 24
Finished Aug 09 07:01:50 PM PDT 24
Peak memory 197832 kb
Host smart-2446543d-c30c-4993-888c-65a5561ca96d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2470196517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.2470196517
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1502507590
Short name T872
Test name
Test status
Simulation time 35865886 ps
CPU time 0.89 seconds
Started Aug 09 07:01:46 PM PDT 24
Finished Aug 09 07:01:47 PM PDT 24
Peak memory 195996 kb
Host smart-c3e824e8-85d9-49c6-88d2-799173e61265
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502507590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1502507590
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3038311367
Short name T879
Test name
Test status
Simulation time 64904111 ps
CPU time 1.09 seconds
Started Aug 09 07:01:46 PM PDT 24
Finished Aug 09 07:01:47 PM PDT 24
Peak memory 195904 kb
Host smart-59c9b6d0-8910-4d6e-a39c-b295c11f9fec
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3038311367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.3038311367
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4070931944
Short name T935
Test name
Test status
Simulation time 363028795 ps
CPU time 1.48 seconds
Started Aug 09 07:01:50 PM PDT 24
Finished Aug 09 07:01:51 PM PDT 24
Peak memory 196712 kb
Host smart-d7a5ec47-2d51-44b1-bf01-e370b989ada1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070931944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4070931944
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.4283859744
Short name T899
Test name
Test status
Simulation time 291674330 ps
CPU time 1.3 seconds
Started Aug 09 07:01:47 PM PDT 24
Finished Aug 09 07:01:48 PM PDT 24
Peak memory 197224 kb
Host smart-658e1872-7c0c-416d-824b-c7a0cd3370c8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4283859744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.4283859744
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2746946106
Short name T852
Test name
Test status
Simulation time 26141004 ps
CPU time 0.84 seconds
Started Aug 09 07:01:49 PM PDT 24
Finished Aug 09 07:01:49 PM PDT 24
Peak memory 195484 kb
Host smart-975c997c-cc1a-4363-af88-2d2e38109f38
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746946106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2746946106
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1096816338
Short name T891
Test name
Test status
Simulation time 79459032 ps
CPU time 0.96 seconds
Started Aug 09 07:01:49 PM PDT 24
Finished Aug 09 07:01:50 PM PDT 24
Peak memory 195316 kb
Host smart-4e1d353a-857e-4b0a-8764-856e3606a69d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1096816338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.1096816338
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.575154015
Short name T947
Test name
Test status
Simulation time 129767953 ps
CPU time 0.94 seconds
Started Aug 09 07:01:49 PM PDT 24
Finished Aug 09 07:01:50 PM PDT 24
Peak memory 191536 kb
Host smart-f4d05a9f-924e-46cd-8ec5-ce6c7b571409
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575154015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.575154015
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2904989193
Short name T851
Test name
Test status
Simulation time 57639315 ps
CPU time 1.07 seconds
Started Aug 09 07:01:47 PM PDT 24
Finished Aug 09 07:01:48 PM PDT 24
Peak memory 196432 kb
Host smart-28e601ad-97a3-47ed-b085-9c9832ac3875
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2904989193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.2904989193
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2418860892
Short name T867
Test name
Test status
Simulation time 46378341 ps
CPU time 1.2 seconds
Started Aug 09 07:01:47 PM PDT 24
Finished Aug 09 07:01:48 PM PDT 24
Peak memory 196840 kb
Host smart-54672f15-900c-412c-94d8-28095d95f514
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418860892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2418860892
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2685079058
Short name T876
Test name
Test status
Simulation time 39653227 ps
CPU time 1.19 seconds
Started Aug 09 07:01:47 PM PDT 24
Finished Aug 09 07:01:49 PM PDT 24
Peak memory 197596 kb
Host smart-5786be49-845a-4763-996b-c9d5b52090b2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2685079058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.2685079058
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3501471024
Short name T918
Test name
Test status
Simulation time 161826978 ps
CPU time 1.38 seconds
Started Aug 09 07:01:48 PM PDT 24
Finished Aug 09 07:01:49 PM PDT 24
Peak memory 195688 kb
Host smart-bcc2bf46-a44d-4486-9805-8953073f6b2a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501471024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3501471024
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1345033306
Short name T916
Test name
Test status
Simulation time 23290862 ps
CPU time 0.8 seconds
Started Aug 09 07:01:47 PM PDT 24
Finished Aug 09 07:01:48 PM PDT 24
Peak memory 195324 kb
Host smart-1352b094-7a10-4c85-9d5e-a434df5e2732
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1345033306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.1345033306
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3644663337
Short name T898
Test name
Test status
Simulation time 132585139 ps
CPU time 1.14 seconds
Started Aug 09 07:01:46 PM PDT 24
Finished Aug 09 07:01:48 PM PDT 24
Peak memory 198044 kb
Host smart-62442f53-2699-4109-bcfd-ed7f920acf3d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644663337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3644663337
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2587759758
Short name T896
Test name
Test status
Simulation time 69449264 ps
CPU time 1.11 seconds
Started Aug 09 07:01:52 PM PDT 24
Finished Aug 09 07:01:53 PM PDT 24
Peak memory 196696 kb
Host smart-35cba763-e356-4cf0-ac97-60ea82979b44
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2587759758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.2587759758
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2412122509
Short name T903
Test name
Test status
Simulation time 70815320 ps
CPU time 1.33 seconds
Started Aug 09 07:01:48 PM PDT 24
Finished Aug 09 07:01:49 PM PDT 24
Peak memory 196412 kb
Host smart-54f3c8a7-0c59-4f8b-a9bf-891a12d20276
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412122509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2412122509
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3386807398
Short name T864
Test name
Test status
Simulation time 95037255 ps
CPU time 0.81 seconds
Started Aug 09 07:01:47 PM PDT 24
Finished Aug 09 07:01:48 PM PDT 24
Peak memory 196076 kb
Host smart-6ce0b5f3-ee2c-48d2-b6e3-293a2220c22f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3386807398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.3386807398
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1913285931
Short name T946
Test name
Test status
Simulation time 115804808 ps
CPU time 0.91 seconds
Started Aug 09 07:01:56 PM PDT 24
Finished Aug 09 07:01:58 PM PDT 24
Peak memory 195468 kb
Host smart-9447822d-dd69-4880-bf1a-c1b2e7a9d6ec
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913285931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1913285931
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2906204478
Short name T941
Test name
Test status
Simulation time 116503926 ps
CPU time 1.1 seconds
Started Aug 09 07:01:57 PM PDT 24
Finished Aug 09 07:01:58 PM PDT 24
Peak memory 196752 kb
Host smart-3644ad5c-d3fb-440b-b35e-673c6f141f1c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2906204478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.2906204478
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3462733450
Short name T892
Test name
Test status
Simulation time 55625522 ps
CPU time 1.12 seconds
Started Aug 09 07:01:57 PM PDT 24
Finished Aug 09 07:01:58 PM PDT 24
Peak memory 197972 kb
Host smart-130c2a7d-49c1-44b6-b8c9-cbc01ce3161f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462733450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3462733450
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1588963193
Short name T895
Test name
Test status
Simulation time 87093732 ps
CPU time 1.42 seconds
Started Aug 09 07:01:56 PM PDT 24
Finished Aug 09 07:01:58 PM PDT 24
Peak memory 196604 kb
Host smart-0081017c-3b41-42f3-ae87-f5086b3f5e67
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1588963193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1588963193
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1393540293
Short name T922
Test name
Test status
Simulation time 62507663 ps
CPU time 1.21 seconds
Started Aug 09 07:01:57 PM PDT 24
Finished Aug 09 07:01:58 PM PDT 24
Peak memory 196804 kb
Host smart-6b4be5e8-fac9-4725-a13e-aff92ec8d6c2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393540293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1393540293
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2858836012
Short name T894
Test name
Test status
Simulation time 1456064380 ps
CPU time 1.34 seconds
Started Aug 09 07:01:56 PM PDT 24
Finished Aug 09 07:01:58 PM PDT 24
Peak memory 196812 kb
Host smart-8e06b843-37b4-4efa-9eda-20798ce1f806
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2858836012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.2858836012
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2904530898
Short name T900
Test name
Test status
Simulation time 52285683 ps
CPU time 0.89 seconds
Started Aug 09 07:01:57 PM PDT 24
Finished Aug 09 07:01:58 PM PDT 24
Peak memory 196516 kb
Host smart-33be0c9f-4c57-45da-912c-76e62fabb995
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904530898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2904530898
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2429050065
Short name T907
Test name
Test status
Simulation time 142421471 ps
CPU time 0.96 seconds
Started Aug 09 07:01:57 PM PDT 24
Finished Aug 09 07:01:58 PM PDT 24
Peak memory 196484 kb
Host smart-26dc2ab4-10ef-4535-a6c6-e92f71cba9ec
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2429050065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.2429050065
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.179664922
Short name T938
Test name
Test status
Simulation time 75217923 ps
CPU time 0.79 seconds
Started Aug 09 07:01:56 PM PDT 24
Finished Aug 09 07:01:57 PM PDT 24
Peak memory 195472 kb
Host smart-a4043be4-ede4-4f79-9610-8578d28a5c57
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179664922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.179664922
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2192169991
Short name T940
Test name
Test status
Simulation time 331888337 ps
CPU time 0.74 seconds
Started Aug 09 07:01:57 PM PDT 24
Finished Aug 09 07:01:58 PM PDT 24
Peak memory 195380 kb
Host smart-1b849e8e-b283-4822-8206-c9cc7514687f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2192169991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.2192169991
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1302987031
Short name T906
Test name
Test status
Simulation time 266230093 ps
CPU time 1.25 seconds
Started Aug 09 07:01:55 PM PDT 24
Finished Aug 09 07:01:57 PM PDT 24
Peak memory 196508 kb
Host smart-cd86e3fe-0f5d-4367-aefa-dbded7dacb46
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302987031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1302987031
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2670482329
Short name T877
Test name
Test status
Simulation time 1584614559 ps
CPU time 1.55 seconds
Started Aug 09 07:01:45 PM PDT 24
Finished Aug 09 07:01:46 PM PDT 24
Peak memory 196572 kb
Host smart-199e5fd5-3d44-4222-9cf0-4f8c7d7d36ef
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2670482329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2670482329
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3626774170
Short name T917
Test name
Test status
Simulation time 42643134 ps
CPU time 1.2 seconds
Started Aug 09 07:01:47 PM PDT 24
Finished Aug 09 07:01:48 PM PDT 24
Peak memory 196500 kb
Host smart-569acc4a-267f-41a0-83bb-77ef6c200c5c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626774170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3626774170
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1078251755
Short name T911
Test name
Test status
Simulation time 130067737 ps
CPU time 0.91 seconds
Started Aug 09 07:01:55 PM PDT 24
Finished Aug 09 07:01:56 PM PDT 24
Peak memory 196260 kb
Host smart-cbac42ec-6484-4ed0-8bd5-6e30ceb7a602
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1078251755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1078251755
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.676346485
Short name T910
Test name
Test status
Simulation time 535004966 ps
CPU time 0.9 seconds
Started Aug 09 07:01:56 PM PDT 24
Finished Aug 09 07:01:57 PM PDT 24
Peak memory 197568 kb
Host smart-9fb08e6b-8011-4754-93be-f71e97388988
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676346485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.676346485
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1466832019
Short name T915
Test name
Test status
Simulation time 141278505 ps
CPU time 1 seconds
Started Aug 09 07:01:55 PM PDT 24
Finished Aug 09 07:01:56 PM PDT 24
Peak memory 195908 kb
Host smart-9891ab08-7e7c-4f06-a03a-e77babdcc839
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1466832019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.1466832019
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2901205244
Short name T850
Test name
Test status
Simulation time 38589530 ps
CPU time 1.23 seconds
Started Aug 09 07:01:56 PM PDT 24
Finished Aug 09 07:01:57 PM PDT 24
Peak memory 198108 kb
Host smart-31411a0e-7b1b-4a8c-b298-589208a847af
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901205244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2901205244
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1575950496
Short name T901
Test name
Test status
Simulation time 33520315 ps
CPU time 0.82 seconds
Started Aug 09 07:01:57 PM PDT 24
Finished Aug 09 07:01:58 PM PDT 24
Peak memory 196060 kb
Host smart-00e585e6-4e89-424d-8089-50ee06c5b20b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1575950496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.1575950496
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2731056398
Short name T878
Test name
Test status
Simulation time 143348416 ps
CPU time 0.89 seconds
Started Aug 09 07:01:58 PM PDT 24
Finished Aug 09 07:01:59 PM PDT 24
Peak memory 195280 kb
Host smart-8390c1a7-a558-4466-9fa0-c2a25e21854c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731056398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2731056398
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1015970489
Short name T909
Test name
Test status
Simulation time 187246866 ps
CPU time 1.25 seconds
Started Aug 09 07:01:57 PM PDT 24
Finished Aug 09 07:01:59 PM PDT 24
Peak memory 195732 kb
Host smart-b3370fe8-f44f-4f3b-b22b-05c5222a94fa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1015970489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.1015970489
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1225543882
Short name T873
Test name
Test status
Simulation time 180682464 ps
CPU time 1.18 seconds
Started Aug 09 07:02:01 PM PDT 24
Finished Aug 09 07:02:02 PM PDT 24
Peak memory 197976 kb
Host smart-64b10ad7-353a-49d9-be41-d1329f90b76c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225543882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1225543882
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3189365842
Short name T856
Test name
Test status
Simulation time 227696466 ps
CPU time 1.38 seconds
Started Aug 09 07:02:01 PM PDT 24
Finished Aug 09 07:02:03 PM PDT 24
Peak memory 196492 kb
Host smart-8389e55e-d0c0-4ba4-9b4f-607353d6e3bf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3189365842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.3189365842
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3654366585
Short name T926
Test name
Test status
Simulation time 49881335 ps
CPU time 1.28 seconds
Started Aug 09 07:01:58 PM PDT 24
Finished Aug 09 07:01:59 PM PDT 24
Peak memory 196072 kb
Host smart-e1be5f85-c0fd-48c6-a8c1-c3b726dce278
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654366585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3654366585
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1049143271
Short name T880
Test name
Test status
Simulation time 626932975 ps
CPU time 1.47 seconds
Started Aug 09 07:02:00 PM PDT 24
Finished Aug 09 07:02:01 PM PDT 24
Peak memory 197984 kb
Host smart-b41aaec2-875e-4e3a-838f-39d8532684e4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1049143271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.1049143271
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3348347236
Short name T868
Test name
Test status
Simulation time 132111810 ps
CPU time 1.1 seconds
Started Aug 09 07:01:55 PM PDT 24
Finished Aug 09 07:01:57 PM PDT 24
Peak memory 198112 kb
Host smart-035b0a45-e6c0-4e64-9195-73e41a1f1767
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348347236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3348347236
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2938190056
Short name T883
Test name
Test status
Simulation time 227380060 ps
CPU time 1.27 seconds
Started Aug 09 07:01:54 PM PDT 24
Finished Aug 09 07:01:56 PM PDT 24
Peak memory 195632 kb
Host smart-b4ac9b75-50d3-4a2e-898d-bf2b92416a1d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2938190056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2938190056
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.54942140
Short name T934
Test name
Test status
Simulation time 52609844 ps
CPU time 1.27 seconds
Started Aug 09 07:01:57 PM PDT 24
Finished Aug 09 07:01:58 PM PDT 24
Peak memory 196792 kb
Host smart-d27cc6bc-b9fb-4120-82e3-d0fa8d650579
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54942140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.54942140
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1299507790
Short name T928
Test name
Test status
Simulation time 230862090 ps
CPU time 1 seconds
Started Aug 09 07:02:00 PM PDT 24
Finished Aug 09 07:02:01 PM PDT 24
Peak memory 197344 kb
Host smart-1f2ef347-8c9f-4f72-bb69-b4835f674a1d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1299507790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.1299507790
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2645597074
Short name T919
Test name
Test status
Simulation time 44194965 ps
CPU time 1.24 seconds
Started Aug 09 07:01:56 PM PDT 24
Finished Aug 09 07:01:58 PM PDT 24
Peak memory 196592 kb
Host smart-287a41aa-48c2-458c-b9ee-0b2db66ff5e7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645597074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2645597074
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2993837128
Short name T858
Test name
Test status
Simulation time 1285795362 ps
CPU time 1.18 seconds
Started Aug 09 07:01:58 PM PDT 24
Finished Aug 09 07:01:59 PM PDT 24
Peak memory 196568 kb
Host smart-c20cfdf5-2783-4fa7-82c4-00e1355ba292
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2993837128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2993837128
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.447199787
Short name T854
Test name
Test status
Simulation time 52684370 ps
CPU time 1.13 seconds
Started Aug 09 07:01:53 PM PDT 24
Finished Aug 09 07:01:55 PM PDT 24
Peak memory 196584 kb
Host smart-d50012ae-e4b1-4ce0-b176-44c4e8edd5b2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447199787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.447199787
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.51062868
Short name T912
Test name
Test status
Simulation time 71268536 ps
CPU time 1.13 seconds
Started Aug 09 07:01:56 PM PDT 24
Finished Aug 09 07:01:57 PM PDT 24
Peak memory 196572 kb
Host smart-0be0e251-1374-4a4a-8fcd-f2ec6806730b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=51062868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.51062868
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3604068480
Short name T933
Test name
Test status
Simulation time 61895938 ps
CPU time 1.24 seconds
Started Aug 09 07:01:56 PM PDT 24
Finished Aug 09 07:01:58 PM PDT 24
Peak memory 195872 kb
Host smart-41bf39ed-01c3-4724-88c0-0d838507249a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604068480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3604068480
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.270828006
Short name T923
Test name
Test status
Simulation time 73126359 ps
CPU time 1.21 seconds
Started Aug 09 07:01:49 PM PDT 24
Finished Aug 09 07:01:51 PM PDT 24
Peak memory 195712 kb
Host smart-582db9d0-1f5f-4465-a68d-df47407bd34a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=270828006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.270828006
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1057551291
Short name T861
Test name
Test status
Simulation time 50482342 ps
CPU time 0.83 seconds
Started Aug 09 07:01:46 PM PDT 24
Finished Aug 09 07:01:47 PM PDT 24
Peak memory 196156 kb
Host smart-e5035efb-83e9-4686-a37e-c67e722c211c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057551291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1057551291
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2559703059
Short name T860
Test name
Test status
Simulation time 57057175 ps
CPU time 1.12 seconds
Started Aug 09 07:01:56 PM PDT 24
Finished Aug 09 07:01:57 PM PDT 24
Peak memory 197544 kb
Host smart-87ba3058-2b33-48f5-89d4-28d599a4454b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2559703059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.2559703059
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.110471449
Short name T943
Test name
Test status
Simulation time 40113566 ps
CPU time 0.94 seconds
Started Aug 09 07:01:57 PM PDT 24
Finished Aug 09 07:01:58 PM PDT 24
Peak memory 195380 kb
Host smart-d8636afd-2f02-43da-9b5f-9d285c98fc19
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110471449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.110471449
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.4288406033
Short name T905
Test name
Test status
Simulation time 61985723 ps
CPU time 1.11 seconds
Started Aug 09 07:02:01 PM PDT 24
Finished Aug 09 07:02:02 PM PDT 24
Peak memory 196372 kb
Host smart-2e4e5c74-88f8-4a10-9766-4fe7ae2ca5b9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4288406033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.4288406033
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2272901401
Short name T914
Test name
Test status
Simulation time 244104889 ps
CPU time 1.49 seconds
Started Aug 09 07:01:59 PM PDT 24
Finished Aug 09 07:02:01 PM PDT 24
Peak memory 196616 kb
Host smart-bd932389-13b7-4323-b070-f1a0bbcf8272
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272901401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2272901401
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2974317916
Short name T945
Test name
Test status
Simulation time 354030760 ps
CPU time 0.87 seconds
Started Aug 09 07:01:55 PM PDT 24
Finished Aug 09 07:01:56 PM PDT 24
Peak memory 195408 kb
Host smart-f1a41c9c-1dc7-452a-8f7b-07e210dae231
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2974317916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.2974317916
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2290303296
Short name T887
Test name
Test status
Simulation time 158354344 ps
CPU time 1.05 seconds
Started Aug 09 07:01:56 PM PDT 24
Finished Aug 09 07:01:57 PM PDT 24
Peak memory 197988 kb
Host smart-c3d310f8-6a66-44cb-a521-43b84aeb77ef
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290303296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2290303296
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3160127168
Short name T930
Test name
Test status
Simulation time 84351075 ps
CPU time 0.89 seconds
Started Aug 09 07:01:58 PM PDT 24
Finished Aug 09 07:01:59 PM PDT 24
Peak memory 195428 kb
Host smart-8357bb5a-6ec5-44a0-aaf4-e1e42479d3dd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3160127168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.3160127168
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.762340947
Short name T939
Test name
Test status
Simulation time 108511341 ps
CPU time 1.05 seconds
Started Aug 09 07:01:57 PM PDT 24
Finished Aug 09 07:01:58 PM PDT 24
Peak memory 196572 kb
Host smart-f30ffcb6-d276-4fce-8151-e8d3a3ba7545
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762340947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.762340947
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3503728820
Short name T936
Test name
Test status
Simulation time 30489906 ps
CPU time 0.97 seconds
Started Aug 09 07:01:57 PM PDT 24
Finished Aug 09 07:01:58 PM PDT 24
Peak memory 196492 kb
Host smart-29d334c3-bb0b-4ed1-8a32-add4fdff745d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3503728820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3503728820
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3562824434
Short name T874
Test name
Test status
Simulation time 122369332 ps
CPU time 1.33 seconds
Started Aug 09 07:02:06 PM PDT 24
Finished Aug 09 07:02:08 PM PDT 24
Peak memory 196820 kb
Host smart-e4c8d595-4ded-4644-8e1b-bf51d1d9f3f3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562824434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3562824434
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3936225460
Short name T908
Test name
Test status
Simulation time 29198663 ps
CPU time 0.89 seconds
Started Aug 09 07:02:08 PM PDT 24
Finished Aug 09 07:02:09 PM PDT 24
Peak memory 195424 kb
Host smart-76d44b6c-686f-4ffd-b52d-c835742b3cbe
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3936225460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.3936225460
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1701470984
Short name T849
Test name
Test status
Simulation time 46120828 ps
CPU time 1.24 seconds
Started Aug 09 07:02:04 PM PDT 24
Finished Aug 09 07:02:06 PM PDT 24
Peak memory 196788 kb
Host smart-c9bd8738-7db2-4fed-8938-d01153d12edf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701470984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1701470984
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2147537589
Short name T889
Test name
Test status
Simulation time 55993231 ps
CPU time 1.01 seconds
Started Aug 09 07:02:05 PM PDT 24
Finished Aug 09 07:02:06 PM PDT 24
Peak memory 196648 kb
Host smart-69912465-406a-4632-b6ef-a7e82b31860a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2147537589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.2147537589
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2508516654
Short name T902
Test name
Test status
Simulation time 36769285 ps
CPU time 0.86 seconds
Started Aug 09 07:02:07 PM PDT 24
Finished Aug 09 07:02:08 PM PDT 24
Peak memory 196076 kb
Host smart-f7d9a1a7-371b-4ed9-a97b-09f2ef26afad
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508516654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2508516654
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3197969287
Short name T870
Test name
Test status
Simulation time 99662110 ps
CPU time 1.06 seconds
Started Aug 09 07:02:06 PM PDT 24
Finished Aug 09 07:02:08 PM PDT 24
Peak memory 196764 kb
Host smart-b7afacaf-41ad-4d60-af3d-631e5e8d2e3c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3197969287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.3197969287
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3690590704
Short name T929
Test name
Test status
Simulation time 59326210 ps
CPU time 1.14 seconds
Started Aug 09 07:02:05 PM PDT 24
Finished Aug 09 07:02:06 PM PDT 24
Peak memory 196716 kb
Host smart-0e00bea9-7600-41bc-b6cc-e96c119008e6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690590704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3690590704
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1684993577
Short name T925
Test name
Test status
Simulation time 80407727 ps
CPU time 1.32 seconds
Started Aug 09 07:02:05 PM PDT 24
Finished Aug 09 07:02:07 PM PDT 24
Peak memory 198088 kb
Host smart-ad59aac7-aabf-4be2-bc79-e32ee068ecd5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1684993577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.1684993577
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4228008106
Short name T882
Test name
Test status
Simulation time 66146970 ps
CPU time 1.25 seconds
Started Aug 09 07:02:06 PM PDT 24
Finished Aug 09 07:02:07 PM PDT 24
Peak memory 196748 kb
Host smart-5b85c5d3-8650-4ea4-b8a5-93a9d7a1ca93
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228008106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4228008106
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2466476193
Short name T944
Test name
Test status
Simulation time 85195586 ps
CPU time 1.29 seconds
Started Aug 09 07:02:07 PM PDT 24
Finished Aug 09 07:02:08 PM PDT 24
Peak memory 196852 kb
Host smart-52d0e5f0-2ac6-4228-af65-118b3e180fd0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2466476193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2466476193
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.325333494
Short name T886
Test name
Test status
Simulation time 35731629 ps
CPU time 0.88 seconds
Started Aug 09 07:02:08 PM PDT 24
Finished Aug 09 07:02:08 PM PDT 24
Peak memory 195608 kb
Host smart-53bb2770-a3a2-435a-a744-2c0c5423a63f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325333494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.325333494
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3301214763
Short name T863
Test name
Test status
Simulation time 34416945 ps
CPU time 0.78 seconds
Started Aug 09 07:01:48 PM PDT 24
Finished Aug 09 07:01:49 PM PDT 24
Peak memory 196084 kb
Host smart-3391770a-8862-4bad-8643-dd784b870bec
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3301214763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3301214763
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3919510358
Short name T866
Test name
Test status
Simulation time 138666423 ps
CPU time 1.45 seconds
Started Aug 09 07:01:47 PM PDT 24
Finished Aug 09 07:01:49 PM PDT 24
Peak memory 196620 kb
Host smart-412bcefa-7ec7-47e4-82fa-63c995ca94db
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919510358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3919510358
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3128718182
Short name T859
Test name
Test status
Simulation time 219826172 ps
CPU time 1.04 seconds
Started Aug 09 07:01:47 PM PDT 24
Finished Aug 09 07:01:48 PM PDT 24
Peak memory 195620 kb
Host smart-88b5ebd4-bd64-4190-b6f8-02741e96ac40
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3128718182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.3128718182
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1232803840
Short name T857
Test name
Test status
Simulation time 98166199 ps
CPU time 0.92 seconds
Started Aug 09 07:01:51 PM PDT 24
Finished Aug 09 07:01:52 PM PDT 24
Peak memory 196380 kb
Host smart-932c0810-cbbd-4f06-bd52-98ecef6a74c3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232803840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1232803840
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.456300321
Short name T927
Test name
Test status
Simulation time 260701754 ps
CPU time 1.12 seconds
Started Aug 09 07:01:51 PM PDT 24
Finished Aug 09 07:01:52 PM PDT 24
Peak memory 195392 kb
Host smart-d2021e09-deef-48dd-807c-5cb366711c7c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=456300321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.456300321
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3704819243
Short name T931
Test name
Test status
Simulation time 44843529 ps
CPU time 0.8 seconds
Started Aug 09 07:01:50 PM PDT 24
Finished Aug 09 07:01:51 PM PDT 24
Peak memory 195276 kb
Host smart-f77fe261-9b8b-47a2-9f9f-070b477651a8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704819243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3704819243
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.222844311
Short name T869
Test name
Test status
Simulation time 150788221 ps
CPU time 0.98 seconds
Started Aug 09 07:01:48 PM PDT 24
Finished Aug 09 07:01:49 PM PDT 24
Peak memory 196656 kb
Host smart-b543310f-4a42-48ba-9b44-4a0742dfcf9c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=222844311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.222844311
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.66206887
Short name T904
Test name
Test status
Simulation time 155918563 ps
CPU time 1.54 seconds
Started Aug 09 07:01:47 PM PDT 24
Finished Aug 09 07:01:49 PM PDT 24
Peak memory 196720 kb
Host smart-03ba815b-1d7f-43db-be32-354b91a8d6c5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66206887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.66206887
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3957383334
Short name T888
Test name
Test status
Simulation time 48607762 ps
CPU time 1.29 seconds
Started Aug 09 07:01:48 PM PDT 24
Finished Aug 09 07:01:49 PM PDT 24
Peak memory 196780 kb
Host smart-aa32168e-0c91-4050-98cc-956e5e7bb020
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3957383334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3957383334
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2586807479
Short name T884
Test name
Test status
Simulation time 83330698 ps
CPU time 1.31 seconds
Started Aug 09 07:01:48 PM PDT 24
Finished Aug 09 07:01:49 PM PDT 24
Peak memory 197300 kb
Host smart-8b578a9a-f9d7-4329-abab-88e12e55f6b8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586807479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2586807479
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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