Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3937056	1			T23	89		T24	84		T25	1
all_pins[1]	3937056	1			T23	89		T24	84		T25	1
all_pins[2]	3937056	1			T23	89		T24	84		T25	1
all_pins[3]	3937056	1			T23	89		T24	84		T25	1
all_pins[4]	3937056	1			T23	89		T24	84		T25	1
all_pins[5]	3937056	1			T23	89		T24	84		T25	1
all_pins[6]	3937056	1			T23	89		T24	84		T25	1
all_pins[7]	3937056	1			T23	89		T24	84		T25	1
all_pins[8]	3937056	1			T23	89		T24	84		T25	1
all_pins[9]	3937056	1			T23	89		T24	84		T25	1
all_pins[10]	3937056	1			T23	89		T24	84		T25	1
all_pins[11]	3937056	1			T23	89		T24	84		T25	1
all_pins[12]	3937056	1			T23	89		T24	84		T25	1
all_pins[13]	3937056	1			T23	89		T24	84		T25	1
all_pins[14]	3937056	1			T23	89		T24	84		T25	1
all_pins[15]	3937056	1			T23	89		T24	84		T25	1
all_pins[16]	3937056	1			T23	89		T24	84		T25	1
all_pins[17]	3937056	1			T23	89		T24	84		T25	1
all_pins[18]	3937056	1			T23	89		T24	84		T25	1
all_pins[19]	3937056	1			T23	89		T24	84		T25	1
all_pins[20]	3937056	1			T23	89		T24	84		T25	1
all_pins[21]	3937056	1			T23	89		T24	84		T25	1
all_pins[22]	3937056	1			T23	89		T24	84		T25	1
all_pins[23]	3937056	1			T23	89		T24	84		T25	1
all_pins[24]	3937056	1			T23	89		T24	84		T25	1
all_pins[25]	3937056	1			T23	89		T24	84		T25	1
all_pins[26]	3937056	1			T23	89		T24	84		T25	1
all_pins[27]	3937056	1			T23	89		T24	84		T25	1
all_pins[28]	3937056	1			T23	89		T24	84		T25	1
all_pins[29]	3937056	1			T23	89		T24	84		T25	1
all_pins[30]	3937056	1			T23	89		T24	84		T25	1
all_pins[31]	3937056	1			T23	89		T24	84		T25	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	78271900	1			T23	2456		T24	1352		T25	32
values[0x1]	47713892	1			T23	392		T24	1336		T27	258917
transitions[0x0=>0x1]	28589748	1			T23	282		T24	663		T27	154296
transitions[0x1=>0x0]	28589594	1			T23	282		T24	662		T27	154296

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2443965	1			T23	84		T24	39		T25	1
all_pins[0]	values[0x1]	1493091	1			T23	5		T24	45		T27	8341
all_pins[0]	transitions[0x0=>0x1]	926992	1			T23	5		T24	23		T27	5176
all_pins[0]	transitions[0x1=>0x0]	920830	1			T23	7		T24	26		T27	4739
all_pins[1]	values[0x0]	2451927	1			T23	72		T24	36		T25	1
all_pins[1]	values[0x1]	1485129	1			T23	17		T24	48		T27	8491
all_pins[1]	transitions[0x0=>0x1]	888479	1			T23	17		T24	25		T27	4848
all_pins[1]	transitions[0x1=>0x0]	896441	1			T23	5		T24	22		T27	4698
all_pins[2]	values[0x0]	2448531	1			T23	77		T24	48		T25	1
all_pins[2]	values[0x1]	1488525	1			T23	12		T24	36		T27	7949
all_pins[2]	transitions[0x0=>0x1]	894141	1			T23	6		T24	13		T27	4538
all_pins[2]	transitions[0x1=>0x0]	890745	1			T23	11		T24	25		T27	5080
all_pins[3]	values[0x0]	2443159	1			T23	79		T24	34		T25	1
all_pins[3]	values[0x1]	1493897	1			T23	10		T24	50		T27	7886
all_pins[3]	transitions[0x0=>0x1]	895859	1			T23	10		T24	28		T27	4802
all_pins[3]	transitions[0x1=>0x0]	890487	1			T23	12		T24	14		T27	4865
all_pins[4]	values[0x0]	2438123	1			T23	71		T24	50		T25	1
all_pins[4]	values[0x1]	1498933	1			T23	18		T24	34		T27	7993
all_pins[4]	transitions[0x0=>0x1]	896778	1			T23	17		T24	10		T27	4814
all_pins[4]	transitions[0x1=>0x0]	891742	1			T23	9		T24	26		T27	4707
all_pins[5]	values[0x0]	2453120	1			T23	79		T24	44		T25	1
all_pins[5]	values[0x1]	1483936	1			T23	10		T24	40		T27	8089
all_pins[5]	transitions[0x0=>0x1]	885148	1			T23	5		T24	25		T27	4826
all_pins[5]	transitions[0x1=>0x0]	900145	1			T23	13		T24	19		T27	4730
all_pins[6]	values[0x0]	2447137	1			T23	82		T24	46		T25	1
all_pins[6]	values[0x1]	1489919	1			T23	7		T24	38		T27	8246
all_pins[6]	transitions[0x0=>0x1]	893894	1			T23	6		T24	19		T27	4793
all_pins[6]	transitions[0x1=>0x0]	887911	1			T23	9		T24	21		T27	4636
all_pins[7]	values[0x0]	2445653	1			T23	76		T24	43		T25	1
all_pins[7]	values[0x1]	1491403	1			T23	13		T24	41		T27	8272
all_pins[7]	transitions[0x0=>0x1]	892029	1			T23	9		T24	22		T27	4838
all_pins[7]	transitions[0x1=>0x0]	890545	1			T23	3		T24	19		T27	4812
all_pins[8]	values[0x0]	2443344	1			T23	80		T24	46		T25	1
all_pins[8]	values[0x1]	1493712	1			T23	9		T24	38		T27	8440
all_pins[8]	transitions[0x0=>0x1]	895254	1			T23	6		T24	20		T27	4967
all_pins[8]	transitions[0x1=>0x0]	892945	1			T23	10		T24	23		T27	4799
all_pins[9]	values[0x0]	2443966	1			T23	79		T24	39		T25	1
all_pins[9]	values[0x1]	1493090	1			T23	10		T24	45		T27	8002
all_pins[9]	transitions[0x0=>0x1]	892503	1			T23	10		T24	26		T27	4649
all_pins[9]	transitions[0x1=>0x0]	893125	1			T23	9		T24	19		T27	5087
all_pins[10]	values[0x0]	2443961	1			T23	77		T24	43		T25	1
all_pins[10]	values[0x1]	1493095	1			T23	12		T24	41		T27	8090
all_pins[10]	transitions[0x0=>0x1]	890851	1			T23	5		T24	20		T27	4892
all_pins[10]	transitions[0x1=>0x0]	890846	1			T23	3		T24	24		T27	4804
all_pins[11]	values[0x0]	2446571	1			T23	76		T24	35		T25	1
all_pins[11]	values[0x1]	1490485	1			T23	13		T24	49		T27	8144
all_pins[11]	transitions[0x0=>0x1]	892494	1			T23	6		T24	24		T27	4850
all_pins[11]	transitions[0x1=>0x0]	895104	1			T23	5		T24	16		T27	4796
all_pins[12]	values[0x0]	2445859	1			T23	81		T24	49		T25	1
all_pins[12]	values[0x1]	1491197	1			T23	8		T24	35		T27	8136
all_pins[12]	transitions[0x0=>0x1]	890780	1			T23	8		T24	13		T27	4691
all_pins[12]	transitions[0x1=>0x0]	890068	1			T23	13		T24	27		T27	4699
all_pins[13]	values[0x0]	2447277	1			T23	70		T24	42		T25	1
all_pins[13]	values[0x1]	1489779	1			T23	19		T24	42		T27	7778
all_pins[13]	transitions[0x0=>0x1]	893199	1			T23	19		T24	24		T27	4712
all_pins[13]	transitions[0x1=>0x0]	894617	1			T23	8		T24	17		T27	5070
all_pins[14]	values[0x0]	2442351	1			T23	74		T24	38		T25	1
all_pins[14]	values[0x1]	1494705	1			T23	15		T24	46		T27	8279
all_pins[14]	transitions[0x0=>0x1]	896404	1			T23	9		T24	23		T27	4907
all_pins[14]	transitions[0x1=>0x0]	891478	1			T23	13		T24	19		T27	4406
all_pins[15]	values[0x0]	2442823	1			T23	80		T24	41		T25	1
all_pins[15]	values[0x1]	1494233	1			T23	9		T24	43		T27	8112
all_pins[15]	transitions[0x0=>0x1]	891462	1			T23	7		T24	19		T27	4713
all_pins[15]	transitions[0x1=>0x0]	891934	1			T23	13		T24	22		T27	4880
all_pins[16]	values[0x0]	2444915	1			T23	79		T24	39		T25	1
all_pins[16]	values[0x1]	1492141	1			T23	10		T24	45		T27	8099
all_pins[16]	transitions[0x0=>0x1]	891566	1			T23	10		T24	18		T27	4932
all_pins[16]	transitions[0x1=>0x0]	893658	1			T23	9		T24	16		T27	4945
all_pins[17]	values[0x0]	2449374	1			T23	78		T24	46		T25	1
all_pins[17]	values[0x1]	1487682	1			T23	11		T24	38		T27	8024
all_pins[17]	transitions[0x0=>0x1]	891264	1			T23	8		T24	15		T27	4729
all_pins[17]	transitions[0x1=>0x0]	895723	1			T23	7		T24	22		T27	4804
all_pins[18]	values[0x0]	2446420	1			T23	84		T24	46		T25	1
all_pins[18]	values[0x1]	1490636	1			T23	5		T24	38		T27	7916
all_pins[18]	transitions[0x0=>0x1]	893187	1			T23	4		T24	18		T27	4642
all_pins[18]	transitions[0x1=>0x0]	890233	1			T23	10		T24	18		T27	4750
all_pins[19]	values[0x0]	2447976	1			T23	75		T24	41		T25	1
all_pins[19]	values[0x1]	1489080	1			T23	14		T24	43		T27	7563
all_pins[19]	transitions[0x0=>0x1]	892997	1			T23	14		T24	21		T27	4674
all_pins[19]	transitions[0x1=>0x0]	894553	1			T23	5		T24	16		T27	5027
all_pins[20]	values[0x0]	2444890	1			T23	76		T24	38		T25	1
all_pins[20]	values[0x1]	1492166	1			T23	13		T24	46		T27	8078
all_pins[20]	transitions[0x0=>0x1]	894638	1			T23	8		T24	25		T27	5153
all_pins[20]	transitions[0x1=>0x0]	891552	1			T23	9		T24	22		T27	4638
all_pins[21]	values[0x0]	2447441	1			T23	74		T24	47		T25	1
all_pins[21]	values[0x1]	1489615	1			T23	15		T24	37		T27	7722
all_pins[21]	transitions[0x0=>0x1]	888500	1			T23	10		T24	17		T27	4724
all_pins[21]	transitions[0x1=>0x0]	891051	1			T23	8		T24	26		T27	5080
all_pins[22]	values[0x0]	2446160	1			T23	79		T24	51		T25	1
all_pins[22]	values[0x1]	1490896	1			T23	10		T24	33		T27	8274
all_pins[22]	transitions[0x0=>0x1]	892339	1			T23	7		T24	22		T27	5219
all_pins[22]	transitions[0x1=>0x0]	891058	1			T23	12		T24	26		T27	4667
all_pins[23]	values[0x0]	2443075	1			T23	75		T24	45		T25	1
all_pins[23]	values[0x1]	1493981	1			T23	14		T24	39		T27	7943
all_pins[23]	transitions[0x0=>0x1]	894692	1			T23	8		T24	25		T27	4714
all_pins[23]	transitions[0x1=>0x0]	891607	1			T23	4		T24	19		T27	5045
all_pins[24]	values[0x0]	2453464	1			T23	66		T24	37		T25	1
all_pins[24]	values[0x1]	1483592	1			T23	23		T24	47		T27	8150
all_pins[24]	transitions[0x0=>0x1]	886157	1			T23	10		T24	25		T27	4783
all_pins[24]	transitions[0x1=>0x0]	896546	1			T23	1		T24	17		T27	4576
all_pins[25]	values[0x0]	2445641	1			T23	80		T24	45		T25	1
all_pins[25]	values[0x1]	1491415	1			T23	9		T24	39		T27	8396
all_pins[25]	transitions[0x0=>0x1]	895893	1			T23	6		T24	17		T27	5031
all_pins[25]	transitions[0x1=>0x0]	888070	1			T23	20		T24	25		T27	4785
all_pins[26]	values[0x0]	2443849	1			T23	81		T24	41		T25	1
all_pins[26]	values[0x1]	1493207	1			T23	8		T24	43		T27	8175
all_pins[26]	transitions[0x0=>0x1]	895728	1			T23	7		T24	25		T27	4665
all_pins[26]	transitions[0x1=>0x0]	893936	1			T23	8		T24	21		T27	4886
all_pins[27]	values[0x0]	2449186	1			T23	66		T24	40		T25	1
all_pins[27]	values[0x1]	1487870	1			T23	23		T24	44		T27	7853
all_pins[27]	transitions[0x0=>0x1]	887431	1			T23	20		T24	20		T27	4698
all_pins[27]	transitions[0x1=>0x0]	892768	1			T23	5		T24	19		T27	5020
all_pins[28]	values[0x0]	2445318	1			T23	71		T24	51		T25	1
all_pins[28]	values[0x1]	1491738	1			T23	18		T24	33		T27	8001
all_pins[28]	transitions[0x0=>0x1]	893741	1			T23	10		T24	15		T27	4734
all_pins[28]	transitions[0x1=>0x0]	889873	1			T23	15		T24	26		T27	4586
all_pins[29]	values[0x0]	2446620	1			T23	75		T24	37		T25	1
all_pins[29]	values[0x1]	1490436	1			T23	14		T24	47		T27	8398
all_pins[29]	transitions[0x0=>0x1]	890893	1			T23	7		T24	25		T27	5152
all_pins[29]	transitions[0x1=>0x0]	892195	1			T23	11		T24	11		T27	4755
all_pins[30]	values[0x0]	2439831	1			T23	78		T24	40		T25	1
all_pins[30]	values[0x1]	1497225	1			T23	11		T24	44		T27	8173
all_pins[30]	transitions[0x0=>0x1]	894881	1			T23	3		T24	16		T27	4685
all_pins[30]	transitions[0x1=>0x0]	888092	1			T23	6		T24	19		T27	4910
all_pins[31]	values[0x0]	2449973	1			T23	82		T24	35		T25	1
all_pins[31]	values[0x1]	1487083	1			T23	7		T24	49		T27	7904
all_pins[31]	transitions[0x0=>0x1]	889574	1			T23	5		T24	25		T27	4745
all_pins[31]	transitions[0x1=>0x0]	899716	1			T23	9		T24	20		T27	5014