Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[1]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[2]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[3]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[4]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[5]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[6]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[7]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[8]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[9]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[10]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[11]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[12]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[13]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[14]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[15]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[16]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[17]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[18]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[19]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[20]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[21]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[22]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[23]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[24]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[25]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[26]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[27]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[28]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[29]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[30]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[31]	12934101	1			T23	211		T24	43197		T25	826

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

249210342

1

T23

3345

T24

691879

T25

7408

auto[1]

164680890

1

T23

3407

T24

690425

T25

19024

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

331178229

1

T23

6104

T24

138230

T25

14761

auto[1]

82713003

1

T23

648

T25

11671

T26

4090

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

306778833

1

T23

4935

T24

138230

T25

15004

auto[1]

107112399

1

T23

1817

T25

11428

T26

4285

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4810801	1			T23	94		T24	23456		T25	50
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3477078	1			T23	49		T24	19741		T25	246
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1295279	1			T23	19		T25	186		T26	42
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1677150	1			T23	30		T26	60		T27	588
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	386136	1			T23	12		T25	190		T27	11057
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1287657	1			T23	7		T25	154		T26	75
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4813734	1			T23	61		T24	21259		T25	54
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3472894	1			T23	68		T24	21938		T25	207
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1301532	1			T23	8		T25	177		T26	64
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1671380	1			T23	27		T26	76		T27	671
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	383637	1			T23	26		T25	184		T27	10971
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1290924	1			T23	21		T25	204		T26	64
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4803535	1			T23	46		T24	21593		T25	52
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3476974	1			T23	118		T24	21604		T25	245
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1300491	1			T25	177		T26	68		T27	7959
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1678014	1			T23	14		T26	50		T27	562
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	384772	1			T23	22		T25	188		T27	10972
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1290315	1			T23	11		T25	164		T26	97
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4809689	1			T23	49		T24	20278		T25	36
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3470806	1			T23	70		T24	22919		T25	237
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1301033	1			T23	16		T25	186		T26	60
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1677866	1			T23	40		T26	78		T27	693
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	383304	1			T23	18		T25	189		T27	10785
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1291403	1			T23	18		T25	178		T26	69
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4815851	1			T23	54		T24	22152		T25	52
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3469488	1			T23	88		T24	21045		T25	245
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1300344	1			T23	3		T25	194		T26	52
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1678106	1			T23	43		T26	86		T27	623
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	385803	1			T23	16		T25	204		T27	10980
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1284509	1			T23	7		T25	131		T26	53
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4810628	1			T23	107		T24	21643		T25	48
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3475544	1			T23	45		T24	21554		T25	213
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1303725	1			T23	17		T25	218		T26	57
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1674587	1			T23	39		T26	72		T27	582
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	383764	1			T23	1		T25	148		T27	10547
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1285853	1			T23	2		T25	199		T26	68
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4807290	1			T23	33		T24	20265		T25	44
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3480546	1			T23	92		T24	22932		T25	253
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1301136	1			T23	1		T25	161		T26	82
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1671952	1			T23	45		T26	36		T27	630
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	382738	1			T23	17		T25	184		T27	10864
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1290439	1			T23	23		T25	184		T26	75
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4813129	1			T23	49		T24	22642		T25	43
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3475913	1			T23	89		T24	20555		T25	225
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1301143	1			T23	8		T25	190		T26	51
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1673477	1			T23	35		T26	78		T27	694
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	384757	1			T23	13		T25	158		T27	11463
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1285682	1			T23	17		T25	210		T26	82
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4805448	1			T23	40		T24	22343		T25	43
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3481838	1			T23	114		T24	20854		T25	256
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1300994	1			T23	13		T25	195		T26	66
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1674294	1			T23	18		T26	85		T27	629
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	384218	1			T23	10		T25	162		T27	10882
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1287309	1			T23	16		T25	170		T26	50
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4813252	1			T23	42		T24	20811		T25	42
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3473540	1			T23	88		T24	22386		T25	255
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1305422	1			T23	5		T25	210		T26	64
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1673091	1			T23	33		T26	66		T27	605
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	383860	1			T23	13		T25	137		T27	10988
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1284936	1			T23	30		T25	182		T26	61
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4807884	1			T23	46		T24	21798		T25	51
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3477599	1			T23	126		T24	21399		T25	238
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1300074	1			T23	4		T25	198		T26	60
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1678397	1			T23	20		T26	78		T27	605
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	380552	1			T23	10		T25	176		T27	10728
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1289595	1			T23	5		T25	163		T26	53
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4814567	1			T23	103		T24	22274		T25	43
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3468315	1			T23	61		T24	20923		T25	281
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1303162	1			T23	3		T25	174		T26	60
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1676849	1			T23	34		T26	66		T27	687
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	384279	1			T23	8		T25	154		T27	11004
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1286929	1			T23	2		T25	174		T26	57
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4822016	1			T23	74		T24	21341		T25	37
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3466340	1			T23	69		T24	21856		T25	232
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1302641	1			T23	1		T25	178		T26	54
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1670552	1			T23	48		T26	80		T27	731
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	382701	1			T23	9		T25	221		T27	11628
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1289851	1			T23	10		T25	158		T26	39
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4817495	1			T23	55		T24	21634		T25	40
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3465425	1			T23	95		T24	21563		T25	267
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1298402	1			T23	14		T25	179		T26	70
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1679091	1			T23	21		T26	56		T27	629
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	386546	1			T23	12		T25	142		T27	11342
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1287142	1			T23	14		T25	198		T26	55
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4804729	1			T23	52		T24	22315		T25	43
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3477081	1			T23	83		T24	20882		T25	205
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1297566	1			T25	194		T26	57		T27	7878
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1675595	1			T23	37		T26	56		T27	699
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	387346	1			T23	24		T25	202		T27	11271
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1291784	1			T23	15		T25	182		T26	88
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4821061	1			T23	88		T24	22872		T25	36
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3475236	1			T23	52		T24	20325		T25	269
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1308899	1			T23	26		T25	142		T26	58
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1664192	1			T23	30		T26	74		T27	659
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	380471	1			T23	6		T25	221		T27	11353
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1284242	1			T23	9		T25	158		T26	74
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4822599	1			T23	111		T24	23659		T25	41
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3467036	1			T23	48		T24	19538		T25	224
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1296706	1			T23	10		T25	194		T26	58
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1680545	1			T23	39		T26	77		T27	644
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	383372	1			T23	3		T25	157		T27	10790
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1283843	1			T25	210		T26	70		T27	7482
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4809230	1			T23	75		T24	21761		T25	48
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3479432	1			T23	69		T24	21436		T25	236
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1300043	1			T23	5		T25	134		T26	58
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1677505	1			T23	44		T26	62		T27	599
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	380574	1			T23	11		T25	206		T27	10735
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1287317	1			T23	7		T25	202		T26	82
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4812529	1			T23	63		T24	20895		T25	43
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3481848	1			T23	101		T24	22302		T25	252
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1295757	1			T23	4		T25	152		T26	68
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1680025	1			T23	14		T26	56		T27	634
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	383601	1			T23	10		T25	199		T27	10956
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1280341	1			T23	19		T25	180		T26	68
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4811146	1			T23	28		T24	21182		T25	37
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3482758	1			T23	123		T24	22015		T25	256
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1298658	1			T25	178		T26	63		T27	8001
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1675028	1			T23	25		T26	82		T27	720
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	384468	1			T23	22		T25	172		T27	10948
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1282043	1			T23	13		T25	183		T26	54
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4815455	1			T23	62		T24	20527		T25	48
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3481514	1			T23	85		T24	22670		T25	259
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1293678	1			T23	2		T25	211		T26	75
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1676790	1			T23	18		T26	46		T27	711
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	384131	1			T23	19		T25	146		T27	11088
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1282533	1			T23	25		T25	162		T26	82
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4811711	1			T23	114		T24	22642		T25	42
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3482288	1			T23	31		T24	20555		T25	260
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1296132	1			T23	13		T25	176		T26	36
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1678669	1			T23	40		T26	107		T27	620
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	382418	1			T23	11		T25	176		T27	10518
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1282883	1			T23	2		T25	172		T26	60
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4811702	1			T23	63		T24	21379		T25	45
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3474552	1			T23	85		T24	21818		T25	248
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1294259	1			T23	1		T25	194		T26	92
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1680940	1			T23	25		T26	54		T27	721
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	385148	1			T23	25		T25	180		T27	11616
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1287500	1			T23	12		T25	159		T26	57
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4809243	1			T23	57		T24	20342		T25	52
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3479345	1			T23	78		T24	22855		T25	179
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1292636	1			T23	12		T25	196		T26	43
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1678872	1			T23	24		T26	74		T27	646
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	383312	1			T23	31		T25	210		T27	10702
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1290693	1			T23	9		T25	189		T26	66
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4811117	1			T23	73		T24	21090		T25	42
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3477130	1			T23	101		T24	22107		T25	195
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1297991	1			T23	18		T25	174		T26	72
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1680968	1			T23	11		T26	48		T27	625
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	384684	1			T23	7		T25	185		T27	11016
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1282211	1			T23	1		T25	230		T26	60
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4814273	1			T23	50		T24	20685		T25	50
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3477342	1			T23	86		T24	22512		T25	250
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1296831	1			T25	182		T26	70		T27	7784
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1675445	1			T23	21		T26	74		T27	693
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	384085	1			T23	22		T25	202		T27	11299
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1286125	1			T23	32		T25	142		T26	66
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4807987	1			T23	79		T24	21473		T25	42
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3478936	1			T23	76		T24	21724		T25	244
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1297383	1			T23	3		T25	172		T26	62
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1677012	1			T23	36		T26	72		T27	624
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	383540	1			T23	14		T25	184		T27	10922
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1289243	1			T23	3		T25	184		T26	75
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4807502	1			T23	80		T24	20786		T25	43
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3481648	1			T23	82		T24	22411		T25	242
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1296114	1			T23	12		T25	205		T26	52
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1683258	1			T23	5		T26	78		T27	721
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	385447	1			T23	24		T25	168		T27	11339
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1280132	1			T23	8		T25	168		T26	69
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4817488	1			T23	70		T24	21767		T25	43
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3474602	1			T23	62		T24	21430		T25	196
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1295291	1			T23	13		T25	200		T26	62
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1680410	1			T23	35		T26	60		T27	663
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	384338	1			T23	18		T25	178		T27	11548
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1281972	1			T23	13		T25	209		T26	71
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4807024	1			T23	43		T24	22299		T25	54
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3478896	1			T23	100		T24	20898		T25	237
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1292839	1			T23	4		T25	268		T26	86
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1682438	1			T23	11		T26	56		T27	616
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	384851	1			T23	23		T25	118		T27	10853
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1288053	1			T23	30		T25	149		T26	47
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4821586	1			T23	86		T24	21678		T25	49
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3467715	1			T23	52		T24	21519		T25	243
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1295998	1			T23	11		T25	170		T26	60
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1679453	1			T23	51		T26	67		T27	682
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	385017	1			T23	9		T25	178		T27	10486
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1284332	1			T23	2		T25	186		T26	72
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4813856	1			T23	104		T24	21038		T25	48
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3480622	1			T23	46		T24	22159		T25	201
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1290836	1			T23	6		T25	202		T26	59
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1679839	1			T23	29		T26	66		T27	779
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	386731	1			T23	13		T25	205		T27	11764
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1282217	1			T23	13		T25	170		T26	50

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal