Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[1]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[2]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[3]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[4]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[5]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[6]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[7]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[8]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[9]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[10]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[11]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[12]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[13]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[14]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[15]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[16]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[17]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[18]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[19]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[20]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[21]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[22]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[23]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[24]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[25]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[26]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[27]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[28]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[29]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[30]	12934101	1			T23	211		T24	43197		T25	826
bins_for_gpio_bits[31]	12934101	1			T23	211		T24	43197		T25	826

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

249210342

1

T23

3345

T24

691879

T25

7408

auto[1]

164680890

1

T23

3407

T24

690425

T25

19024

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

249201563

1

T23

3347

T24

691879

T25

7415

auto[1]

164689669

1

T23

3405

T24

690425

T25

19017

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7553048	1			T23	143		T24	23456		T25	178
bins_for_gpio_bits[0]	auto[0]	auto[1]	229913	1			T23	1		T25	58		T26	15
bins_for_gpio_bits[0]	auto[1]	auto[0]	230182	1			T25	58		T26	16		T27	1377
bins_for_gpio_bits[0]	auto[1]	auto[1]	4920958	1			T23	67		T24	19741		T25	532
bins_for_gpio_bits[1]	auto[0]	auto[0]	7556047	1			T23	95		T24	21259		T25	185
bins_for_gpio_bits[1]	auto[0]	auto[1]	230356	1			T23	1		T25	47		T26	13
bins_for_gpio_bits[1]	auto[1]	auto[0]	230599	1			T23	1		T25	46		T26	13
bins_for_gpio_bits[1]	auto[1]	auto[1]	4917099	1			T23	114		T24	21938		T25	548
bins_for_gpio_bits[2]	auto[0]	auto[0]	7551218	1			T23	60		T24	21593		T25	184
bins_for_gpio_bits[2]	auto[0]	auto[1]	230590	1			T25	46		T26	19		T27	1325
bins_for_gpio_bits[2]	auto[1]	auto[0]	230822	1			T25	45		T26	20		T27	1318
bins_for_gpio_bits[2]	auto[1]	auto[1]	4921471	1			T23	151		T24	21604		T25	551
bins_for_gpio_bits[3]	auto[0]	auto[0]	7557576	1			T23	104		T24	20278		T25	173
bins_for_gpio_bits[3]	auto[0]	auto[1]	230758	1			T23	1		T25	49		T26	16
bins_for_gpio_bits[3]	auto[1]	auto[0]	231012	1			T23	1		T25	49		T26	17
bins_for_gpio_bits[3]	auto[1]	auto[1]	4914755	1			T23	105		T24	22919		T25	555
bins_for_gpio_bits[4]	auto[0]	auto[0]	7563586	1			T23	99		T24	22152		T25	199
bins_for_gpio_bits[4]	auto[0]	auto[1]	230405	1			T23	1		T25	47		T26	15
bins_for_gpio_bits[4]	auto[1]	auto[0]	230715	1			T23	1		T25	47		T26	16
bins_for_gpio_bits[4]	auto[1]	auto[1]	4909395	1			T23	110		T24	21045		T25	533
bins_for_gpio_bits[5]	auto[0]	auto[0]	7558220	1			T23	163		T24	21643		T25	221
bins_for_gpio_bits[5]	auto[0]	auto[1]	230474	1			T23	1		T25	45		T26	19
bins_for_gpio_bits[5]	auto[1]	auto[0]	230720	1			T25	45		T26	19		T27	1386
bins_for_gpio_bits[5]	auto[1]	auto[1]	4914687	1			T23	47		T24	21554		T25	515
bins_for_gpio_bits[6]	auto[0]	auto[0]	7550118	1			T23	79		T24	20265		T25	162
bins_for_gpio_bits[6]	auto[0]	auto[1]	229961	1			T25	44		T26	19		T27	1354
bins_for_gpio_bits[6]	auto[1]	auto[0]	230260	1			T25	43		T26	20		T27	1352
bins_for_gpio_bits[6]	auto[1]	auto[1]	4923762	1			T23	132		T24	22932		T25	577
bins_for_gpio_bits[7]	auto[0]	auto[0]	7558076	1			T23	90		T24	22642		T25	187
bins_for_gpio_bits[7]	auto[0]	auto[1]	229416	1			T23	1		T25	46		T26	16
bins_for_gpio_bits[7]	auto[1]	auto[0]	229673	1			T23	2		T25	46		T26	16
bins_for_gpio_bits[7]	auto[1]	auto[1]	4916936	1			T23	118		T24	20555		T25	547
bins_for_gpio_bits[8]	auto[0]	auto[0]	7550627	1			T23	71		T24	22343		T25	187
bins_for_gpio_bits[8]	auto[0]	auto[1]	229816	1			T25	52		T26	11		T27	1358
bins_for_gpio_bits[8]	auto[1]	auto[0]	230109	1			T25	51		T26	11		T27	1352
bins_for_gpio_bits[8]	auto[1]	auto[1]	4923549	1			T23	140		T24	20854		T25	536
bins_for_gpio_bits[9]	auto[0]	auto[0]	7561496	1			T23	78		T24	20811		T25	202
bins_for_gpio_bits[9]	auto[0]	auto[1]	229990	1			T23	2		T25	50		T26	14
bins_for_gpio_bits[9]	auto[1]	auto[0]	230269	1			T23	2		T25	50		T26	15
bins_for_gpio_bits[9]	auto[1]	auto[1]	4912346	1			T23	129		T24	22386		T25	524
bins_for_gpio_bits[10]	auto[0]	auto[0]	7555951	1			T23	70		T24	21798		T25	194
bins_for_gpio_bits[10]	auto[0]	auto[1]	230140	1			T25	55		T26	15		T27	1340
bins_for_gpio_bits[10]	auto[1]	auto[0]	230404	1			T25	55		T26	16		T27	1338
bins_for_gpio_bits[10]	auto[1]	auto[1]	4917606	1			T23	141		T24	21399		T25	522
bins_for_gpio_bits[11]	auto[0]	auto[0]	7564598	1			T23	139		T24	22274		T25	168
bins_for_gpio_bits[11]	auto[0]	auto[1]	229735	1			T23	1		T25	49		T26	14
bins_for_gpio_bits[11]	auto[1]	auto[0]	229980	1			T23	1		T25	49		T26	15
bins_for_gpio_bits[11]	auto[1]	auto[1]	4909788	1			T23	70		T24	20923		T25	560
bins_for_gpio_bits[12]	auto[0]	auto[0]	7564667	1			T23	123		T24	21341		T25	169
bins_for_gpio_bits[12]	auto[0]	auto[1]	230244	1			T25	46		T26	12		T27	1297
bins_for_gpio_bits[12]	auto[1]	auto[0]	230542	1			T25	46		T26	13		T27	1293
bins_for_gpio_bits[12]	auto[1]	auto[1]	4908648	1			T23	88		T24	21856		T25	565
bins_for_gpio_bits[13]	auto[0]	auto[0]	7564880	1			T23	89		T24	21634		T25	175
bins_for_gpio_bits[13]	auto[0]	auto[1]	229849	1			T23	1		T25	45		T26	17
bins_for_gpio_bits[13]	auto[1]	auto[0]	230108	1			T23	1		T25	44		T26	18
bins_for_gpio_bits[13]	auto[1]	auto[1]	4909264	1			T23	120		T24	21563		T25	562
bins_for_gpio_bits[14]	auto[0]	auto[0]	7548033	1			T23	89		T24	22315		T25	193
bins_for_gpio_bits[14]	auto[0]	auto[1]	229593	1			T25	44		T26	15		T27	1320
bins_for_gpio_bits[14]	auto[1]	auto[0]	229857	1			T25	44		T26	15		T27	1315
bins_for_gpio_bits[14]	auto[1]	auto[1]	4926618	1			T23	122		T24	20882		T25	545
bins_for_gpio_bits[15]	auto[0]	auto[0]	7564266	1			T23	144		T24	22872		T25	142
bins_for_gpio_bits[15]	auto[0]	auto[1]	229596	1			T25	36		T26	15		T27	1304
bins_for_gpio_bits[15]	auto[1]	auto[0]	229886	1			T25	36		T26	15		T27	1301
bins_for_gpio_bits[15]	auto[1]	auto[1]	4910353	1			T23	67		T24	20325		T25	612
bins_for_gpio_bits[16]	auto[0]	auto[0]	7569485	1			T23	160		T24	23659		T25	184
bins_for_gpio_bits[16]	auto[0]	auto[1]	230093	1			T25	51		T26	16		T27	1366
bins_for_gpio_bits[16]	auto[1]	auto[0]	230365	1			T25	51		T26	16		T27	1361
bins_for_gpio_bits[16]	auto[1]	auto[1]	4904158	1			T23	51		T24	19538		T25	540
bins_for_gpio_bits[17]	auto[0]	auto[0]	7556170	1			T23	124		T24	21761		T25	144
bins_for_gpio_bits[17]	auto[0]	auto[1]	230377	1			T25	38		T26	21		T27	1345
bins_for_gpio_bits[17]	auto[1]	auto[0]	230608	1			T25	38		T26	21		T27	1344
bins_for_gpio_bits[17]	auto[1]	auto[1]	4916946	1			T23	87		T24	21436		T25	606
bins_for_gpio_bits[18]	auto[0]	auto[0]	7558146	1			T23	80		T24	20895		T25	154
bins_for_gpio_bits[18]	auto[0]	auto[1]	229885	1			T23	1		T25	41		T26	16
bins_for_gpio_bits[18]	auto[1]	auto[0]	230165	1			T23	1		T25	41		T26	16
bins_for_gpio_bits[18]	auto[1]	auto[1]	4915905	1			T23	129		T24	22302		T25	590
bins_for_gpio_bits[19]	auto[0]	auto[0]	7554689	1			T23	53		T24	21182		T25	164
bins_for_gpio_bits[19]	auto[0]	auto[1]	229836	1			T25	51		T26	17		T27	1349
bins_for_gpio_bits[19]	auto[1]	auto[0]	230143	1			T25	51		T26	17		T27	1344
bins_for_gpio_bits[19]	auto[1]	auto[1]	4919433	1			T23	158		T24	22015		T25	560
bins_for_gpio_bits[20]	auto[0]	auto[0]	7555927	1			T23	82		T24	20527		T25	210
bins_for_gpio_bits[20]	auto[0]	auto[1]	229756	1			T25	50		T26	16		T27	1352
bins_for_gpio_bits[20]	auto[1]	auto[0]	229996	1			T25	49		T26	16		T27	1349
bins_for_gpio_bits[20]	auto[1]	auto[1]	4918422	1			T23	129		T24	22670		T25	517
bins_for_gpio_bits[21]	auto[0]	auto[0]	7555803	1			T23	167		T24	22642		T25	178
bins_for_gpio_bits[21]	auto[0]	auto[1]	230434	1			T25	40		T26	15		T27	1371
bins_for_gpio_bits[21]	auto[1]	auto[0]	230709	1			T25	40		T26	15		T27	1366
bins_for_gpio_bits[21]	auto[1]	auto[1]	4917155	1			T23	44		T24	20555		T25	568
bins_for_gpio_bits[22]	auto[0]	auto[0]	7556347	1			T23	89		T24	21379		T25	193
bins_for_gpio_bits[22]	auto[0]	auto[1]	230283	1			T25	46		T26	16		T27	1318
bins_for_gpio_bits[22]	auto[1]	auto[0]	230554	1			T25	46		T26	17		T27	1314
bins_for_gpio_bits[22]	auto[1]	auto[1]	4916917	1			T23	122		T24	21818		T25	541
bins_for_gpio_bits[23]	auto[0]	auto[0]	7549740	1			T23	93		T24	20342		T25	206
bins_for_gpio_bits[23]	auto[0]	auto[1]	230731	1			T25	42		T26	15		T27	1365
bins_for_gpio_bits[23]	auto[1]	auto[0]	231011	1			T25	42		T26	15		T27	1359
bins_for_gpio_bits[23]	auto[1]	auto[1]	4922619	1			T23	118		T24	22855		T25	536
bins_for_gpio_bits[24]	auto[0]	auto[0]	7559623	1			T23	101		T24	21090		T25	170
bins_for_gpio_bits[24]	auto[0]	auto[1]	230174	1			T23	1		T25	46		T26	16
bins_for_gpio_bits[24]	auto[1]	auto[0]	230453	1			T23	1		T25	46		T26	16
bins_for_gpio_bits[24]	auto[1]	auto[1]	4913851	1			T23	108		T24	22107		T25	564
bins_for_gpio_bits[25]	auto[0]	auto[0]	7555906	1			T23	71		T24	20685		T25	194
bins_for_gpio_bits[25]	auto[0]	auto[1]	230334	1			T25	38		T26	17		T27	1345
bins_for_gpio_bits[25]	auto[1]	auto[0]	230643	1			T25	38		T26	17		T27	1341
bins_for_gpio_bits[25]	auto[1]	auto[1]	4917218	1			T23	140		T24	22512		T25	556
bins_for_gpio_bits[26]	auto[0]	auto[0]	7551899	1			T23	118		T24	21473		T25	173
bins_for_gpio_bits[26]	auto[0]	auto[1]	230160	1			T25	41		T26	16		T27	1332
bins_for_gpio_bits[26]	auto[1]	auto[0]	230483	1			T25	41		T26	17		T27	1331
bins_for_gpio_bits[26]	auto[1]	auto[1]	4921559	1			T23	93		T24	21724		T25	571
bins_for_gpio_bits[27]	auto[0]	auto[0]	7556305	1			T23	97		T24	20786		T25	206
bins_for_gpio_bits[27]	auto[0]	auto[1]	230277	1			T25	43		T26	12		T27	1314
bins_for_gpio_bits[27]	auto[1]	auto[0]	230569	1			T25	42		T26	13		T27	1313
bins_for_gpio_bits[27]	auto[1]	auto[1]	4916950	1			T23	114		T24	22411		T25	535
bins_for_gpio_bits[28]	auto[0]	auto[0]	7563293	1			T23	117		T24	21767		T25	197
bins_for_gpio_bits[28]	auto[0]	auto[1]	229614	1			T23	1		T25	46		T26	13
bins_for_gpio_bits[28]	auto[1]	auto[0]	229896	1			T23	1		T25	46		T26	14
bins_for_gpio_bits[28]	auto[1]	auto[1]	4911298	1			T23	92		T24	21430		T25	537
bins_for_gpio_bits[29]	auto[0]	auto[0]	7551502	1			T23	58		T24	22299		T25	271
bins_for_gpio_bits[29]	auto[0]	auto[1]	230506	1			T25	51		T26	16		T27	1358
bins_for_gpio_bits[29]	auto[1]	auto[0]	230799	1			T25	51		T26	17		T27	1353
bins_for_gpio_bits[29]	auto[1]	auto[1]	4921294	1			T23	153		T24	20898		T25	453
bins_for_gpio_bits[30]	auto[0]	auto[0]	7566518	1			T23	148		T24	21678		T25	174
bins_for_gpio_bits[30]	auto[0]	auto[1]	230254	1			T23	1		T25	45		T26	17
bins_for_gpio_bits[30]	auto[1]	auto[0]	230519	1			T25	45		T26	17		T27	1384
bins_for_gpio_bits[30]	auto[1]	auto[1]	4906810	1			T23	62		T24	21519		T25	562
bins_for_gpio_bits[31]	auto[0]	auto[0]	7554666	1			T23	138		T24	21038		T25	207
bins_for_gpio_bits[31]	auto[0]	auto[1]	229587	1			T23	1		T25	43		T26	12
bins_for_gpio_bits[31]	auto[1]	auto[0]	229865	1			T23	1		T25	43		T26	12
bins_for_gpio_bits[31]	auto[1]	auto[1]	4919983	1			T23	71		T24	22159		T25	533