Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7578720 |
1 |
|
|
T23 |
101 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5545289 |
1 |
|
|
T23 |
22 |
|
T27 |
27875 |
|
T31 |
216928 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12418972 |
1 |
|
|
T23 |
123 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
705037 |
1 |
|
|
T27 |
2934 |
|
T31 |
27879 |
|
T61 |
308 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7581973 |
1 |
|
|
T23 |
96 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5542036 |
1 |
|
|
T23 |
27 |
|
T27 |
26633 |
|
T31 |
219561 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2419080 |
1 |
|
|
T23 |
24 |
|
T27 |
11910 |
|
T31 |
97187 |
| auto[1] |
auto[0] |
auto[1] |
352150 |
1 |
|
|
T27 |
1423 |
|
T31 |
14254 |
|
T61 |
154 |
| auto[1] |
auto[1] |
auto[0] |
2417919 |
1 |
|
|
T23 |
3 |
|
T27 |
11789 |
|
T31 |
94495 |
| auto[1] |
auto[1] |
auto[1] |
352887 |
1 |
|
|
T27 |
1511 |
|
T31 |
13625 |
|
T61 |
154 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7580276 |
1 |
|
|
T23 |
84 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5543733 |
1 |
|
|
T23 |
39 |
|
T27 |
28985 |
|
T31 |
221133 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12421017 |
1 |
|
|
T23 |
122 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
702992 |
1 |
|
|
T23 |
1 |
|
T27 |
2872 |
|
T31 |
27254 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7584390 |
1 |
|
|
T23 |
107 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5539619 |
1 |
|
|
T23 |
16 |
|
T27 |
26725 |
|
T31 |
215608 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2419459 |
1 |
|
|
T23 |
15 |
|
T27 |
11116 |
|
T31 |
91659 |
| auto[1] |
auto[0] |
auto[1] |
350828 |
1 |
|
|
T23 |
1 |
|
T27 |
1253 |
|
T31 |
13046 |
| auto[1] |
auto[1] |
auto[0] |
2417168 |
1 |
|
|
T27 |
12737 |
|
T31 |
96695 |
|
T61 |
385 |
| auto[1] |
auto[1] |
auto[1] |
352164 |
1 |
|
|
T27 |
1619 |
|
T31 |
14208 |
|
T61 |
99 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7591852 |
1 |
|
|
T23 |
90 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5532157 |
1 |
|
|
T23 |
33 |
|
T27 |
28043 |
|
T31 |
215435 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12415474 |
1 |
|
|
T23 |
123 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
708535 |
1 |
|
|
T27 |
3099 |
|
T31 |
27768 |
|
T61 |
233 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7556746 |
1 |
|
|
T23 |
97 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5567263 |
1 |
|
|
T23 |
26 |
|
T27 |
28104 |
|
T31 |
219192 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2433109 |
1 |
|
|
T23 |
15 |
|
T27 |
12071 |
|
T31 |
96817 |
| auto[1] |
auto[0] |
auto[1] |
354719 |
1 |
|
|
T27 |
1403 |
|
T31 |
14310 |
|
T61 |
107 |
| auto[1] |
auto[1] |
auto[0] |
2425619 |
1 |
|
|
T23 |
11 |
|
T27 |
12934 |
|
T31 |
94607 |
| auto[1] |
auto[1] |
auto[1] |
353816 |
1 |
|
|
T27 |
1696 |
|
T31 |
13458 |
|
T61 |
126 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7589605 |
1 |
|
|
T23 |
81 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5534404 |
1 |
|
|
T23 |
42 |
|
T27 |
27037 |
|
T31 |
222365 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12417421 |
1 |
|
|
T23 |
122 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
706588 |
1 |
|
|
T23 |
1 |
|
T27 |
3091 |
|
T31 |
28721 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7569980 |
1 |
|
|
T23 |
105 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5554029 |
1 |
|
|
T23 |
18 |
|
T27 |
28009 |
|
T31 |
225653 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2434107 |
1 |
|
|
T23 |
7 |
|
T27 |
13077 |
|
T31 |
95799 |
| auto[1] |
auto[0] |
auto[1] |
355626 |
1 |
|
|
T23 |
1 |
|
T27 |
1637 |
|
T31 |
13926 |
| auto[1] |
auto[1] |
auto[0] |
2413334 |
1 |
|
|
T23 |
10 |
|
T27 |
11841 |
|
T31 |
101133 |
| auto[1] |
auto[1] |
auto[1] |
350962 |
1 |
|
|
T27 |
1454 |
|
T31 |
14795 |
|
T61 |
100 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7582774 |
1 |
|
|
T23 |
92 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5541235 |
1 |
|
|
T23 |
31 |
|
T27 |
27779 |
|
T31 |
213147 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12416044 |
1 |
|
|
T23 |
122 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
707965 |
1 |
|
|
T23 |
1 |
|
T27 |
2813 |
|
T31 |
27908 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7559377 |
1 |
|
|
T23 |
103 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5564632 |
1 |
|
|
T23 |
20 |
|
T27 |
26167 |
|
T31 |
218405 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2428358 |
1 |
|
|
T23 |
14 |
|
T27 |
11213 |
|
T31 |
95356 |
| auto[1] |
auto[0] |
auto[1] |
354351 |
1 |
|
|
T23 |
1 |
|
T27 |
1350 |
|
T31 |
13600 |
| auto[1] |
auto[1] |
auto[0] |
2428309 |
1 |
|
|
T23 |
5 |
|
T27 |
12141 |
|
T31 |
95141 |
| auto[1] |
auto[1] |
auto[1] |
353614 |
1 |
|
|
T27 |
1463 |
|
T31 |
14308 |
|
T61 |
102 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7582708 |
1 |
|
|
T23 |
80 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5541301 |
1 |
|
|
T23 |
43 |
|
T27 |
26310 |
|
T31 |
215849 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12414723 |
1 |
|
|
T23 |
122 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
709286 |
1 |
|
|
T23 |
1 |
|
T27 |
3095 |
|
T31 |
27396 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7552768 |
1 |
|
|
T23 |
92 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5571241 |
1 |
|
|
T23 |
31 |
|
T27 |
27450 |
|
T31 |
215426 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2440410 |
1 |
|
|
T23 |
19 |
|
T27 |
12210 |
|
T31 |
94587 |
| auto[1] |
auto[0] |
auto[1] |
355530 |
1 |
|
|
T23 |
1 |
|
T27 |
1583 |
|
T31 |
13682 |
| auto[1] |
auto[1] |
auto[0] |
2421545 |
1 |
|
|
T23 |
11 |
|
T27 |
12145 |
|
T31 |
93443 |
| auto[1] |
auto[1] |
auto[1] |
353756 |
1 |
|
|
T27 |
1512 |
|
T31 |
13714 |
|
T61 |
136 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7583693 |
1 |
|
|
T23 |
79 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5540316 |
1 |
|
|
T23 |
44 |
|
T27 |
27729 |
|
T31 |
224710 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12424990 |
1 |
|
|
T23 |
122 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
699019 |
1 |
|
|
T23 |
1 |
|
T27 |
2991 |
|
T31 |
26716 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7614328 |
1 |
|
|
T23 |
100 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5509681 |
1 |
|
|
T23 |
23 |
|
T27 |
27683 |
|
T31 |
212317 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2403719 |
1 |
|
|
T23 |
15 |
|
T27 |
12057 |
|
T31 |
89813 |
| auto[1] |
auto[0] |
auto[1] |
349301 |
1 |
|
|
T27 |
1459 |
|
T31 |
12989 |
|
T61 |
100 |
| auto[1] |
auto[1] |
auto[0] |
2406943 |
1 |
|
|
T23 |
7 |
|
T27 |
12635 |
|
T31 |
95788 |
| auto[1] |
auto[1] |
auto[1] |
349718 |
1 |
|
|
T23 |
1 |
|
T27 |
1532 |
|
T31 |
13727 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7585110 |
1 |
|
|
T23 |
98 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5538899 |
1 |
|
|
T23 |
25 |
|
T27 |
26819 |
|
T31 |
215582 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12416446 |
1 |
|
|
T23 |
121 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
707563 |
1 |
|
|
T23 |
2 |
|
T27 |
3098 |
|
T31 |
28068 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7570244 |
1 |
|
|
T23 |
79 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5553765 |
1 |
|
|
T23 |
44 |
|
T27 |
27978 |
|
T31 |
220017 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2432611 |
1 |
|
|
T23 |
32 |
|
T27 |
12255 |
|
T31 |
98713 |
| auto[1] |
auto[0] |
auto[1] |
355509 |
1 |
|
|
T23 |
2 |
|
T27 |
1572 |
|
T31 |
14453 |
| auto[1] |
auto[1] |
auto[0] |
2413591 |
1 |
|
|
T23 |
10 |
|
T27 |
12625 |
|
T31 |
93236 |
| auto[1] |
auto[1] |
auto[1] |
352054 |
1 |
|
|
T27 |
1526 |
|
T31 |
13615 |
|
T61 |
118 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7585948 |
1 |
|
|
T23 |
85 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5538061 |
1 |
|
|
T23 |
38 |
|
T27 |
26825 |
|
T31 |
218723 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12420939 |
1 |
|
|
T23 |
122 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
703070 |
1 |
|
|
T23 |
1 |
|
T27 |
2951 |
|
T31 |
28012 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7590839 |
1 |
|
|
T23 |
89 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5533170 |
1 |
|
|
T23 |
34 |
|
T27 |
26644 |
|
T31 |
221068 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2425823 |
1 |
|
|
T23 |
24 |
|
T27 |
11953 |
|
T31 |
97852 |
| auto[1] |
auto[0] |
auto[1] |
353877 |
1 |
|
|
T27 |
1458 |
|
T31 |
14220 |
|
T61 |
155 |
| auto[1] |
auto[1] |
auto[0] |
2404277 |
1 |
|
|
T23 |
9 |
|
T27 |
11740 |
|
T31 |
95204 |
| auto[1] |
auto[1] |
auto[1] |
349193 |
1 |
|
|
T23 |
1 |
|
T27 |
1493 |
|
T31 |
13792 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7581687 |
1 |
|
|
T23 |
74 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5542322 |
1 |
|
|
T23 |
49 |
|
T27 |
27647 |
|
T31 |
227443 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12425642 |
1 |
|
|
T23 |
123 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
698367 |
1 |
|
|
T27 |
3203 |
|
T31 |
26952 |
|
T61 |
341 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7614632 |
1 |
|
|
T23 |
102 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5509377 |
1 |
|
|
T23 |
21 |
|
T27 |
28507 |
|
T31 |
212937 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2409867 |
1 |
|
|
T23 |
5 |
|
T27 |
12569 |
|
T31 |
92141 |
| auto[1] |
auto[0] |
auto[1] |
349796 |
1 |
|
|
T27 |
1570 |
|
T31 |
13528 |
|
T61 |
159 |
| auto[1] |
auto[1] |
auto[0] |
2401143 |
1 |
|
|
T23 |
16 |
|
T27 |
12735 |
|
T31 |
93844 |
| auto[1] |
auto[1] |
auto[1] |
348571 |
1 |
|
|
T27 |
1633 |
|
T31 |
13424 |
|
T61 |
182 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7576921 |
1 |
|
|
T23 |
98 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5547088 |
1 |
|
|
T23 |
25 |
|
T27 |
26696 |
|
T31 |
211602 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12424323 |
1 |
|
|
T23 |
123 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
699686 |
1 |
|
|
T27 |
2790 |
|
T31 |
28678 |
|
T61 |
261 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7606737 |
1 |
|
|
T23 |
103 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5517272 |
1 |
|
|
T23 |
20 |
|
T27 |
26054 |
|
T31 |
225062 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2411091 |
1 |
|
|
T23 |
16 |
|
T27 |
11327 |
|
T31 |
103933 |
| auto[1] |
auto[0] |
auto[1] |
351226 |
1 |
|
|
T27 |
1394 |
|
T31 |
15549 |
|
T61 |
144 |
| auto[1] |
auto[1] |
auto[0] |
2406495 |
1 |
|
|
T23 |
4 |
|
T27 |
11937 |
|
T31 |
92451 |
| auto[1] |
auto[1] |
auto[1] |
348460 |
1 |
|
|
T27 |
1396 |
|
T31 |
13129 |
|
T61 |
117 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7587009 |
1 |
|
|
T23 |
81 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5537000 |
1 |
|
|
T23 |
42 |
|
T27 |
27157 |
|
T31 |
220335 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12418273 |
1 |
|
|
T23 |
123 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
705736 |
1 |
|
|
T27 |
2709 |
|
T31 |
28018 |
|
T61 |
255 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7566712 |
1 |
|
|
T23 |
102 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5557297 |
1 |
|
|
T23 |
21 |
|
T27 |
25053 |
|
T31 |
220013 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2426260 |
1 |
|
|
T23 |
12 |
|
T27 |
11584 |
|
T31 |
94229 |
| auto[1] |
auto[0] |
auto[1] |
352660 |
1 |
|
|
T27 |
1346 |
|
T31 |
13815 |
|
T61 |
177 |
| auto[1] |
auto[1] |
auto[0] |
2425301 |
1 |
|
|
T23 |
9 |
|
T27 |
10760 |
|
T31 |
97766 |
| auto[1] |
auto[1] |
auto[1] |
353076 |
1 |
|
|
T27 |
1363 |
|
T31 |
14203 |
|
T61 |
78 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7621096 |
1 |
|
|
T23 |
80 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5502913 |
1 |
|
|
T23 |
43 |
|
T27 |
26553 |
|
T31 |
214571 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12418583 |
1 |
|
|
T23 |
121 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
705426 |
1 |
|
|
T23 |
2 |
|
T27 |
3028 |
|
T31 |
27459 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7576383 |
1 |
|
|
T23 |
83 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5547626 |
1 |
|
|
T23 |
40 |
|
T27 |
27045 |
|
T31 |
217564 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2444818 |
1 |
|
|
T23 |
17 |
|
T27 |
12058 |
|
T31 |
96620 |
| auto[1] |
auto[0] |
auto[1] |
356565 |
1 |
|
|
T23 |
1 |
|
T27 |
1461 |
|
T31 |
14013 |
| auto[1] |
auto[1] |
auto[0] |
2397382 |
1 |
|
|
T23 |
21 |
|
T27 |
11959 |
|
T31 |
93485 |
| auto[1] |
auto[1] |
auto[1] |
348861 |
1 |
|
|
T23 |
1 |
|
T27 |
1567 |
|
T31 |
13446 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7607239 |
1 |
|
|
T23 |
70 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5516770 |
1 |
|
|
T23 |
53 |
|
T27 |
26465 |
|
T31 |
224542 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12418040 |
1 |
|
|
T23 |
122 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
705969 |
1 |
|
|
T23 |
1 |
|
T27 |
3062 |
|
T31 |
27875 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7563853 |
1 |
|
|
T23 |
93 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5560156 |
1 |
|
|
T23 |
30 |
|
T27 |
27655 |
|
T31 |
217788 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2437660 |
1 |
|
|
T23 |
14 |
|
T27 |
11970 |
|
T31 |
92900 |
| auto[1] |
auto[0] |
auto[1] |
354946 |
1 |
|
|
T23 |
1 |
|
T27 |
1463 |
|
T31 |
13407 |
| auto[1] |
auto[1] |
auto[0] |
2416527 |
1 |
|
|
T23 |
15 |
|
T27 |
12623 |
|
T31 |
97013 |
| auto[1] |
auto[1] |
auto[1] |
351023 |
1 |
|
|
T27 |
1599 |
|
T31 |
14468 |
|
T61 |
139 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7573695 |
1 |
|
|
T23 |
70 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5550314 |
1 |
|
|
T23 |
53 |
|
T27 |
25793 |
|
T31 |
218997 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12421091 |
1 |
|
|
T23 |
121 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
702918 |
1 |
|
|
T23 |
2 |
|
T27 |
2945 |
|
T31 |
28347 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7593453 |
1 |
|
|
T23 |
90 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5530556 |
1 |
|
|
T23 |
33 |
|
T27 |
26927 |
|
T31 |
221186 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2414629 |
1 |
|
|
T23 |
18 |
|
T27 |
12680 |
|
T31 |
97170 |
| auto[1] |
auto[0] |
auto[1] |
351715 |
1 |
|
|
T23 |
1 |
|
T27 |
1605 |
|
T31 |
14337 |
| auto[1] |
auto[1] |
auto[0] |
2413009 |
1 |
|
|
T23 |
13 |
|
T27 |
11302 |
|
T31 |
95669 |
| auto[1] |
auto[1] |
auto[1] |
351203 |
1 |
|
|
T23 |
1 |
|
T27 |
1340 |
|
T31 |
14010 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7609247 |
1 |
|
|
T23 |
74 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5514762 |
1 |
|
|
T23 |
49 |
|
T27 |
27241 |
|
T31 |
215574 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12420466 |
1 |
|
|
T23 |
123 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
703543 |
1 |
|
|
T27 |
3107 |
|
T31 |
28551 |
|
T61 |
239 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7591635 |
1 |
|
|
T23 |
98 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5532374 |
1 |
|
|
T23 |
25 |
|
T27 |
27438 |
|
T31 |
223484 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2423559 |
1 |
|
|
T23 |
10 |
|
T27 |
12269 |
|
T31 |
98182 |
| auto[1] |
auto[0] |
auto[1] |
352243 |
1 |
|
|
T27 |
1529 |
|
T31 |
14360 |
|
T61 |
175 |
| auto[1] |
auto[1] |
auto[0] |
2405272 |
1 |
|
|
T23 |
15 |
|
T27 |
12062 |
|
T31 |
96751 |
| auto[1] |
auto[1] |
auto[1] |
351300 |
1 |
|
|
T27 |
1578 |
|
T31 |
14191 |
|
T61 |
64 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7574504 |
1 |
|
|
T23 |
78 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5549505 |
1 |
|
|
T23 |
45 |
|
T27 |
27540 |
|
T31 |
216793 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12420508 |
1 |
|
|
T23 |
122 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
703501 |
1 |
|
|
T23 |
1 |
|
T27 |
3005 |
|
T31 |
27547 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7586910 |
1 |
|
|
T23 |
97 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5537099 |
1 |
|
|
T23 |
26 |
|
T27 |
27451 |
|
T31 |
217233 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2420834 |
1 |
|
|
T23 |
12 |
|
T27 |
11895 |
|
T31 |
97023 |
| auto[1] |
auto[0] |
auto[1] |
353039 |
1 |
|
|
T27 |
1439 |
|
T31 |
14284 |
|
T61 |
118 |
| auto[1] |
auto[1] |
auto[0] |
2412764 |
1 |
|
|
T23 |
13 |
|
T27 |
12551 |
|
T31 |
92663 |
| auto[1] |
auto[1] |
auto[1] |
350462 |
1 |
|
|
T23 |
1 |
|
T27 |
1566 |
|
T31 |
13263 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7587846 |
1 |
|
|
T23 |
68 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5536163 |
1 |
|
|
T23 |
55 |
|
T27 |
27235 |
|
T31 |
221571 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12417347 |
1 |
|
|
T23 |
122 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
706662 |
1 |
|
|
T23 |
1 |
|
T27 |
2939 |
|
T31 |
27906 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7572177 |
1 |
|
|
T23 |
103 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5551832 |
1 |
|
|
T23 |
20 |
|
T27 |
26495 |
|
T31 |
220432 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2429963 |
1 |
|
|
T23 |
11 |
|
T27 |
11744 |
|
T31 |
93682 |
| auto[1] |
auto[0] |
auto[1] |
354003 |
1 |
|
|
T27 |
1450 |
|
T31 |
13493 |
|
T61 |
170 |
| auto[1] |
auto[1] |
auto[0] |
2415207 |
1 |
|
|
T23 |
8 |
|
T27 |
11812 |
|
T31 |
98844 |
| auto[1] |
auto[1] |
auto[1] |
352659 |
1 |
|
|
T23 |
1 |
|
T27 |
1489 |
|
T31 |
14413 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7566800 |
1 |
|
|
T23 |
90 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5557209 |
1 |
|
|
T23 |
33 |
|
T27 |
27431 |
|
T31 |
222703 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12426677 |
1 |
|
|
T23 |
123 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
697332 |
1 |
|
|
T27 |
2869 |
|
T31 |
28353 |
|
T61 |
257 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7632282 |
1 |
|
|
T23 |
106 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5491727 |
1 |
|
|
T23 |
17 |
|
T27 |
26328 |
|
T31 |
221569 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2398446 |
1 |
|
|
T23 |
10 |
|
T27 |
11221 |
|
T31 |
93158 |
| auto[1] |
auto[0] |
auto[1] |
349175 |
1 |
|
|
T27 |
1333 |
|
T31 |
13598 |
|
T61 |
96 |
| auto[1] |
auto[1] |
auto[0] |
2395949 |
1 |
|
|
T23 |
7 |
|
T27 |
12238 |
|
T31 |
100058 |
| auto[1] |
auto[1] |
auto[1] |
348157 |
1 |
|
|
T27 |
1536 |
|
T31 |
14755 |
|
T61 |
161 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7590170 |
1 |
|
|
T23 |
91 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5533839 |
1 |
|
|
T23 |
32 |
|
T27 |
26378 |
|
T31 |
216399 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12418510 |
1 |
|
|
T23 |
122 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
705499 |
1 |
|
|
T23 |
1 |
|
T27 |
3030 |
|
T31 |
28358 |