Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7604530 |
1 |
|
|
T23 |
74 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5519479 |
1 |
|
|
T23 |
49 |
|
T27 |
26820 |
|
T31 |
224249 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12415583 |
1 |
|
|
T23 |
122 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
708426 |
1 |
|
|
T23 |
1 |
|
T27 |
2957 |
|
T31 |
28607 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7561560 |
1 |
|
|
T23 |
77 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5562449 |
1 |
|
|
T23 |
46 |
|
T27 |
26585 |
|
T31 |
223091 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2442666 |
1 |
|
|
T23 |
22 |
|
T27 |
11806 |
|
T31 |
99059 |
| auto[1] |
auto[0] |
auto[1] |
356546 |
1 |
|
|
T23 |
1 |
|
T27 |
1442 |
|
T31 |
14442 |
| auto[1] |
auto[1] |
auto[0] |
2411357 |
1 |
|
|
T23 |
23 |
|
T27 |
11822 |
|
T31 |
95425 |
| auto[1] |
auto[1] |
auto[1] |
351880 |
1 |
|
|
T27 |
1515 |
|
T31 |
14165 |
|
T61 |
150 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |