Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7597564 |
1 |
|
|
T23 |
91 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5526445 |
1 |
|
|
T23 |
32 |
|
T27 |
27580 |
|
T31 |
220235 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12412992 |
1 |
|
|
T23 |
121 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
711017 |
1 |
|
|
T23 |
2 |
|
T27 |
2766 |
|
T31 |
27321 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7537324 |
1 |
|
|
T23 |
97 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5586685 |
1 |
|
|
T23 |
26 |
|
T27 |
25426 |
|
T31 |
215163 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2447409 |
1 |
|
|
T23 |
17 |
|
T27 |
11401 |
|
T31 |
92613 |
| auto[1] |
auto[0] |
auto[1] |
357200 |
1 |
|
|
T23 |
1 |
|
T27 |
1374 |
|
T31 |
13314 |
| auto[1] |
auto[1] |
auto[0] |
2428259 |
1 |
|
|
T23 |
7 |
|
T27 |
11259 |
|
T31 |
95229 |
| auto[1] |
auto[1] |
auto[1] |
353817 |
1 |
|
|
T23 |
1 |
|
T27 |
1392 |
|
T31 |
14007 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |