Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7579183 |
1 |
|
|
T23 |
82 |
|
T24 |
43197 |
|
T25 |
458 |
auto[1] |
5544826 |
1 |
|
|
T23 |
41 |
|
T27 |
28174 |
|
T31 |
223520 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12418832 |
1 |
|
|
T23 |
122 |
|
T24 |
43197 |
|
T25 |
458 |
auto[1] |
705177 |
1 |
|
|
T23 |
1 |
|
T27 |
3011 |
|
T31 |
27670 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7574664 |
1 |
|
|
T23 |
95 |
|
T24 |
43197 |
|
T25 |
458 |
auto[1] |
5549345 |
1 |
|
|
T23 |
28 |
|
T27 |
27086 |
|
T31 |
218970 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2418789 |
1 |
|
|
T23 |
16 |
|
T27 |
11735 |
|
T31 |
92862 |
auto[1] |
auto[0] |
auto[1] |
353260 |
1 |
|
|
T27 |
1436 |
|
T31 |
13217 |
|
T61 |
139 |
auto[1] |
auto[1] |
auto[0] |
2425379 |
1 |
|
|
T23 |
11 |
|
T27 |
12340 |
|
T31 |
98438 |
auto[1] |
auto[1] |
auto[1] |
351917 |
1 |
|
|
T23 |
1 |
|
T27 |
1575 |
|
T31 |
14453 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |