Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7552872 |
1 |
|
|
T23 |
89 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5571137 |
1 |
|
|
T23 |
34 |
|
T27 |
28298 |
|
T31 |
220978 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12419956 |
1 |
|
|
T23 |
121 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
704053 |
1 |
|
|
T23 |
2 |
|
T27 |
3035 |
|
T31 |
26176 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7582528 |
1 |
|
|
T23 |
89 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5541481 |
1 |
|
|
T23 |
34 |
|
T27 |
27117 |
|
T31 |
209493 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2404591 |
1 |
|
|
T23 |
18 |
|
T27 |
11402 |
|
T31 |
90775 |
| auto[1] |
auto[0] |
auto[1] |
349039 |
1 |
|
|
T23 |
1 |
|
T27 |
1304 |
|
T31 |
12826 |
| auto[1] |
auto[1] |
auto[0] |
2432837 |
1 |
|
|
T23 |
14 |
|
T27 |
12680 |
|
T31 |
92542 |
| auto[1] |
auto[1] |
auto[1] |
355014 |
1 |
|
|
T23 |
1 |
|
T27 |
1731 |
|
T31 |
13350 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |