Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7564683 |
1 |
|
|
T23 |
91 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5559326 |
1 |
|
|
T23 |
32 |
|
T27 |
26306 |
|
T31 |
223546 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12421046 |
1 |
|
|
T23 |
122 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
702963 |
1 |
|
|
T23 |
1 |
|
T27 |
2913 |
|
T31 |
27808 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7591778 |
1 |
|
|
T23 |
86 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5532231 |
1 |
|
|
T23 |
37 |
|
T27 |
26674 |
|
T31 |
219824 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2409431 |
1 |
|
|
T23 |
20 |
|
T27 |
12562 |
|
T31 |
95235 |
| auto[1] |
auto[0] |
auto[1] |
350189 |
1 |
|
|
T23 |
1 |
|
T27 |
1536 |
|
T31 |
13983 |
| auto[1] |
auto[1] |
auto[0] |
2419837 |
1 |
|
|
T23 |
16 |
|
T27 |
11199 |
|
T31 |
96781 |
| auto[1] |
auto[1] |
auto[1] |
352774 |
1 |
|
|
T27 |
1377 |
|
T31 |
13825 |
|
T61 |
132 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |