Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7578720 |
1 |
|
|
T23 |
101 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5545289 |
1 |
|
|
T23 |
22 |
|
T27 |
27875 |
|
T31 |
216928 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10856944 |
1 |
|
|
T23 |
121 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
2267065 |
1 |
|
|
T23 |
2 |
|
T27 |
16321 |
|
T31 |
82704 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7579842 |
1 |
|
|
T23 |
88 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5544167 |
1 |
|
|
T23 |
35 |
|
T27 |
25690 |
|
T31 |
216814 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1642615 |
1 |
|
|
T23 |
27 |
|
T27 |
4265 |
|
T31 |
66320 |
| auto[1] |
auto[0] |
auto[1] |
1140006 |
1 |
|
|
T23 |
1 |
|
T27 |
7674 |
|
T31 |
40847 |
| auto[1] |
auto[1] |
auto[0] |
1634487 |
1 |
|
|
T23 |
6 |
|
T27 |
5104 |
|
T31 |
67790 |
| auto[1] |
auto[1] |
auto[1] |
1127059 |
1 |
|
|
T23 |
1 |
|
T27 |
8647 |
|
T31 |
41857 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |