Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7580276 |
1 |
|
|
T23 |
84 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5543733 |
1 |
|
|
T23 |
39 |
|
T27 |
28985 |
|
T31 |
221133 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10856671 |
1 |
|
|
T23 |
101 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
2267338 |
1 |
|
|
T23 |
22 |
|
T27 |
17634 |
|
T31 |
82086 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7564891 |
1 |
|
|
T23 |
88 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5559118 |
1 |
|
|
T23 |
35 |
|
T27 |
27897 |
|
T31 |
219648 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1648649 |
1 |
|
|
T23 |
9 |
|
T27 |
4628 |
|
T31 |
67526 |
| auto[1] |
auto[0] |
auto[1] |
1139574 |
1 |
|
|
T23 |
14 |
|
T27 |
8398 |
|
T31 |
40260 |
| auto[1] |
auto[1] |
auto[0] |
1643131 |
1 |
|
|
T23 |
4 |
|
T27 |
5635 |
|
T31 |
70036 |
| auto[1] |
auto[1] |
auto[1] |
1127764 |
1 |
|
|
T23 |
8 |
|
T27 |
9236 |
|
T31 |
41826 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |