Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7591852 |
1 |
|
|
T23 |
90 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5532157 |
1 |
|
|
T23 |
33 |
|
T27 |
28043 |
|
T31 |
215435 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10860766 |
1 |
|
|
T23 |
107 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
2263243 |
1 |
|
|
T23 |
16 |
|
T27 |
16101 |
|
T31 |
81307 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7586915 |
1 |
|
|
T23 |
97 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5537094 |
1 |
|
|
T23 |
26 |
|
T27 |
24554 |
|
T31 |
213394 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1641354 |
1 |
|
|
T23 |
10 |
|
T27 |
3902 |
|
T31 |
65632 |
| auto[1] |
auto[0] |
auto[1] |
1134154 |
1 |
|
|
T23 |
14 |
|
T27 |
7875 |
|
T31 |
40766 |
| auto[1] |
auto[1] |
auto[0] |
1632497 |
1 |
|
|
T27 |
4551 |
|
T31 |
66455 |
|
T61 |
441 |
| auto[1] |
auto[1] |
auto[1] |
1129089 |
1 |
|
|
T23 |
2 |
|
T27 |
8226 |
|
T31 |
40541 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |