Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7582774 |
1 |
|
|
T23 |
92 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5541235 |
1 |
|
|
T23 |
31 |
|
T27 |
27779 |
|
T31 |
213147 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10861124 |
1 |
|
|
T23 |
109 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
2262885 |
1 |
|
|
T23 |
14 |
|
T27 |
17118 |
|
T31 |
82066 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7584016 |
1 |
|
|
T23 |
100 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5539993 |
1 |
|
|
T23 |
23 |
|
T27 |
26492 |
|
T31 |
215611 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1632369 |
1 |
|
|
T23 |
9 |
|
T27 |
4568 |
|
T31 |
69023 |
| auto[1] |
auto[0] |
auto[1] |
1128329 |
1 |
|
|
T23 |
10 |
|
T27 |
8143 |
|
T31 |
42456 |
| auto[1] |
auto[1] |
auto[0] |
1644739 |
1 |
|
|
T27 |
4806 |
|
T31 |
64522 |
|
T61 |
393 |
| auto[1] |
auto[1] |
auto[1] |
1134556 |
1 |
|
|
T23 |
4 |
|
T27 |
8975 |
|
T31 |
39610 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |