Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7578389 |
1 |
|
|
T23 |
96 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5545620 |
1 |
|
|
T23 |
27 |
|
T27 |
27978 |
|
T31 |
220955 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2410033 |
1 |
|
|
T23 |
26 |
|
T27 |
13449 |
|
T31 |
96210 |
| auto[1] |
auto[0] |
auto[1] |
351799 |
1 |
|
|
T23 |
1 |
|
T27 |
1655 |
|
T31 |
14060 |
| auto[1] |
auto[1] |
auto[0] |
2430088 |
1 |
|
|
T27 |
11499 |
|
T31 |
96387 |
|
T61 |
618 |
| auto[1] |
auto[1] |
auto[1] |
353700 |
1 |
|
|
T27 |
1375 |
|
T31 |
14298 |
|
T61 |
164 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |