Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7583693 |
1 |
|
|
T23 |
79 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5540316 |
1 |
|
|
T23 |
44 |
|
T27 |
27729 |
|
T31 |
224710 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10861709 |
1 |
|
|
T23 |
106 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
2262300 |
1 |
|
|
T23 |
17 |
|
T27 |
17041 |
|
T31 |
82701 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7605210 |
1 |
|
|
T23 |
102 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5518799 |
1 |
|
|
T23 |
21 |
|
T27 |
26777 |
|
T31 |
218019 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1625614 |
1 |
|
|
T27 |
4589 |
|
T31 |
65680 |
|
T61 |
231 |
| auto[1] |
auto[0] |
auto[1] |
1127056 |
1 |
|
|
T23 |
6 |
|
T27 |
8414 |
|
T31 |
40021 |
| auto[1] |
auto[1] |
auto[0] |
1630885 |
1 |
|
|
T23 |
4 |
|
T27 |
5147 |
|
T31 |
69638 |
| auto[1] |
auto[1] |
auto[1] |
1135244 |
1 |
|
|
T23 |
11 |
|
T27 |
8627 |
|
T31 |
42680 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |