Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7585110 |
1 |
|
|
T23 |
98 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5538899 |
1 |
|
|
T23 |
25 |
|
T27 |
26819 |
|
T31 |
215582 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10854603 |
1 |
|
|
T23 |
116 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
2269406 |
1 |
|
|
T23 |
7 |
|
T27 |
16557 |
|
T31 |
82506 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7562655 |
1 |
|
|
T23 |
102 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5561354 |
1 |
|
|
T23 |
21 |
|
T27 |
25990 |
|
T31 |
220958 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1654870 |
1 |
|
|
T23 |
10 |
|
T27 |
4903 |
|
T31 |
71465 |
| auto[1] |
auto[0] |
auto[1] |
1138465 |
1 |
|
|
T23 |
5 |
|
T27 |
8641 |
|
T31 |
41724 |
| auto[1] |
auto[1] |
auto[0] |
1637078 |
1 |
|
|
T23 |
4 |
|
T27 |
4530 |
|
T31 |
66987 |
| auto[1] |
auto[1] |
auto[1] |
1130941 |
1 |
|
|
T23 |
2 |
|
T27 |
7916 |
|
T31 |
40782 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |