Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7587009 |
1 |
|
|
T23 |
81 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5537000 |
1 |
|
|
T23 |
42 |
|
T27 |
27157 |
|
T31 |
220335 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10861889 |
1 |
|
|
T23 |
106 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
2262120 |
1 |
|
|
T23 |
17 |
|
T27 |
17730 |
|
T31 |
81969 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7587974 |
1 |
|
|
T23 |
104 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5536035 |
1 |
|
|
T23 |
19 |
|
T27 |
28043 |
|
T31 |
216046 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1628202 |
1 |
|
|
T27 |
5022 |
|
T31 |
64445 |
|
T61 |
392 |
| auto[1] |
auto[0] |
auto[1] |
1130468 |
1 |
|
|
T23 |
7 |
|
T27 |
8774 |
|
T31 |
40215 |
| auto[1] |
auto[1] |
auto[0] |
1645713 |
1 |
|
|
T23 |
2 |
|
T27 |
5291 |
|
T31 |
69632 |
| auto[1] |
auto[1] |
auto[1] |
1131652 |
1 |
|
|
T23 |
10 |
|
T27 |
8956 |
|
T31 |
41754 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |