Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7621096 |
1 |
|
|
T23 |
80 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5502913 |
1 |
|
|
T23 |
43 |
|
T27 |
26553 |
|
T31 |
214571 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10860138 |
1 |
|
|
T23 |
116 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
2263871 |
1 |
|
|
T23 |
7 |
|
T27 |
17802 |
|
T31 |
81937 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7593207 |
1 |
|
|
T23 |
101 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5530802 |
1 |
|
|
T23 |
22 |
|
T27 |
27654 |
|
T31 |
215526 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1642264 |
1 |
|
|
T23 |
8 |
|
T27 |
4837 |
|
T31 |
68264 |
| auto[1] |
auto[0] |
auto[1] |
1136051 |
1 |
|
|
T23 |
7 |
|
T27 |
8764 |
|
T31 |
41245 |
| auto[1] |
auto[1] |
auto[0] |
1624667 |
1 |
|
|
T23 |
7 |
|
T27 |
5015 |
|
T31 |
65325 |
| auto[1] |
auto[1] |
auto[1] |
1127820 |
1 |
|
|
T27 |
9038 |
|
T31 |
40692 |
|
T61 |
290 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |