Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7573695 |
1 |
|
|
T23 |
70 |
|
T24 |
43197 |
|
T25 |
458 |
auto[1] |
5550314 |
1 |
|
|
T23 |
53 |
|
T27 |
25793 |
|
T31 |
218997 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10852795 |
1 |
|
|
T23 |
116 |
|
T24 |
43197 |
|
T25 |
458 |
auto[1] |
2271214 |
1 |
|
|
T23 |
7 |
|
T27 |
16907 |
|
T31 |
82722 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7570111 |
1 |
|
|
T23 |
96 |
|
T24 |
43197 |
|
T25 |
458 |
auto[1] |
5553898 |
1 |
|
|
T23 |
27 |
|
T27 |
26663 |
|
T31 |
220672 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1642753 |
1 |
|
|
T23 |
6 |
|
T27 |
4857 |
|
T31 |
69960 |
auto[1] |
auto[0] |
auto[1] |
1136865 |
1 |
|
|
T23 |
3 |
|
T27 |
8873 |
|
T31 |
41369 |
auto[1] |
auto[1] |
auto[0] |
1639931 |
1 |
|
|
T23 |
14 |
|
T27 |
4899 |
|
T31 |
67990 |
auto[1] |
auto[1] |
auto[1] |
1134349 |
1 |
|
|
T23 |
4 |
|
T27 |
8034 |
|
T31 |
41353 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |