Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7609247 |
1 |
|
|
T23 |
74 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5514762 |
1 |
|
|
T23 |
49 |
|
T27 |
27241 |
|
T31 |
215574 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10858188 |
1 |
|
|
T23 |
102 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
2265821 |
1 |
|
|
T23 |
21 |
|
T27 |
16939 |
|
T31 |
81518 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7578193 |
1 |
|
|
T23 |
100 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5545816 |
1 |
|
|
T23 |
23 |
|
T27 |
26382 |
|
T31 |
214792 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1655501 |
1 |
|
|
T27 |
4494 |
|
T31 |
69135 |
|
T61 |
380 |
| auto[1] |
auto[0] |
auto[1] |
1138580 |
1 |
|
|
T23 |
9 |
|
T27 |
8499 |
|
T31 |
42008 |
| auto[1] |
auto[1] |
auto[0] |
1624494 |
1 |
|
|
T23 |
2 |
|
T27 |
4949 |
|
T31 |
64139 |
| auto[1] |
auto[1] |
auto[1] |
1127241 |
1 |
|
|
T23 |
12 |
|
T27 |
8440 |
|
T31 |
39510 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |