Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7587846 |
1 |
|
|
T23 |
68 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5536163 |
1 |
|
|
T23 |
55 |
|
T27 |
27235 |
|
T31 |
221571 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10860301 |
1 |
|
|
T23 |
112 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
2263708 |
1 |
|
|
T23 |
11 |
|
T27 |
16649 |
|
T31 |
83203 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7576763 |
1 |
|
|
T23 |
91 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5547246 |
1 |
|
|
T23 |
32 |
|
T27 |
26558 |
|
T31 |
221821 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1646227 |
1 |
|
|
T23 |
7 |
|
T27 |
4802 |
|
T31 |
68336 |
| auto[1] |
auto[0] |
auto[1] |
1138823 |
1 |
|
|
T23 |
2 |
|
T27 |
8244 |
|
T31 |
41429 |
| auto[1] |
auto[1] |
auto[0] |
1637311 |
1 |
|
|
T23 |
14 |
|
T27 |
5107 |
|
T31 |
70282 |
| auto[1] |
auto[1] |
auto[1] |
1124885 |
1 |
|
|
T23 |
9 |
|
T27 |
8405 |
|
T31 |
41774 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |