Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7605126 |
1 |
|
|
T23 |
76 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5518883 |
1 |
|
|
T23 |
47 |
|
T27 |
28671 |
|
T31 |
222280 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12416129 |
1 |
|
|
T23 |
123 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
707880 |
1 |
|
|
T27 |
2626 |
|
T31 |
28743 |
|
T61 |
257 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7563632 |
1 |
|
|
T23 |
81 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5560377 |
1 |
|
|
T23 |
42 |
|
T27 |
24628 |
|
T31 |
222851 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2454745 |
1 |
|
|
T23 |
15 |
|
T27 |
10679 |
|
T31 |
96699 |
| auto[1] |
auto[0] |
auto[1] |
357829 |
1 |
|
|
T27 |
1168 |
|
T31 |
14144 |
|
T61 |
143 |
| auto[1] |
auto[1] |
auto[0] |
2397752 |
1 |
|
|
T23 |
27 |
|
T27 |
11323 |
|
T31 |
97409 |
| auto[1] |
auto[1] |
auto[1] |
350051 |
1 |
|
|
T27 |
1458 |
|
T31 |
14599 |
|
T61 |
114 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |