Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7555341 |
1 |
|
|
T23 |
87 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5568668 |
1 |
|
|
T23 |
36 |
|
T27 |
27232 |
|
T31 |
218704 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12421843 |
1 |
|
|
T23 |
122 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
702166 |
1 |
|
|
T23 |
1 |
|
T27 |
2944 |
|
T31 |
27674 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7598464 |
1 |
|
|
T23 |
104 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5525545 |
1 |
|
|
T23 |
19 |
|
T27 |
26458 |
|
T31 |
218388 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2411747 |
1 |
|
|
T23 |
18 |
|
T27 |
11507 |
|
T31 |
94856 |
| auto[1] |
auto[0] |
auto[1] |
350863 |
1 |
|
|
T23 |
1 |
|
T27 |
1455 |
|
T31 |
13826 |
| auto[1] |
auto[1] |
auto[0] |
2411632 |
1 |
|
|
T27 |
12007 |
|
T31 |
95858 |
|
T61 |
432 |
| auto[1] |
auto[1] |
auto[1] |
351303 |
1 |
|
|
T27 |
1489 |
|
T31 |
13848 |
|
T61 |
113 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |