Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7592252 |
1 |
|
|
T23 |
80 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5531757 |
1 |
|
|
T23 |
43 |
|
T27 |
26675 |
|
T31 |
222618 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12418236 |
1 |
|
|
T23 |
122 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
705773 |
1 |
|
|
T23 |
1 |
|
T27 |
2819 |
|
T31 |
28141 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7572406 |
1 |
|
|
T23 |
96 |
|
T24 |
43197 |
|
T25 |
458 |
| auto[1] |
5551603 |
1 |
|
|
T23 |
27 |
|
T27 |
26249 |
|
T31 |
221623 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2434975 |
1 |
|
|
T23 |
12 |
|
T27 |
12021 |
|
T31 |
94822 |
| auto[1] |
auto[0] |
auto[1] |
354948 |
1 |
|
|
T27 |
1478 |
|
T31 |
13846 |
|
T61 |
124 |
| auto[1] |
auto[1] |
auto[0] |
2410855 |
1 |
|
|
T23 |
14 |
|
T27 |
11409 |
|
T31 |
98660 |
| auto[1] |
auto[1] |
auto[1] |
350825 |
1 |
|
|
T23 |
1 |
|
T27 |
1341 |
|
T31 |
14295 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |