Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 940
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T760 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.783795412 Aug 10 05:08:56 PM PDT 24 Aug 10 05:08:59 PM PDT 24 1193234585 ps
T103 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1249981038 Aug 10 05:08:52 PM PDT 24 Aug 10 05:08:53 PM PDT 24 123379767 ps
T761 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1338343593 Aug 10 05:08:45 PM PDT 24 Aug 10 05:08:46 PM PDT 24 18674489 ps
T762 /workspace/coverage/cover_reg_top/20.gpio_intr_test.2202165812 Aug 10 05:09:02 PM PDT 24 Aug 10 05:09:02 PM PDT 24 45451339 ps
T763 /workspace/coverage/cover_reg_top/35.gpio_intr_test.2500264668 Aug 10 05:09:01 PM PDT 24 Aug 10 05:09:02 PM PDT 24 29961030 ps
T764 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2268478672 Aug 10 05:08:35 PM PDT 24 Aug 10 05:08:36 PM PDT 24 51015872 ps
T765 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3300098280 Aug 10 05:08:59 PM PDT 24 Aug 10 05:09:00 PM PDT 24 30753189 ps
T93 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2380520421 Aug 10 05:09:02 PM PDT 24 Aug 10 05:09:02 PM PDT 24 14316147 ps
T766 /workspace/coverage/cover_reg_top/46.gpio_intr_test.1898706464 Aug 10 05:08:57 PM PDT 24 Aug 10 05:08:58 PM PDT 24 18894228 ps
T767 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2362083796 Aug 10 05:08:49 PM PDT 24 Aug 10 05:08:50 PM PDT 24 54299267 ps
T768 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3052010130 Aug 10 05:08:35 PM PDT 24 Aug 10 05:08:36 PM PDT 24 39167113 ps
T769 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.678066706 Aug 10 05:08:34 PM PDT 24 Aug 10 05:08:36 PM PDT 24 34344972 ps
T770 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1723254001 Aug 10 05:09:02 PM PDT 24 Aug 10 05:09:02 PM PDT 24 46020033 ps
T771 /workspace/coverage/cover_reg_top/3.gpio_intr_test.3721583186 Aug 10 05:08:34 PM PDT 24 Aug 10 05:08:35 PM PDT 24 15500080 ps
T772 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.816999414 Aug 10 05:08:39 PM PDT 24 Aug 10 05:08:40 PM PDT 24 23776644 ps
T773 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1159404064 Aug 10 05:08:46 PM PDT 24 Aug 10 05:08:48 PM PDT 24 53744212 ps
T116 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.358206533 Aug 10 05:08:34 PM PDT 24 Aug 10 05:08:36 PM PDT 24 239307802 ps
T774 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.4058368226 Aug 10 05:08:45 PM PDT 24 Aug 10 05:08:46 PM PDT 24 341903089 ps
T94 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1150342539 Aug 10 05:08:37 PM PDT 24 Aug 10 05:08:38 PM PDT 24 24861384 ps
T95 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1481475646 Aug 10 05:08:39 PM PDT 24 Aug 10 05:08:40 PM PDT 24 15584832 ps
T775 /workspace/coverage/cover_reg_top/33.gpio_intr_test.3417327327 Aug 10 05:08:56 PM PDT 24 Aug 10 05:08:56 PM PDT 24 15263082 ps
T49 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3148561816 Aug 10 05:08:40 PM PDT 24 Aug 10 05:08:41 PM PDT 24 92675964 ps
T776 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2559252559 Aug 10 05:08:47 PM PDT 24 Aug 10 05:08:48 PM PDT 24 62407075 ps
T777 /workspace/coverage/cover_reg_top/0.gpio_intr_test.983354360 Aug 10 05:08:35 PM PDT 24 Aug 10 05:08:36 PM PDT 24 19535954 ps
T778 /workspace/coverage/cover_reg_top/22.gpio_intr_test.287244993 Aug 10 05:08:59 PM PDT 24 Aug 10 05:09:00 PM PDT 24 13784358 ps
T779 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.606950608 Aug 10 05:08:39 PM PDT 24 Aug 10 05:08:40 PM PDT 24 580120453 ps
T780 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2939478485 Aug 10 05:08:35 PM PDT 24 Aug 10 05:08:36 PM PDT 24 50276810 ps
T781 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3557366786 Aug 10 05:08:44 PM PDT 24 Aug 10 05:08:47 PM PDT 24 106487099 ps
T782 /workspace/coverage/cover_reg_top/44.gpio_intr_test.1358762221 Aug 10 05:08:59 PM PDT 24 Aug 10 05:09:00 PM PDT 24 28009482 ps
T783 /workspace/coverage/cover_reg_top/10.gpio_intr_test.2298356573 Aug 10 05:08:46 PM PDT 24 Aug 10 05:08:47 PM PDT 24 32540849 ps
T784 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.4061522815 Aug 10 05:08:44 PM PDT 24 Aug 10 05:08:45 PM PDT 24 29898685 ps
T785 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3821452281 Aug 10 05:08:47 PM PDT 24 Aug 10 05:08:47 PM PDT 24 60764860 ps
T786 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.847197953 Aug 10 05:08:39 PM PDT 24 Aug 10 05:08:41 PM PDT 24 102647962 ps
T787 /workspace/coverage/cover_reg_top/24.gpio_intr_test.253859175 Aug 10 05:08:57 PM PDT 24 Aug 10 05:08:58 PM PDT 24 14358985 ps
T788 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1867692588 Aug 10 05:08:38 PM PDT 24 Aug 10 05:08:39 PM PDT 24 56294700 ps
T789 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2323589641 Aug 10 05:08:36 PM PDT 24 Aug 10 05:08:40 PM PDT 24 921865410 ps
T790 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1457386694 Aug 10 05:08:34 PM PDT 24 Aug 10 05:08:36 PM PDT 24 95982358 ps
T791 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1872346934 Aug 10 05:08:53 PM PDT 24 Aug 10 05:08:54 PM PDT 24 37734395 ps
T792 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2846485319 Aug 10 05:09:01 PM PDT 24 Aug 10 05:09:01 PM PDT 24 19095967 ps
T793 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3844412456 Aug 10 05:08:52 PM PDT 24 Aug 10 05:08:53 PM PDT 24 12665722 ps
T794 /workspace/coverage/cover_reg_top/19.gpio_intr_test.935843815 Aug 10 05:08:59 PM PDT 24 Aug 10 05:09:00 PM PDT 24 11739937 ps
T795 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2299221852 Aug 10 05:08:34 PM PDT 24 Aug 10 05:08:37 PM PDT 24 509040245 ps
T796 /workspace/coverage/cover_reg_top/42.gpio_intr_test.2068770596 Aug 10 05:08:58 PM PDT 24 Aug 10 05:08:59 PM PDT 24 15617440 ps
T797 /workspace/coverage/cover_reg_top/16.gpio_intr_test.3156513478 Aug 10 05:09:01 PM PDT 24 Aug 10 05:09:02 PM PDT 24 15339581 ps
T798 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.797838447 Aug 10 05:08:36 PM PDT 24 Aug 10 05:08:38 PM PDT 24 229912112 ps
T799 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.190016824 Aug 10 05:08:46 PM PDT 24 Aug 10 05:08:47 PM PDT 24 49828870 ps
T800 /workspace/coverage/cover_reg_top/7.gpio_intr_test.1490534132 Aug 10 05:08:45 PM PDT 24 Aug 10 05:08:46 PM PDT 24 27935257 ps
T801 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.810062336 Aug 10 05:08:46 PM PDT 24 Aug 10 05:08:47 PM PDT 24 22678701 ps
T802 /workspace/coverage/cover_reg_top/43.gpio_intr_test.3291689781 Aug 10 05:08:58 PM PDT 24 Aug 10 05:08:59 PM PDT 24 39908142 ps
T44 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3889511565 Aug 10 05:08:46 PM PDT 24 Aug 10 05:08:48 PM PDT 24 220461813 ps
T803 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3450704277 Aug 10 05:08:46 PM PDT 24 Aug 10 05:08:47 PM PDT 24 744160475 ps
T804 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.860809009 Aug 10 05:08:39 PM PDT 24 Aug 10 05:08:40 PM PDT 24 42870704 ps
T805 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3954433893 Aug 10 05:09:01 PM PDT 24 Aug 10 05:09:01 PM PDT 24 17758881 ps
T806 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3138229467 Aug 10 05:08:46 PM PDT 24 Aug 10 05:08:48 PM PDT 24 52486331 ps
T807 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1190199173 Aug 10 05:08:45 PM PDT 24 Aug 10 05:08:47 PM PDT 24 227663826 ps
T808 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.959644728 Aug 10 05:08:47 PM PDT 24 Aug 10 05:08:48 PM PDT 24 49970041 ps
T809 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2890687752 Aug 10 05:08:45 PM PDT 24 Aug 10 05:08:46 PM PDT 24 409471145 ps
T810 /workspace/coverage/cover_reg_top/30.gpio_intr_test.910639588 Aug 10 05:09:00 PM PDT 24 Aug 10 05:09:01 PM PDT 24 26921516 ps
T811 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1203450148 Aug 10 05:08:37 PM PDT 24 Aug 10 05:08:39 PM PDT 24 274442656 ps
T812 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.230877560 Aug 10 05:08:53 PM PDT 24 Aug 10 05:08:54 PM PDT 24 96459291 ps
T813 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3596522636 Aug 10 05:08:40 PM PDT 24 Aug 10 05:08:41 PM PDT 24 58813877 ps
T814 /workspace/coverage/cover_reg_top/8.gpio_intr_test.2402134165 Aug 10 05:08:48 PM PDT 24 Aug 10 05:08:48 PM PDT 24 11985512 ps
T815 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.172980139 Aug 10 05:08:47 PM PDT 24 Aug 10 05:08:48 PM PDT 24 50869373 ps
T816 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3876897495 Aug 10 05:08:46 PM PDT 24 Aug 10 05:08:48 PM PDT 24 35736181 ps
T817 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1275815218 Aug 10 05:08:45 PM PDT 24 Aug 10 05:08:48 PM PDT 24 92416925 ps
T818 /workspace/coverage/cover_reg_top/36.gpio_intr_test.2882943467 Aug 10 05:09:01 PM PDT 24 Aug 10 05:09:02 PM PDT 24 47114334 ps
T819 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3162103847 Aug 10 05:08:57 PM PDT 24 Aug 10 05:08:58 PM PDT 24 96315300 ps
T820 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1995805106 Aug 10 05:09:02 PM PDT 24 Aug 10 05:09:04 PM PDT 24 1036298780 ps
T821 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.901069174 Aug 10 05:08:34 PM PDT 24 Aug 10 05:08:37 PM PDT 24 101712380 ps
T822 /workspace/coverage/cover_reg_top/49.gpio_intr_test.914068913 Aug 10 05:08:58 PM PDT 24 Aug 10 05:09:00 PM PDT 24 14928620 ps
T823 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.4272381996 Aug 10 05:08:35 PM PDT 24 Aug 10 05:08:37 PM PDT 24 112587775 ps
T824 /workspace/coverage/cover_reg_top/39.gpio_intr_test.191175102 Aug 10 05:08:57 PM PDT 24 Aug 10 05:08:58 PM PDT 24 71055765 ps
T825 /workspace/coverage/cover_reg_top/4.gpio_intr_test.1511662999 Aug 10 05:08:36 PM PDT 24 Aug 10 05:08:36 PM PDT 24 26016735 ps
T826 /workspace/coverage/cover_reg_top/17.gpio_intr_test.242434843 Aug 10 05:08:59 PM PDT 24 Aug 10 05:09:00 PM PDT 24 21884277 ps
T827 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1965594178 Aug 10 05:08:45 PM PDT 24 Aug 10 05:08:46 PM PDT 24 77961353 ps
T828 /workspace/coverage/cover_reg_top/14.gpio_intr_test.3649588703 Aug 10 05:08:45 PM PDT 24 Aug 10 05:08:46 PM PDT 24 39979752 ps
T829 /workspace/coverage/cover_reg_top/1.gpio_intr_test.1675385941 Aug 10 05:08:37 PM PDT 24 Aug 10 05:08:38 PM PDT 24 14557323 ps
T830 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3817582091 Aug 10 05:08:59 PM PDT 24 Aug 10 05:09:00 PM PDT 24 19959303 ps
T831 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.4228658317 Aug 10 05:09:00 PM PDT 24 Aug 10 05:09:01 PM PDT 24 18253904 ps
T832 /workspace/coverage/cover_reg_top/13.gpio_intr_test.202942776 Aug 10 05:08:47 PM PDT 24 Aug 10 05:08:48 PM PDT 24 36290059 ps
T833 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2139695372 Aug 10 05:08:34 PM PDT 24 Aug 10 05:08:34 PM PDT 24 92012035 ps
T834 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.761553554 Aug 10 05:08:47 PM PDT 24 Aug 10 05:08:48 PM PDT 24 260302126 ps
T835 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.161322488 Aug 10 05:08:46 PM PDT 24 Aug 10 05:08:47 PM PDT 24 31114893 ps
T836 /workspace/coverage/cover_reg_top/28.gpio_intr_test.1650070973 Aug 10 05:08:59 PM PDT 24 Aug 10 05:09:00 PM PDT 24 15718209 ps
T837 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1406509718 Aug 10 05:08:38 PM PDT 24 Aug 10 05:08:39 PM PDT 24 38699186 ps
T96 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3286401775 Aug 10 05:08:37 PM PDT 24 Aug 10 05:08:37 PM PDT 24 67939527 ps
T838 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2177055973 Aug 10 05:08:46 PM PDT 24 Aug 10 05:08:47 PM PDT 24 45216469 ps
T839 /workspace/coverage/cover_reg_top/6.gpio_intr_test.595417029 Aug 10 05:08:53 PM PDT 24 Aug 10 05:08:53 PM PDT 24 49728348 ps
T840 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2568348274 Aug 10 05:09:02 PM PDT 24 Aug 10 05:09:04 PM PDT 24 41340741 ps
T97 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1757298071 Aug 10 05:08:34 PM PDT 24 Aug 10 05:08:37 PM PDT 24 236365335 ps
T841 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.4170949874 Aug 10 05:11:34 PM PDT 24 Aug 10 05:11:35 PM PDT 24 41125730 ps
T842 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1422523645 Aug 10 05:11:23 PM PDT 24 Aug 10 05:11:24 PM PDT 24 169624724 ps
T843 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4209345297 Aug 10 05:11:31 PM PDT 24 Aug 10 05:11:33 PM PDT 24 292069816 ps
T844 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3659507514 Aug 10 05:11:13 PM PDT 24 Aug 10 05:11:13 PM PDT 24 96715159 ps
T845 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.477090735 Aug 10 05:11:16 PM PDT 24 Aug 10 05:11:17 PM PDT 24 311802506 ps
T846 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2419664534 Aug 10 05:11:33 PM PDT 24 Aug 10 05:11:34 PM PDT 24 77252354 ps
T847 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3058432139 Aug 10 05:11:35 PM PDT 24 Aug 10 05:11:37 PM PDT 24 252583821 ps
T848 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.136044767 Aug 10 05:11:35 PM PDT 24 Aug 10 05:11:36 PM PDT 24 59338252 ps
T849 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2203202635 Aug 10 05:11:11 PM PDT 24 Aug 10 05:11:12 PM PDT 24 43375621 ps
T850 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1122313200 Aug 10 05:11:25 PM PDT 24 Aug 10 05:11:26 PM PDT 24 427822340 ps
T851 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2535156011 Aug 10 05:11:13 PM PDT 24 Aug 10 05:11:14 PM PDT 24 115434316 ps
T852 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1966511040 Aug 10 05:11:24 PM PDT 24 Aug 10 05:11:26 PM PDT 24 230271898 ps
T853 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.693667631 Aug 10 05:11:34 PM PDT 24 Aug 10 05:11:35 PM PDT 24 84590975 ps
T854 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3872199667 Aug 10 05:11:13 PM PDT 24 Aug 10 05:11:14 PM PDT 24 187754945 ps
T855 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.4225281302 Aug 10 05:11:45 PM PDT 24 Aug 10 05:11:46 PM PDT 24 29257000 ps
T856 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1266583332 Aug 10 05:11:32 PM PDT 24 Aug 10 05:11:33 PM PDT 24 216092350 ps
T857 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.337731599 Aug 10 05:11:13 PM PDT 24 Aug 10 05:11:14 PM PDT 24 227672412 ps
T858 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.411751095 Aug 10 05:11:02 PM PDT 24 Aug 10 05:11:03 PM PDT 24 82359892 ps
T859 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1486812878 Aug 10 05:11:25 PM PDT 24 Aug 10 05:11:27 PM PDT 24 38554666 ps
T860 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.513921546 Aug 10 05:11:04 PM PDT 24 Aug 10 05:11:05 PM PDT 24 87373987 ps
T861 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3653705862 Aug 10 05:11:42 PM PDT 24 Aug 10 05:11:43 PM PDT 24 71661874 ps
T862 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2656188811 Aug 10 05:11:13 PM PDT 24 Aug 10 05:11:14 PM PDT 24 108401262 ps
T863 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4140225268 Aug 10 05:11:12 PM PDT 24 Aug 10 05:11:13 PM PDT 24 114892238 ps
T864 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1699630689 Aug 10 05:11:41 PM PDT 24 Aug 10 05:11:42 PM PDT 24 106488933 ps
T865 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2448675381 Aug 10 05:11:43 PM PDT 24 Aug 10 05:11:44 PM PDT 24 91474102 ps
T866 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.774000348 Aug 10 05:11:42 PM PDT 24 Aug 10 05:11:44 PM PDT 24 138787148 ps
T867 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.844561617 Aug 10 05:11:11 PM PDT 24 Aug 10 05:11:12 PM PDT 24 246726811 ps
T868 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2569453086 Aug 10 05:11:26 PM PDT 24 Aug 10 05:11:27 PM PDT 24 96229949 ps
T869 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2538279791 Aug 10 05:11:26 PM PDT 24 Aug 10 05:11:27 PM PDT 24 88913971 ps
T870 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3785471171 Aug 10 05:11:32 PM PDT 24 Aug 10 05:11:33 PM PDT 24 89690727 ps
T871 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1086396963 Aug 10 05:11:32 PM PDT 24 Aug 10 05:11:34 PM PDT 24 150359645 ps
T872 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1913074363 Aug 10 05:11:24 PM PDT 24 Aug 10 05:11:25 PM PDT 24 74432049 ps
T873 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2399176913 Aug 10 05:11:34 PM PDT 24 Aug 10 05:11:35 PM PDT 24 33011031 ps
T874 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.720991509 Aug 10 05:11:33 PM PDT 24 Aug 10 05:11:34 PM PDT 24 680505886 ps
T875 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.716325658 Aug 10 05:11:24 PM PDT 24 Aug 10 05:11:26 PM PDT 24 39133042 ps
T876 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3919856974 Aug 10 05:11:24 PM PDT 24 Aug 10 05:11:25 PM PDT 24 26256024 ps
T877 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2823131497 Aug 10 05:11:05 PM PDT 24 Aug 10 05:11:06 PM PDT 24 34145978 ps
T878 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1460445323 Aug 10 05:11:12 PM PDT 24 Aug 10 05:11:13 PM PDT 24 240856214 ps
T879 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.4037161237 Aug 10 05:11:14 PM PDT 24 Aug 10 05:11:15 PM PDT 24 112904943 ps
T880 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1512821160 Aug 10 05:11:32 PM PDT 24 Aug 10 05:11:34 PM PDT 24 38474705 ps
T881 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4026391987 Aug 10 05:11:23 PM PDT 24 Aug 10 05:11:24 PM PDT 24 110518318 ps
T882 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.896916190 Aug 10 05:11:04 PM PDT 24 Aug 10 05:11:06 PM PDT 24 106743519 ps
T883 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3192603839 Aug 10 05:11:14 PM PDT 24 Aug 10 05:11:15 PM PDT 24 172147583 ps
T884 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1511111186 Aug 10 05:11:43 PM PDT 24 Aug 10 05:11:44 PM PDT 24 39789433 ps
T885 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.765581058 Aug 10 05:11:24 PM PDT 24 Aug 10 05:11:25 PM PDT 24 102569110 ps
T886 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.549379576 Aug 10 05:11:04 PM PDT 24 Aug 10 05:11:05 PM PDT 24 193698251 ps
T887 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4240917639 Aug 10 05:11:35 PM PDT 24 Aug 10 05:11:35 PM PDT 24 84230963 ps
T888 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2457649331 Aug 10 05:11:36 PM PDT 24 Aug 10 05:11:38 PM PDT 24 321986991 ps
T889 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1287839836 Aug 10 05:11:32 PM PDT 24 Aug 10 05:11:33 PM PDT 24 50591841 ps
T890 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.4096038450 Aug 10 05:11:31 PM PDT 24 Aug 10 05:11:33 PM PDT 24 70643923 ps
T891 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2319649794 Aug 10 05:11:14 PM PDT 24 Aug 10 05:11:15 PM PDT 24 106327121 ps
T892 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3822103460 Aug 10 05:11:23 PM PDT 24 Aug 10 05:11:24 PM PDT 24 33242232 ps
T893 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1152497161 Aug 10 05:11:11 PM PDT 24 Aug 10 05:11:13 PM PDT 24 171594782 ps
T894 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3683568500 Aug 10 05:11:35 PM PDT 24 Aug 10 05:11:36 PM PDT 24 333540000 ps
T895 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.595763222 Aug 10 05:11:31 PM PDT 24 Aug 10 05:11:32 PM PDT 24 67204095 ps
T896 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1785296914 Aug 10 05:11:12 PM PDT 24 Aug 10 05:11:13 PM PDT 24 206131035 ps
T897 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.618386225 Aug 10 05:11:41 PM PDT 24 Aug 10 05:11:42 PM PDT 24 43257678 ps
T898 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1588824850 Aug 10 05:11:35 PM PDT 24 Aug 10 05:11:36 PM PDT 24 61949084 ps
T899 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3879749981 Aug 10 05:11:43 PM PDT 24 Aug 10 05:11:45 PM PDT 24 169059492 ps
T900 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1216733362 Aug 10 05:11:11 PM PDT 24 Aug 10 05:11:12 PM PDT 24 64744593 ps
T901 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3609878095 Aug 10 05:11:14 PM PDT 24 Aug 10 05:11:15 PM PDT 24 91171788 ps
T902 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3125463739 Aug 10 05:11:03 PM PDT 24 Aug 10 05:11:05 PM PDT 24 80488017 ps
T903 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.695486642 Aug 10 05:11:24 PM PDT 24 Aug 10 05:11:25 PM PDT 24 79348874 ps
T904 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2980538756 Aug 10 05:11:34 PM PDT 24 Aug 10 05:11:36 PM PDT 24 32585346 ps
T905 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.4179743202 Aug 10 05:11:24 PM PDT 24 Aug 10 05:11:25 PM PDT 24 534323748 ps
T906 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.4285805797 Aug 10 05:11:33 PM PDT 24 Aug 10 05:11:34 PM PDT 24 28359801 ps
T907 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2464769086 Aug 10 05:11:35 PM PDT 24 Aug 10 05:11:36 PM PDT 24 74651365 ps
T908 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2352648589 Aug 10 05:11:22 PM PDT 24 Aug 10 05:11:24 PM PDT 24 79228132 ps
T909 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1657039685 Aug 10 05:11:33 PM PDT 24 Aug 10 05:11:35 PM PDT 24 143097536 ps
T910 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.400770981 Aug 10 05:11:13 PM PDT 24 Aug 10 05:11:14 PM PDT 24 69936339 ps
T911 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2211945482 Aug 10 05:11:13 PM PDT 24 Aug 10 05:11:14 PM PDT 24 936476957 ps
T912 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4126179952 Aug 10 05:11:15 PM PDT 24 Aug 10 05:11:16 PM PDT 24 229177321 ps
T913 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2620814540 Aug 10 05:11:04 PM PDT 24 Aug 10 05:11:06 PM PDT 24 269823057 ps
T914 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2179195916 Aug 10 05:11:13 PM PDT 24 Aug 10 05:11:14 PM PDT 24 100037036 ps
T915 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.849048760 Aug 10 05:11:11 PM PDT 24 Aug 10 05:11:12 PM PDT 24 95589366 ps
T916 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2058259045 Aug 10 05:11:44 PM PDT 24 Aug 10 05:11:45 PM PDT 24 87126652 ps
T917 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1039882208 Aug 10 05:11:32 PM PDT 24 Aug 10 05:11:34 PM PDT 24 135939039 ps
T918 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1942820285 Aug 10 05:11:08 PM PDT 24 Aug 10 05:11:09 PM PDT 24 261582586 ps
T919 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.722210623 Aug 10 05:11:23 PM PDT 24 Aug 10 05:11:24 PM PDT 24 354544518 ps
T920 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2267191975 Aug 10 05:11:13 PM PDT 24 Aug 10 05:11:14 PM PDT 24 164452649 ps
T921 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1016884394 Aug 10 05:11:14 PM PDT 24 Aug 10 05:11:15 PM PDT 24 94259452 ps
T922 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.414694151 Aug 10 05:11:14 PM PDT 24 Aug 10 05:11:15 PM PDT 24 262617521 ps
T923 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2097638057 Aug 10 05:11:14 PM PDT 24 Aug 10 05:11:15 PM PDT 24 98901541 ps
T924 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.953393288 Aug 10 05:11:16 PM PDT 24 Aug 10 05:11:17 PM PDT 24 49329918 ps
T925 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1983107333 Aug 10 05:11:16 PM PDT 24 Aug 10 05:11:17 PM PDT 24 36890495 ps
T926 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2787547644 Aug 10 05:11:33 PM PDT 24 Aug 10 05:11:34 PM PDT 24 82229579 ps
T927 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1175736138 Aug 10 05:11:12 PM PDT 24 Aug 10 05:11:13 PM PDT 24 109595018 ps
T928 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3361968704 Aug 10 05:11:14 PM PDT 24 Aug 10 05:11:15 PM PDT 24 536149914 ps
T929 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.815394855 Aug 10 05:11:35 PM PDT 24 Aug 10 05:11:37 PM PDT 24 46124974 ps
T930 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.311573242 Aug 10 05:11:16 PM PDT 24 Aug 10 05:11:17 PM PDT 24 208784492 ps
T931 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.735526222 Aug 10 05:11:35 PM PDT 24 Aug 10 05:11:37 PM PDT 24 282509442 ps
T932 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3807594709 Aug 10 05:11:34 PM PDT 24 Aug 10 05:11:35 PM PDT 24 263142608 ps
T933 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1364094070 Aug 10 05:11:26 PM PDT 24 Aug 10 05:11:27 PM PDT 24 104199384 ps
T934 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.769727911 Aug 10 05:11:15 PM PDT 24 Aug 10 05:11:16 PM PDT 24 151945727 ps
T935 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1535735450 Aug 10 05:11:11 PM PDT 24 Aug 10 05:11:13 PM PDT 24 133332347 ps
T936 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1784766442 Aug 10 05:11:26 PM PDT 24 Aug 10 05:11:28 PM PDT 24 379646046 ps
T937 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1097433592 Aug 10 05:11:34 PM PDT 24 Aug 10 05:11:36 PM PDT 24 221071495 ps
T938 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2006969800 Aug 10 05:11:12 PM PDT 24 Aug 10 05:11:14 PM PDT 24 49353565 ps
T939 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3152604372 Aug 10 05:11:44 PM PDT 24 Aug 10 05:11:45 PM PDT 24 615874564 ps
T940 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3402718404 Aug 10 05:11:13 PM PDT 24 Aug 10 05:11:14 PM PDT 24 59999639 ps

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.102401351
Short name T31
Test name
Test status
Simulation time 341542405834 ps
CPU time 1168.96 seconds
Started Aug 10 05:15:43 PM PDT 24
Finished Aug 10 05:35:13 PM PDT 24
Peak memory 206976 kb
Host smart-6f87e081-8435-497e-8a40-f6e39205a5dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=102401351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.102401351
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3521184954
Short name T18
Test name
Test status
Simulation time 189444042 ps
CPU time 3.9 seconds
Started Aug 10 05:16:35 PM PDT 24
Finished Aug 10 05:16:39 PM PDT 24
Peak memory 198636 kb
Host smart-12512a33-ae37-456e-97cc-cde192c687c0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521184954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3521184954
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3417137945
Short name T86
Test name
Test status
Simulation time 11738049 ps
CPU time 0.55 seconds
Started Aug 10 05:08:46 PM PDT 24
Finished Aug 10 05:08:47 PM PDT 24
Peak memory 194664 kb
Host smart-51677516-b913-4706-8c46-33a8ced09b48
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417137945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.3417137945
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.787628702
Short name T35
Test name
Test status
Simulation time 398391166 ps
CPU time 1.49 seconds
Started Aug 10 05:08:59 PM PDT 24
Finished Aug 10 05:09:01 PM PDT 24
Peak memory 198700 kb
Host smart-fd899153-f820-4b99-8697-935f988ecb14
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787628702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.gpio_tl_intg_err.787628702
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.4086201809
Short name T2
Test name
Test status
Simulation time 609183170 ps
CPU time 2.24 seconds
Started Aug 10 05:16:30 PM PDT 24
Finished Aug 10 05:16:32 PM PDT 24
Peak memory 198536 kb
Host smart-c8dd9f4b-78bf-454d-97de-5785c5c93650
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086201809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.4086201809
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_alert_test.2655897253
Short name T40
Test name
Test status
Simulation time 14557591 ps
CPU time 0.59 seconds
Started Aug 10 05:15:23 PM PDT 24
Finished Aug 10 05:15:24 PM PDT 24
Peak memory 194460 kb
Host smart-635e3ffc-5a1d-4027-908a-ef5d9d3bae5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655897253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.2655897253
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.1555009541
Short name T37
Test name
Test status
Simulation time 132414579 ps
CPU time 0.8 seconds
Started Aug 10 05:15:05 PM PDT 24
Finished Aug 10 05:15:06 PM PDT 24
Peak memory 214352 kb
Host smart-da9040dc-ee55-4426-ad73-3f3339cb52b4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555009541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.1555009541
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1222519461
Short name T85
Test name
Test status
Simulation time 19719319 ps
CPU time 0.67 seconds
Started Aug 10 05:08:37 PM PDT 24
Finished Aug 10 05:08:38 PM PDT 24
Peak memory 195224 kb
Host smart-17424c79-bc6d-4f5b-99e3-e2bf0371cfff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222519461 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1222519461
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.3818190935
Short name T43
Test name
Test status
Simulation time 51522565 ps
CPU time 0.88 seconds
Started Aug 10 05:08:47 PM PDT 24
Finished Aug 10 05:08:48 PM PDT 24
Peak memory 197476 kb
Host smart-fdf38450-2ce2-4b4a-9258-26f31e2c219b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818190935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.3818190935
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.606950608
Short name T779
Test name
Test status
Simulation time 580120453 ps
CPU time 1.15 seconds
Started Aug 10 05:08:39 PM PDT 24
Finished Aug 10 05:08:40 PM PDT 24
Peak memory 198756 kb
Host smart-fbd1014c-a553-41ff-ae60-408619b6fe32
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606950608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.gpio_tl_intg_err.606950608
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1481475646
Short name T95
Test name
Test status
Simulation time 15584832 ps
CPU time 0.65 seconds
Started Aug 10 05:08:39 PM PDT 24
Finished Aug 10 05:08:40 PM PDT 24
Peak memory 195424 kb
Host smart-fed29940-034d-4d47-a15f-1bf83c608e37
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481475646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.1481475646
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.521794835
Short name T748
Test name
Test status
Simulation time 5286234275 ps
CPU time 3.61 seconds
Started Aug 10 05:08:35 PM PDT 24
Finished Aug 10 05:08:38 PM PDT 24
Peak memory 198200 kb
Host smart-f69d3601-bbd7-4fce-ba15-cf08add0580a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521794835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.521794835
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.4262479585
Short name T756
Test name
Test status
Simulation time 24468015 ps
CPU time 0.68 seconds
Started Aug 10 05:08:38 PM PDT 24
Finished Aug 10 05:08:39 PM PDT 24
Peak memory 196456 kb
Host smart-dc3d15ff-9446-486f-a39a-48ffbbe78d83
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262479585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.4262479585
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1650313062
Short name T722
Test name
Test status
Simulation time 35927567 ps
CPU time 0.67 seconds
Started Aug 10 05:08:35 PM PDT 24
Finished Aug 10 05:08:36 PM PDT 24
Peak memory 198256 kb
Host smart-4bf72303-7f28-49b3-b9ea-4735b1cd6766
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650313062 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1650313062
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.91342152
Short name T741
Test name
Test status
Simulation time 15177552 ps
CPU time 0.7 seconds
Started Aug 10 05:08:35 PM PDT 24
Finished Aug 10 05:08:36 PM PDT 24
Peak memory 196344 kb
Host smart-30aaac19-f5f6-4da8-b888-d98e5a4a51e1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91342152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_c
sr_rw.91342152
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.983354360
Short name T777
Test name
Test status
Simulation time 19535954 ps
CPU time 0.58 seconds
Started Aug 10 05:08:35 PM PDT 24
Finished Aug 10 05:08:36 PM PDT 24
Peak memory 194392 kb
Host smart-6eabeab1-dcd7-48ee-bbd7-37f4c3744957
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983354360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.983354360
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3052010130
Short name T768
Test name
Test status
Simulation time 39167113 ps
CPU time 0.88 seconds
Started Aug 10 05:08:35 PM PDT 24
Finished Aug 10 05:08:36 PM PDT 24
Peak memory 196872 kb
Host smart-184a6a94-4b7a-41f7-b114-aef685d497b7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052010130 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3052010130
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.901069174
Short name T821
Test name
Test status
Simulation time 101712380 ps
CPU time 2.83 seconds
Started Aug 10 05:08:34 PM PDT 24
Finished Aug 10 05:08:37 PM PDT 24
Peak memory 198832 kb
Host smart-275e3e28-b76b-4f15-ae01-e455a8872054
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901069174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.901069174
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1176555129
Short name T91
Test name
Test status
Simulation time 257025077 ps
CPU time 0.74 seconds
Started Aug 10 05:08:37 PM PDT 24
Finished Aug 10 05:08:38 PM PDT 24
Peak memory 196132 kb
Host smart-0c9b0ddc-7b4e-4fa8-bcf3-b9d83be3b5b6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176555129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.1176555129
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1757298071
Short name T97
Test name
Test status
Simulation time 236365335 ps
CPU time 1.99 seconds
Started Aug 10 05:08:34 PM PDT 24
Finished Aug 10 05:08:37 PM PDT 24
Peak memory 197312 kb
Host smart-3062ec33-3eee-46f7-8aff-11328d510fb6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757298071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.1757298071
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1406509718
Short name T837
Test name
Test status
Simulation time 38699186 ps
CPU time 0.58 seconds
Started Aug 10 05:08:38 PM PDT 24
Finished Aug 10 05:08:39 PM PDT 24
Peak memory 195120 kb
Host smart-df9d767a-5013-49c4-8660-816105fdfb2a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406509718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.1406509718
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.847197953
Short name T786
Test name
Test status
Simulation time 102647962 ps
CPU time 1.61 seconds
Started Aug 10 05:08:39 PM PDT 24
Finished Aug 10 05:08:41 PM PDT 24
Peak memory 198796 kb
Host smart-70bc30f4-5682-4dbe-9516-991d425dea2c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847197953 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.847197953
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1150342539
Short name T94
Test name
Test status
Simulation time 24861384 ps
CPU time 0.63 seconds
Started Aug 10 05:08:37 PM PDT 24
Finished Aug 10 05:08:38 PM PDT 24
Peak memory 195552 kb
Host smart-5718edff-60a7-4ad0-816f-f33786189e2d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150342539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1150342539
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1675385941
Short name T829
Test name
Test status
Simulation time 14557323 ps
CPU time 0.58 seconds
Started Aug 10 05:08:37 PM PDT 24
Finished Aug 10 05:08:38 PM PDT 24
Peak memory 194364 kb
Host smart-fafc7dc6-78d1-4782-9526-942058037c50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675385941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1675385941
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2251046310
Short name T712
Test name
Test status
Simulation time 199208728 ps
CPU time 2.02 seconds
Started Aug 10 05:08:41 PM PDT 24
Finished Aug 10 05:08:43 PM PDT 24
Peak memory 198840 kb
Host smart-69ac9218-5238-4f87-9ed1-2010fe849c5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251046310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2251046310
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.358206533
Short name T116
Test name
Test status
Simulation time 239307802 ps
CPU time 1.62 seconds
Started Aug 10 05:08:34 PM PDT 24
Finished Aug 10 05:08:36 PM PDT 24
Peak memory 198704 kb
Host smart-181ca93a-2868-4161-b898-3a8200e7b95c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358206533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.gpio_tl_intg_err.358206533
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3042936640
Short name T753
Test name
Test status
Simulation time 89608037 ps
CPU time 0.81 seconds
Started Aug 10 05:08:49 PM PDT 24
Finished Aug 10 05:08:50 PM PDT 24
Peak memory 198548 kb
Host smart-eeba23bb-4763-407c-a3e7-d5e30051a13c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042936640 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.3042936640
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3752538305
Short name T726
Test name
Test status
Simulation time 18728057 ps
CPU time 0.65 seconds
Started Aug 10 05:08:48 PM PDT 24
Finished Aug 10 05:08:49 PM PDT 24
Peak memory 195368 kb
Host smart-824f0b2d-fa53-4f87-b3c1-28b11db93998
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752538305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3752538305
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.2298356573
Short name T783
Test name
Test status
Simulation time 32540849 ps
CPU time 0.67 seconds
Started Aug 10 05:08:46 PM PDT 24
Finished Aug 10 05:08:47 PM PDT 24
Peak memory 195064 kb
Host smart-f4026ad1-9137-4c7b-a2f1-d3cf76d2309f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298356573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.2298356573
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2014484797
Short name T102
Test name
Test status
Simulation time 86078951 ps
CPU time 0.8 seconds
Started Aug 10 05:08:46 PM PDT 24
Finished Aug 10 05:08:47 PM PDT 24
Peak memory 196696 kb
Host smart-05c756a9-99fa-4b6b-b32f-d2742b114ddf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014484797 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.2014484797
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.204710562
Short name T742
Test name
Test status
Simulation time 186193007 ps
CPU time 1.2 seconds
Started Aug 10 05:08:45 PM PDT 24
Finished Aug 10 05:08:46 PM PDT 24
Peak memory 198776 kb
Host smart-c1030d36-0603-45dd-ab28-9dc06eff30fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204710562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.204710562
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2890687752
Short name T809
Test name
Test status
Simulation time 409471145 ps
CPU time 0.85 seconds
Started Aug 10 05:08:45 PM PDT 24
Finished Aug 10 05:08:46 PM PDT 24
Peak memory 197724 kb
Host smart-94fec5c6-a156-4b3c-8ee4-ff99d853cf05
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890687752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.2890687752
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.211531853
Short name T746
Test name
Test status
Simulation time 188415545 ps
CPU time 1.17 seconds
Started Aug 10 05:08:48 PM PDT 24
Finished Aug 10 05:08:49 PM PDT 24
Peak memory 198776 kb
Host smart-272ccb42-7282-45bf-9c16-52061d8fbb4a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211531853 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.211531853
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3133885220
Short name T114
Test name
Test status
Simulation time 48759650 ps
CPU time 0.59 seconds
Started Aug 10 05:08:46 PM PDT 24
Finished Aug 10 05:08:47 PM PDT 24
Peak memory 195428 kb
Host smart-584c68dc-d7f5-4007-be90-af365cfcc3a1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133885220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.3133885220
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.1192788940
Short name T721
Test name
Test status
Simulation time 16077836 ps
CPU time 0.65 seconds
Started Aug 10 05:08:48 PM PDT 24
Finished Aug 10 05:08:48 PM PDT 24
Peak memory 195156 kb
Host smart-d5e673ab-9053-4a4b-a1bb-7f9a915fae32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192788940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.1192788940
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1338343593
Short name T761
Test name
Test status
Simulation time 18674489 ps
CPU time 0.69 seconds
Started Aug 10 05:08:45 PM PDT 24
Finished Aug 10 05:08:46 PM PDT 24
Peak memory 195708 kb
Host smart-17d5bb7d-7624-4650-8eee-57c79f5256c0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338343593 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1338343593
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2238377251
Short name T735
Test name
Test status
Simulation time 68862362 ps
CPU time 3.04 seconds
Started Aug 10 05:08:47 PM PDT 24
Finished Aug 10 05:08:50 PM PDT 24
Peak memory 198824 kb
Host smart-106fde9d-2828-4311-9919-03b4d76b9416
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238377251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2238377251
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2177055973
Short name T838
Test name
Test status
Simulation time 45216469 ps
CPU time 0.92 seconds
Started Aug 10 05:08:46 PM PDT 24
Finished Aug 10 05:08:47 PM PDT 24
Peak memory 198000 kb
Host smart-2cf1859a-856f-4d75-8bc1-204942c3cceb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177055973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.2177055973
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.230877560
Short name T812
Test name
Test status
Simulation time 96459291 ps
CPU time 0.84 seconds
Started Aug 10 05:08:53 PM PDT 24
Finished Aug 10 05:08:54 PM PDT 24
Peak memory 198596 kb
Host smart-76235376-dee4-4d46-aea1-9fa00d33a166
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230877560 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.230877560
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.149885887
Short name T727
Test name
Test status
Simulation time 38630848 ps
CPU time 0.56 seconds
Started Aug 10 05:08:44 PM PDT 24
Finished Aug 10 05:08:45 PM PDT 24
Peak memory 194332 kb
Host smart-e8662e7b-9026-4595-b06a-70c7b964b823
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149885887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.149885887
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1872346934
Short name T791
Test name
Test status
Simulation time 37734395 ps
CPU time 0.67 seconds
Started Aug 10 05:08:53 PM PDT 24
Finished Aug 10 05:08:54 PM PDT 24
Peak memory 195208 kb
Host smart-1dbaca74-47d1-4895-9313-ff8f0d93e7ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872346934 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.1872346934
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2273438512
Short name T713
Test name
Test status
Simulation time 74651138 ps
CPU time 2.06 seconds
Started Aug 10 05:08:46 PM PDT 24
Finished Aug 10 05:08:48 PM PDT 24
Peak memory 198888 kb
Host smart-a7854b08-c1e3-4cb4-88a2-9cb5ba88a788
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273438512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.2273438512
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3889511565
Short name T44
Test name
Test status
Simulation time 220461813 ps
CPU time 1.13 seconds
Started Aug 10 05:08:46 PM PDT 24
Finished Aug 10 05:08:48 PM PDT 24
Peak memory 198776 kb
Host smart-0be94dc3-eb54-439d-90d5-26016f7747d0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889511565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.3889511565
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.810062336
Short name T801
Test name
Test status
Simulation time 22678701 ps
CPU time 0.81 seconds
Started Aug 10 05:08:46 PM PDT 24
Finished Aug 10 05:08:47 PM PDT 24
Peak memory 198656 kb
Host smart-f7eb0f13-61ca-4e8c-a357-7f7fecd20b6a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810062336 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.810062336
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1698185413
Short name T90
Test name
Test status
Simulation time 14516730 ps
CPU time 0.59 seconds
Started Aug 10 05:08:45 PM PDT 24
Finished Aug 10 05:08:46 PM PDT 24
Peak memory 195860 kb
Host smart-fc9832e5-f141-4389-814e-32ff8ea7574c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698185413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.1698185413
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.202942776
Short name T832
Test name
Test status
Simulation time 36290059 ps
CPU time 0.64 seconds
Started Aug 10 05:08:47 PM PDT 24
Finished Aug 10 05:08:48 PM PDT 24
Peak memory 194524 kb
Host smart-e9fa271c-0c04-439d-874f-b43e06d038f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202942776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.202942776
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.161322488
Short name T835
Test name
Test status
Simulation time 31114893 ps
CPU time 0.86 seconds
Started Aug 10 05:08:46 PM PDT 24
Finished Aug 10 05:08:47 PM PDT 24
Peak memory 196916 kb
Host smart-2835bb73-bc62-4c61-bd61-326bdd97e75f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161322488 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 13.gpio_same_csr_outstanding.161322488
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.38538277
Short name T744
Test name
Test status
Simulation time 579386907 ps
CPU time 2.8 seconds
Started Aug 10 05:08:47 PM PDT 24
Finished Aug 10 05:08:50 PM PDT 24
Peak memory 198828 kb
Host smart-ebb704d9-865d-4fe2-b11f-b47d46ccfee7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38538277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.38538277
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.959644728
Short name T808
Test name
Test status
Simulation time 49970041 ps
CPU time 0.84 seconds
Started Aug 10 05:08:47 PM PDT 24
Finished Aug 10 05:08:48 PM PDT 24
Peak memory 198660 kb
Host smart-2f2b639a-392a-4203-b052-d5007040a12d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959644728 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.959644728
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2559252559
Short name T776
Test name
Test status
Simulation time 62407075 ps
CPU time 0.62 seconds
Started Aug 10 05:08:47 PM PDT 24
Finished Aug 10 05:08:48 PM PDT 24
Peak memory 195936 kb
Host smart-9e659700-4939-4398-8cf2-8a27a7d58321
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559252559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2559252559
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.3649588703
Short name T828
Test name
Test status
Simulation time 39979752 ps
CPU time 0.6 seconds
Started Aug 10 05:08:45 PM PDT 24
Finished Aug 10 05:08:46 PM PDT 24
Peak memory 194504 kb
Host smart-ed6e13de-f109-4b68-b640-fea31c910901
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649588703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.3649588703
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1249981038
Short name T103
Test name
Test status
Simulation time 123379767 ps
CPU time 0.88 seconds
Started Aug 10 05:08:52 PM PDT 24
Finished Aug 10 05:08:53 PM PDT 24
Peak memory 197064 kb
Host smart-e77f5945-c205-4e65-a7b7-ab9bd36a4be3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249981038 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.1249981038
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1349433936
Short name T749
Test name
Test status
Simulation time 696534508 ps
CPU time 2.64 seconds
Started Aug 10 05:08:47 PM PDT 24
Finished Aug 10 05:08:50 PM PDT 24
Peak memory 198684 kb
Host smart-c2060146-13ba-4756-a939-a27ca868b330
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349433936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.1349433936
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1965594178
Short name T827
Test name
Test status
Simulation time 77961353 ps
CPU time 0.91 seconds
Started Aug 10 05:08:45 PM PDT 24
Finished Aug 10 05:08:46 PM PDT 24
Peak memory 197912 kb
Host smart-73c19573-6e54-4d1c-8a65-e7d8ef47cccf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965594178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1965594178
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.172980139
Short name T815
Test name
Test status
Simulation time 50869373 ps
CPU time 0.71 seconds
Started Aug 10 05:08:47 PM PDT 24
Finished Aug 10 05:08:48 PM PDT 24
Peak memory 197716 kb
Host smart-bfde5e97-bdaa-4c91-b625-d20c32d41fa0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172980139 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.172980139
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1206335079
Short name T757
Test name
Test status
Simulation time 92128733 ps
CPU time 0.68 seconds
Started Aug 10 05:08:46 PM PDT 24
Finished Aug 10 05:08:47 PM PDT 24
Peak memory 196068 kb
Host smart-c7c38e38-1796-4c79-a1c6-356814009271
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206335079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.1206335079
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.685942398
Short name T758
Test name
Test status
Simulation time 13920320 ps
CPU time 0.62 seconds
Started Aug 10 05:08:44 PM PDT 24
Finished Aug 10 05:08:45 PM PDT 24
Peak memory 194424 kb
Host smart-a3118c6a-36ec-446e-87aa-22116a8c2a8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685942398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.685942398
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2362083796
Short name T767
Test name
Test status
Simulation time 54299267 ps
CPU time 0.75 seconds
Started Aug 10 05:08:49 PM PDT 24
Finished Aug 10 05:08:50 PM PDT 24
Peak memory 195672 kb
Host smart-54b6bffa-6b3c-47cc-8cb7-f35045894a9a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362083796 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2362083796
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1159404064
Short name T773
Test name
Test status
Simulation time 53744212 ps
CPU time 1.56 seconds
Started Aug 10 05:08:46 PM PDT 24
Finished Aug 10 05:08:48 PM PDT 24
Peak memory 198804 kb
Host smart-3722975a-520d-4ebc-8dca-d3b8521a0919
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159404064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.1159404064
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.761553554
Short name T834
Test name
Test status
Simulation time 260302126 ps
CPU time 1.15 seconds
Started Aug 10 05:08:47 PM PDT 24
Finished Aug 10 05:08:48 PM PDT 24
Peak memory 198692 kb
Host smart-08311946-7921-4259-b5c6-94741948518b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761553554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.gpio_tl_intg_err.761553554
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3162103847
Short name T819
Test name
Test status
Simulation time 96315300 ps
CPU time 0.75 seconds
Started Aug 10 05:08:57 PM PDT 24
Finished Aug 10 05:08:58 PM PDT 24
Peak memory 198648 kb
Host smart-2b8bcf5f-6f88-463a-ba5e-e3020b3f5595
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162103847 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.3162103847
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3844412456
Short name T793
Test name
Test status
Simulation time 12665722 ps
CPU time 0.59 seconds
Started Aug 10 05:08:52 PM PDT 24
Finished Aug 10 05:08:53 PM PDT 24
Peak memory 195920 kb
Host smart-6473fc9c-2b8f-4eae-b8d7-358257936191
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844412456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.3844412456
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3156513478
Short name T797
Test name
Test status
Simulation time 15339581 ps
CPU time 0.65 seconds
Started Aug 10 05:09:01 PM PDT 24
Finished Aug 10 05:09:02 PM PDT 24
Peak memory 194216 kb
Host smart-687e4ddf-f24a-41bc-a3d2-c5829f2be67b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156513478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3156513478
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2700643370
Short name T98
Test name
Test status
Simulation time 72706856 ps
CPU time 0.86 seconds
Started Aug 10 05:08:47 PM PDT 24
Finished Aug 10 05:08:48 PM PDT 24
Peak memory 198108 kb
Host smart-989e5ce5-7e5a-42f2-90ff-6575ec756fff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700643370 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2700643370
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.783795412
Short name T760
Test name
Test status
Simulation time 1193234585 ps
CPU time 2.17 seconds
Started Aug 10 05:08:56 PM PDT 24
Finished Aug 10 05:08:59 PM PDT 24
Peak memory 198836 kb
Host smart-05b3e496-3579-48ac-96e3-397e4cd3576d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783795412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.783795412
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3978969760
Short name T34
Test name
Test status
Simulation time 137379006 ps
CPU time 0.89 seconds
Started Aug 10 05:09:01 PM PDT 24
Finished Aug 10 05:09:02 PM PDT 24
Peak memory 197540 kb
Host smart-7fcd1990-65b9-4bdb-beee-073c523f0a95
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978969760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.3978969760
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3954433893
Short name T805
Test name
Test status
Simulation time 17758881 ps
CPU time 0.74 seconds
Started Aug 10 05:09:01 PM PDT 24
Finished Aug 10 05:09:01 PM PDT 24
Peak memory 197856 kb
Host smart-a4ce6fe2-04d7-4f0a-92de-8b021b909785
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954433893 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3954433893
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2380520421
Short name T93
Test name
Test status
Simulation time 14316147 ps
CPU time 0.57 seconds
Started Aug 10 05:09:02 PM PDT 24
Finished Aug 10 05:09:02 PM PDT 24
Peak memory 194204 kb
Host smart-92cf14f0-1a3b-41e6-ac17-65e774ede140
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380520421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.2380520421
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.242434843
Short name T826
Test name
Test status
Simulation time 21884277 ps
CPU time 0.57 seconds
Started Aug 10 05:08:59 PM PDT 24
Finished Aug 10 05:09:00 PM PDT 24
Peak memory 195008 kb
Host smart-d2b2117c-8eb9-4f44-9e92-0c53526faf7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242434843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.242434843
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3300098280
Short name T765
Test name
Test status
Simulation time 30753189 ps
CPU time 0.84 seconds
Started Aug 10 05:08:59 PM PDT 24
Finished Aug 10 05:09:00 PM PDT 24
Peak memory 197448 kb
Host smart-ae2c6af1-4bc8-43d3-a15e-76e5b28b0335
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300098280 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3300098280
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3225407269
Short name T732
Test name
Test status
Simulation time 71286286 ps
CPU time 1.55 seconds
Started Aug 10 05:09:00 PM PDT 24
Finished Aug 10 05:09:02 PM PDT 24
Peak memory 198996 kb
Host smart-237798f4-0a09-4b2e-9d82-13a5520b17ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225407269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.3225407269
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3691957767
Short name T46
Test name
Test status
Simulation time 450890789 ps
CPU time 1.38 seconds
Started Aug 10 05:09:01 PM PDT 24
Finished Aug 10 05:09:03 PM PDT 24
Peak memory 198104 kb
Host smart-6ec92dde-c381-4f01-9fb1-24a580e1e04b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691957767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.3691957767
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2908171882
Short name T717
Test name
Test status
Simulation time 57186684 ps
CPU time 0.8 seconds
Started Aug 10 05:08:59 PM PDT 24
Finished Aug 10 05:09:00 PM PDT 24
Peak memory 198604 kb
Host smart-a8cfaa81-6973-40a3-92df-b20abf60db0e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908171882 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.2908171882
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1723254001
Short name T770
Test name
Test status
Simulation time 46020033 ps
CPU time 0.63 seconds
Started Aug 10 05:09:02 PM PDT 24
Finished Aug 10 05:09:02 PM PDT 24
Peak memory 196316 kb
Host smart-3c263991-1b0d-40b0-871a-bbebfaf16c3f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723254001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.1723254001
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2379186214
Short name T715
Test name
Test status
Simulation time 33120078 ps
CPU time 0.64 seconds
Started Aug 10 05:09:00 PM PDT 24
Finished Aug 10 05:09:01 PM PDT 24
Peak memory 194704 kb
Host smart-054a4e92-7794-45c0-a63a-7a624e930e22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379186214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2379186214
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1050638323
Short name T83
Test name
Test status
Simulation time 76167947 ps
CPU time 0.67 seconds
Started Aug 10 05:08:58 PM PDT 24
Finished Aug 10 05:08:59 PM PDT 24
Peak memory 195284 kb
Host smart-545f8f76-743e-45d9-8a4c-385445703022
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050638323 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.1050638323
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2435538763
Short name T736
Test name
Test status
Simulation time 274394422 ps
CPU time 2.83 seconds
Started Aug 10 05:08:59 PM PDT 24
Finished Aug 10 05:09:03 PM PDT 24
Peak memory 198844 kb
Host smart-56106fc0-89a3-4a42-9292-c29e6392725c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435538763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.2435538763
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1995805106
Short name T820
Test name
Test status
Simulation time 1036298780 ps
CPU time 1.22 seconds
Started Aug 10 05:09:02 PM PDT 24
Finished Aug 10 05:09:04 PM PDT 24
Peak memory 198704 kb
Host smart-2915882b-a218-4010-86c9-fc3e477a0e08
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995805106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1995805106
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.4228658317
Short name T831
Test name
Test status
Simulation time 18253904 ps
CPU time 0.78 seconds
Started Aug 10 05:09:00 PM PDT 24
Finished Aug 10 05:09:01 PM PDT 24
Peak memory 197736 kb
Host smart-5fa19352-1b53-4627-8323-86cb8bfc028c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228658317 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.4228658317
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3817582091
Short name T830
Test name
Test status
Simulation time 19959303 ps
CPU time 0.64 seconds
Started Aug 10 05:08:59 PM PDT 24
Finished Aug 10 05:09:00 PM PDT 24
Peak memory 195880 kb
Host smart-f24fcb5a-2d5b-4c6d-8879-5ed37e718177
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817582091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.3817582091
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.935843815
Short name T794
Test name
Test status
Simulation time 11739937 ps
CPU time 0.58 seconds
Started Aug 10 05:08:59 PM PDT 24
Finished Aug 10 05:09:00 PM PDT 24
Peak memory 194468 kb
Host smart-a0b66627-2fa0-4713-ad91-d4ffb8c3861f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935843815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.935843815
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2846485319
Short name T792
Test name
Test status
Simulation time 19095967 ps
CPU time 0.66 seconds
Started Aug 10 05:09:01 PM PDT 24
Finished Aug 10 05:09:01 PM PDT 24
Peak memory 195456 kb
Host smart-cf01213d-74ea-478f-bb33-5e6010edfb35
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846485319 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.2846485319
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2568348274
Short name T840
Test name
Test status
Simulation time 41340741 ps
CPU time 2.28 seconds
Started Aug 10 05:09:02 PM PDT 24
Finished Aug 10 05:09:04 PM PDT 24
Peak memory 198756 kb
Host smart-531d0401-e319-41ff-85c2-2cefc1d9b436
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568348274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.2568348274
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3754493962
Short name T84
Test name
Test status
Simulation time 44839082 ps
CPU time 0.77 seconds
Started Aug 10 05:08:37 PM PDT 24
Finished Aug 10 05:08:38 PM PDT 24
Peak memory 196920 kb
Host smart-d945e1eb-7cff-404e-8163-051d5427c746
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754493962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.3754493962
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2424588965
Short name T737
Test name
Test status
Simulation time 81600364 ps
CPU time 2.98 seconds
Started Aug 10 05:08:39 PM PDT 24
Finished Aug 10 05:08:42 PM PDT 24
Peak memory 197852 kb
Host smart-44a2fb2a-c3a8-4fb3-b79e-3dcf65ec53ec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424588965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.2424588965
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1559776470
Short name T88
Test name
Test status
Simulation time 298067497 ps
CPU time 0.66 seconds
Started Aug 10 05:08:35 PM PDT 24
Finished Aug 10 05:08:36 PM PDT 24
Peak memory 195572 kb
Host smart-1a559ef3-79e2-4893-98ef-9d9d0c33e602
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559776470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1559776470
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2359562335
Short name T723
Test name
Test status
Simulation time 392975823 ps
CPU time 0.83 seconds
Started Aug 10 05:08:34 PM PDT 24
Finished Aug 10 05:08:35 PM PDT 24
Peak memory 198692 kb
Host smart-74b41429-a3de-406d-9bc5-33db37c5ea88
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359562335 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2359562335
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.816999414
Short name T772
Test name
Test status
Simulation time 23776644 ps
CPU time 0.56 seconds
Started Aug 10 05:08:39 PM PDT 24
Finished Aug 10 05:08:40 PM PDT 24
Peak memory 193988 kb
Host smart-d2d2619c-714e-48d2-9f50-301b18f70e08
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816999414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_
csr_rw.816999414
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.611780320
Short name T725
Test name
Test status
Simulation time 107472754 ps
CPU time 0.57 seconds
Started Aug 10 05:08:41 PM PDT 24
Finished Aug 10 05:08:41 PM PDT 24
Peak memory 194500 kb
Host smart-7452a859-f85a-4589-9f53-074e4982a5a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611780320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.611780320
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1268295783
Short name T101
Test name
Test status
Simulation time 21830889 ps
CPU time 0.65 seconds
Started Aug 10 05:08:34 PM PDT 24
Finished Aug 10 05:08:35 PM PDT 24
Peak memory 195296 kb
Host smart-7175efb8-77dc-4532-b52d-7ad0b609bb7c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268295783 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.1268295783
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1457386694
Short name T790
Test name
Test status
Simulation time 95982358 ps
CPU time 2.02 seconds
Started Aug 10 05:08:34 PM PDT 24
Finished Aug 10 05:08:36 PM PDT 24
Peak memory 198836 kb
Host smart-4f05d594-8907-402d-9e3a-0fc466468d50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457386694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1457386694
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2939478485
Short name T780
Test name
Test status
Simulation time 50276810 ps
CPU time 0.88 seconds
Started Aug 10 05:08:35 PM PDT 24
Finished Aug 10 05:08:36 PM PDT 24
Peak memory 198364 kb
Host smart-a8d1a59e-1bee-4904-b6b8-2c8fcb3c786e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939478485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.2939478485
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2202165812
Short name T762
Test name
Test status
Simulation time 45451339 ps
CPU time 0.58 seconds
Started Aug 10 05:09:02 PM PDT 24
Finished Aug 10 05:09:02 PM PDT 24
Peak memory 195024 kb
Host smart-ec83eb41-e629-40ce-9684-7fc3e162a03b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202165812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2202165812
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.1639043841
Short name T720
Test name
Test status
Simulation time 51468164 ps
CPU time 0.6 seconds
Started Aug 10 05:09:00 PM PDT 24
Finished Aug 10 05:09:01 PM PDT 24
Peak memory 194592 kb
Host smart-350fd0e3-9bf7-429f-860f-b2dd32a35a04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639043841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.1639043841
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.287244993
Short name T778
Test name
Test status
Simulation time 13784358 ps
CPU time 0.6 seconds
Started Aug 10 05:08:59 PM PDT 24
Finished Aug 10 05:09:00 PM PDT 24
Peak memory 194364 kb
Host smart-5c147dcb-150b-4dd3-b347-4f8a3a11bd3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287244993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.287244993
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.3092584737
Short name T745
Test name
Test status
Simulation time 29998373 ps
CPU time 0.57 seconds
Started Aug 10 05:08:59 PM PDT 24
Finished Aug 10 05:09:00 PM PDT 24
Peak memory 194512 kb
Host smart-147928f4-57c7-4150-8697-7b835df0ad73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092584737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.3092584737
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.253859175
Short name T787
Test name
Test status
Simulation time 14358985 ps
CPU time 0.62 seconds
Started Aug 10 05:08:57 PM PDT 24
Finished Aug 10 05:08:58 PM PDT 24
Peak memory 194488 kb
Host smart-ec10c2ba-2f69-4fe6-8696-64c6021f5cce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253859175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.253859175
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2718371619
Short name T711
Test name
Test status
Simulation time 14157298 ps
CPU time 0.59 seconds
Started Aug 10 05:08:58 PM PDT 24
Finished Aug 10 05:08:59 PM PDT 24
Peak memory 194412 kb
Host smart-7414f321-da91-4650-bfb1-ad50c56f780a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718371619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2718371619
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.2615505878
Short name T716
Test name
Test status
Simulation time 38234249 ps
CPU time 0.63 seconds
Started Aug 10 05:08:59 PM PDT 24
Finished Aug 10 05:09:00 PM PDT 24
Peak memory 195072 kb
Host smart-0e711855-d005-42ae-b352-71df6e6fd4db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615505878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2615505878
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.837227850
Short name T759
Test name
Test status
Simulation time 18303602 ps
CPU time 0.66 seconds
Started Aug 10 05:08:59 PM PDT 24
Finished Aug 10 05:09:00 PM PDT 24
Peak memory 194516 kb
Host smart-4b26f3b4-05f6-457a-803d-c4930c9b6f37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837227850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.837227850
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1650070973
Short name T836
Test name
Test status
Simulation time 15718209 ps
CPU time 0.64 seconds
Started Aug 10 05:08:59 PM PDT 24
Finished Aug 10 05:09:00 PM PDT 24
Peak memory 195212 kb
Host smart-efc37ed2-2bc1-453f-8dad-f46b04e301aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650070973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1650070973
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.3037364216
Short name T743
Test name
Test status
Simulation time 16339136 ps
CPU time 0.61 seconds
Started Aug 10 05:09:02 PM PDT 24
Finished Aug 10 05:09:03 PM PDT 24
Peak memory 194520 kb
Host smart-d513e00e-0bf2-40ed-8e00-4ac22144d6b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037364216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.3037364216
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.401710862
Short name T92
Test name
Test status
Simulation time 12602918 ps
CPU time 0.66 seconds
Started Aug 10 05:08:39 PM PDT 24
Finished Aug 10 05:08:40 PM PDT 24
Peak memory 195388 kb
Host smart-2a5f36a6-a88b-4b1d-8d9e-c52a8bf3bbbb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401710862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.gpio_csr_aliasing.401710862
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2299221852
Short name T795
Test name
Test status
Simulation time 509040245 ps
CPU time 3.31 seconds
Started Aug 10 05:08:34 PM PDT 24
Finished Aug 10 05:08:37 PM PDT 24
Peak memory 198660 kb
Host smart-7919bcdd-4c2c-4a36-ad27-6818f0bdf123
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299221852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.2299221852
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3286401775
Short name T96
Test name
Test status
Simulation time 67939527 ps
CPU time 0.59 seconds
Started Aug 10 05:08:37 PM PDT 24
Finished Aug 10 05:08:37 PM PDT 24
Peak memory 195172 kb
Host smart-8371ea8a-5724-48f8-a8e2-ebf61f4f84ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286401775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3286401775
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2268478672
Short name T764
Test name
Test status
Simulation time 51015872 ps
CPU time 0.85 seconds
Started Aug 10 05:08:35 PM PDT 24
Finished Aug 10 05:08:36 PM PDT 24
Peak memory 198572 kb
Host smart-47d3d468-0d42-4d09-901c-6375f59e0ebd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268478672 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.2268478672
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.669024231
Short name T729
Test name
Test status
Simulation time 75047355 ps
CPU time 0.59 seconds
Started Aug 10 05:08:39 PM PDT 24
Finished Aug 10 05:08:39 PM PDT 24
Peak memory 195248 kb
Host smart-d21dfb0f-5d80-4416-a489-4d8ed8ac931f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669024231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_
csr_rw.669024231
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3721583186
Short name T771
Test name
Test status
Simulation time 15500080 ps
CPU time 0.56 seconds
Started Aug 10 05:08:34 PM PDT 24
Finished Aug 10 05:08:35 PM PDT 24
Peak memory 195164 kb
Host smart-37a14073-54f5-4131-a7d5-b3ac207de5a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721583186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3721583186
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1082716977
Short name T100
Test name
Test status
Simulation time 229747167 ps
CPU time 0.74 seconds
Started Aug 10 05:08:40 PM PDT 24
Finished Aug 10 05:08:41 PM PDT 24
Peak memory 195712 kb
Host smart-0619c9cf-caa6-419e-8163-ab8ce4e695ea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082716977 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.1082716977
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2323589641
Short name T789
Test name
Test status
Simulation time 921865410 ps
CPU time 3.35 seconds
Started Aug 10 05:08:36 PM PDT 24
Finished Aug 10 05:08:40 PM PDT 24
Peak memory 198660 kb
Host smart-5500d123-43d0-4507-be33-4407d0c04ac8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323589641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.2323589641
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1203450148
Short name T811
Test name
Test status
Simulation time 274442656 ps
CPU time 1.26 seconds
Started Aug 10 05:08:37 PM PDT 24
Finished Aug 10 05:08:39 PM PDT 24
Peak memory 198656 kb
Host smart-d71720ad-eaf7-4a8c-9f92-c92502cb43b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203450148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.1203450148
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.910639588
Short name T810
Test name
Test status
Simulation time 26921516 ps
CPU time 0.58 seconds
Started Aug 10 05:09:00 PM PDT 24
Finished Aug 10 05:09:01 PM PDT 24
Peak memory 194424 kb
Host smart-5ff6267d-ac00-4420-9e07-4a3041556061
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910639588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.910639588
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.2467591266
Short name T718
Test name
Test status
Simulation time 50105685 ps
CPU time 0.6 seconds
Started Aug 10 05:08:58 PM PDT 24
Finished Aug 10 05:08:59 PM PDT 24
Peak memory 195016 kb
Host smart-97a4b7bc-468a-4947-9575-b1c1c7fc5ced
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467591266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.2467591266
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.1127655129
Short name T740
Test name
Test status
Simulation time 46559825 ps
CPU time 0.65 seconds
Started Aug 10 05:08:59 PM PDT 24
Finished Aug 10 05:09:00 PM PDT 24
Peak memory 194552 kb
Host smart-70673e1c-7331-4ed2-87e1-a3a7276719d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127655129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.1127655129
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3417327327
Short name T775
Test name
Test status
Simulation time 15263082 ps
CPU time 0.63 seconds
Started Aug 10 05:08:56 PM PDT 24
Finished Aug 10 05:08:56 PM PDT 24
Peak memory 194604 kb
Host smart-21833293-515f-414f-ba64-78d63ced099f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417327327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3417327327
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1298260626
Short name T719
Test name
Test status
Simulation time 38840790 ps
CPU time 0.69 seconds
Started Aug 10 05:09:01 PM PDT 24
Finished Aug 10 05:09:02 PM PDT 24
Peak memory 194460 kb
Host smart-a895f15f-883c-4e57-a76a-f11a55ceebd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298260626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1298260626
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.2500264668
Short name T763
Test name
Test status
Simulation time 29961030 ps
CPU time 0.68 seconds
Started Aug 10 05:09:01 PM PDT 24
Finished Aug 10 05:09:02 PM PDT 24
Peak memory 194960 kb
Host smart-032b92d4-ba61-4d53-aafc-8b8ed4ff1e7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500264668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.2500264668
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2882943467
Short name T818
Test name
Test status
Simulation time 47114334 ps
CPU time 0.59 seconds
Started Aug 10 05:09:01 PM PDT 24
Finished Aug 10 05:09:02 PM PDT 24
Peak memory 194456 kb
Host smart-b6f845cf-ab6e-4920-bfdb-fe8f6f40554b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882943467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2882943467
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.2454448079
Short name T755
Test name
Test status
Simulation time 12732315 ps
CPU time 0.67 seconds
Started Aug 10 05:09:01 PM PDT 24
Finished Aug 10 05:09:01 PM PDT 24
Peak memory 194516 kb
Host smart-9fce2094-f084-4153-96c8-bba513deb57f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454448079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.2454448079
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.2979579616
Short name T731
Test name
Test status
Simulation time 16290301 ps
CPU time 0.61 seconds
Started Aug 10 05:09:00 PM PDT 24
Finished Aug 10 05:09:01 PM PDT 24
Peak memory 194456 kb
Host smart-f880a7d6-7dc7-4ff1-81fc-b63989e6c13a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979579616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.2979579616
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.191175102
Short name T824
Test name
Test status
Simulation time 71055765 ps
CPU time 0.65 seconds
Started Aug 10 05:08:57 PM PDT 24
Finished Aug 10 05:08:58 PM PDT 24
Peak memory 194584 kb
Host smart-f0c3e2e1-92bf-4a60-8f16-aab9582a7ab9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191175102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.191175102
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1867692588
Short name T788
Test name
Test status
Simulation time 56294700 ps
CPU time 0.64 seconds
Started Aug 10 05:08:38 PM PDT 24
Finished Aug 10 05:08:39 PM PDT 24
Peak memory 194880 kb
Host smart-ad06f771-a6ef-4ea6-90e7-77a467c5a33e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867692588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.1867692588
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1279802472
Short name T734
Test name
Test status
Simulation time 35018030 ps
CPU time 1.41 seconds
Started Aug 10 05:08:39 PM PDT 24
Finished Aug 10 05:08:41 PM PDT 24
Peak memory 197632 kb
Host smart-4f732ba4-ac3e-438f-afc2-a42e5101f894
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279802472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.1279802472
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2139695372
Short name T833
Test name
Test status
Simulation time 92012035 ps
CPU time 0.62 seconds
Started Aug 10 05:08:34 PM PDT 24
Finished Aug 10 05:08:34 PM PDT 24
Peak memory 195028 kb
Host smart-362ea932-4858-4f58-90dc-3c0cbd7239bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139695372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.2139695372
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1217359022
Short name T733
Test name
Test status
Simulation time 20925339 ps
CPU time 0.97 seconds
Started Aug 10 05:08:35 PM PDT 24
Finished Aug 10 05:08:36 PM PDT 24
Peak memory 198664 kb
Host smart-032dca22-3b91-4e0c-aec9-09201d2920b2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217359022 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.1217359022
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.860809009
Short name T804
Test name
Test status
Simulation time 42870704 ps
CPU time 0.59 seconds
Started Aug 10 05:08:39 PM PDT 24
Finished Aug 10 05:08:40 PM PDT 24
Peak memory 195252 kb
Host smart-5acfa86a-e9d5-4754-b863-b9c99e5cd1cc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860809009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_
csr_rw.860809009
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.1511662999
Short name T825
Test name
Test status
Simulation time 26016735 ps
CPU time 0.6 seconds
Started Aug 10 05:08:36 PM PDT 24
Finished Aug 10 05:08:36 PM PDT 24
Peak memory 195172 kb
Host smart-3fa5d526-8dd2-4b55-adbd-617afaf9588b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511662999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.1511662999
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.678066706
Short name T769
Test name
Test status
Simulation time 34344972 ps
CPU time 0.85 seconds
Started Aug 10 05:08:34 PM PDT 24
Finished Aug 10 05:08:36 PM PDT 24
Peak memory 196632 kb
Host smart-7b67b908-c34c-46f7-b18d-2878364bd1b7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678066706 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.gpio_same_csr_outstanding.678066706
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.797838447
Short name T798
Test name
Test status
Simulation time 229912112 ps
CPU time 1.67 seconds
Started Aug 10 05:08:36 PM PDT 24
Finished Aug 10 05:08:38 PM PDT 24
Peak memory 198692 kb
Host smart-06d33907-432a-4dbb-922e-c686403febd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797838447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.797838447
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.412116056
Short name T36
Test name
Test status
Simulation time 88701623 ps
CPU time 0.82 seconds
Started Aug 10 05:08:36 PM PDT 24
Finished Aug 10 05:08:37 PM PDT 24
Peak memory 197872 kb
Host smart-f4d110dd-2e11-4861-92a1-61229aac20e9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412116056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.gpio_tl_intg_err.412116056
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.4084264921
Short name T709
Test name
Test status
Simulation time 37394492 ps
CPU time 0.59 seconds
Started Aug 10 05:09:02 PM PDT 24
Finished Aug 10 05:09:03 PM PDT 24
Peak memory 194528 kb
Host smart-b94c3e86-8963-42d5-a86a-0b805244b967
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084264921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.4084264921
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.3010714171
Short name T754
Test name
Test status
Simulation time 18741507 ps
CPU time 0.58 seconds
Started Aug 10 05:09:01 PM PDT 24
Finished Aug 10 05:09:02 PM PDT 24
Peak memory 195052 kb
Host smart-4741697a-a160-4156-8550-4bc42233e052
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010714171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.3010714171
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.2068770596
Short name T796
Test name
Test status
Simulation time 15617440 ps
CPU time 0.64 seconds
Started Aug 10 05:08:58 PM PDT 24
Finished Aug 10 05:08:59 PM PDT 24
Peak memory 194412 kb
Host smart-2b459b29-a31a-4e56-a2e7-1f1f22beeaf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068770596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.2068770596
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3291689781
Short name T802
Test name
Test status
Simulation time 39908142 ps
CPU time 0.6 seconds
Started Aug 10 05:08:58 PM PDT 24
Finished Aug 10 05:08:59 PM PDT 24
Peak memory 194460 kb
Host smart-18f3bb19-9ac3-4ab7-9af9-e1296a95dcaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291689781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3291689781
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1358762221
Short name T782
Test name
Test status
Simulation time 28009482 ps
CPU time 0.59 seconds
Started Aug 10 05:08:59 PM PDT 24
Finished Aug 10 05:09:00 PM PDT 24
Peak memory 194488 kb
Host smart-8d90995f-0dc9-4c57-b61f-185b249ada1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358762221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1358762221
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1897846396
Short name T751
Test name
Test status
Simulation time 31206968 ps
CPU time 0.63 seconds
Started Aug 10 05:08:58 PM PDT 24
Finished Aug 10 05:08:59 PM PDT 24
Peak memory 195008 kb
Host smart-243b5e6c-73a6-47e4-a797-51ed188a8345
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897846396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1897846396
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.1898706464
Short name T766
Test name
Test status
Simulation time 18894228 ps
CPU time 0.61 seconds
Started Aug 10 05:08:57 PM PDT 24
Finished Aug 10 05:08:58 PM PDT 24
Peak memory 194500 kb
Host smart-fd7eca35-f168-4128-bb5f-c75b1e806144
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898706464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.1898706464
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.871413539
Short name T710
Test name
Test status
Simulation time 15441049 ps
CPU time 0.59 seconds
Started Aug 10 05:08:59 PM PDT 24
Finished Aug 10 05:09:00 PM PDT 24
Peak memory 195160 kb
Host smart-23d6ff69-947d-4447-8944-533b0787ae33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871413539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.871413539
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.3596753690
Short name T738
Test name
Test status
Simulation time 189416768 ps
CPU time 0.6 seconds
Started Aug 10 05:08:58 PM PDT 24
Finished Aug 10 05:08:58 PM PDT 24
Peak memory 194476 kb
Host smart-7058a0eb-f421-4c73-8c68-85dcacfdbd93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596753690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.3596753690
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.914068913
Short name T822
Test name
Test status
Simulation time 14928620 ps
CPU time 0.66 seconds
Started Aug 10 05:08:58 PM PDT 24
Finished Aug 10 05:09:00 PM PDT 24
Peak memory 195244 kb
Host smart-d6c3b183-76ad-4aa7-a197-c0b506c63cae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914068913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.914068913
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.4272381996
Short name T823
Test name
Test status
Simulation time 112587775 ps
CPU time 1.3 seconds
Started Aug 10 05:08:35 PM PDT 24
Finished Aug 10 05:08:37 PM PDT 24
Peak memory 198784 kb
Host smart-320df3d6-8efc-49c9-82b2-e21796e254d3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272381996 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.4272381996
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3655202064
Short name T728
Test name
Test status
Simulation time 42750725 ps
CPU time 0.63 seconds
Started Aug 10 05:08:36 PM PDT 24
Finished Aug 10 05:08:37 PM PDT 24
Peak memory 196216 kb
Host smart-520fa0da-8de0-4f88-901e-6b9e6d89a0b5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655202064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.3655202064
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.4142624909
Short name T739
Test name
Test status
Simulation time 231357495 ps
CPU time 0.61 seconds
Started Aug 10 05:08:47 PM PDT 24
Finished Aug 10 05:08:48 PM PDT 24
Peak memory 194528 kb
Host smart-6d200ae1-d0dd-4aa6-b380-31a9616cfd97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142624909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.4142624909
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3596522636
Short name T813
Test name
Test status
Simulation time 58813877 ps
CPU time 0.71 seconds
Started Aug 10 05:08:40 PM PDT 24
Finished Aug 10 05:08:41 PM PDT 24
Peak memory 195616 kb
Host smart-d998035f-71c0-42cf-bfb2-2f61a9d492ee
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596522636 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.3596522636
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3557366786
Short name T781
Test name
Test status
Simulation time 106487099 ps
CPU time 2.28 seconds
Started Aug 10 05:08:44 PM PDT 24
Finished Aug 10 05:08:47 PM PDT 24
Peak memory 198816 kb
Host smart-4b36ab5e-7b9e-4d7f-85c7-f515cf9cffc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557366786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3557366786
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3148561816
Short name T49
Test name
Test status
Simulation time 92675964 ps
CPU time 0.84 seconds
Started Aug 10 05:08:40 PM PDT 24
Finished Aug 10 05:08:41 PM PDT 24
Peak memory 197548 kb
Host smart-c986ca22-53cf-4682-b968-4ca8d3356066
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148561816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3148561816
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.190016824
Short name T799
Test name
Test status
Simulation time 49828870 ps
CPU time 0.91 seconds
Started Aug 10 05:08:46 PM PDT 24
Finished Aug 10 05:08:47 PM PDT 24
Peak memory 198624 kb
Host smart-4c982a65-36e7-4def-94df-229f3cabe7df
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190016824 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.190016824
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1971699472
Short name T115
Test name
Test status
Simulation time 30865658 ps
CPU time 0.62 seconds
Started Aug 10 05:08:44 PM PDT 24
Finished Aug 10 05:08:45 PM PDT 24
Peak memory 195720 kb
Host smart-e76c4635-2d66-4d41-a6a2-58b9c0869787
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971699472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.1971699472
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.595417029
Short name T839
Test name
Test status
Simulation time 49728348 ps
CPU time 0.57 seconds
Started Aug 10 05:08:53 PM PDT 24
Finished Aug 10 05:08:53 PM PDT 24
Peak memory 194432 kb
Host smart-41b2046a-3dc0-4bed-a1b0-ebabd7148b38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595417029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.595417029
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.370703483
Short name T99
Test name
Test status
Simulation time 28256240 ps
CPU time 0.76 seconds
Started Aug 10 05:08:52 PM PDT 24
Finished Aug 10 05:08:53 PM PDT 24
Peak memory 197156 kb
Host smart-7c8db06e-d6b1-4e70-adc0-46dd06593d46
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370703483 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.370703483
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1190199173
Short name T807
Test name
Test status
Simulation time 227663826 ps
CPU time 2.58 seconds
Started Aug 10 05:08:45 PM PDT 24
Finished Aug 10 05:08:47 PM PDT 24
Peak memory 198724 kb
Host smart-b6e6849e-8c1e-4234-9037-0e3b71916835
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190199173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.1190199173
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3151847820
Short name T47
Test name
Test status
Simulation time 1199086657 ps
CPU time 1.3 seconds
Started Aug 10 05:08:44 PM PDT 24
Finished Aug 10 05:08:45 PM PDT 24
Peak memory 198672 kb
Host smart-3daed385-8436-4f1f-be69-d65f9fd52adc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151847820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.3151847820
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1458400672
Short name T747
Test name
Test status
Simulation time 137012309 ps
CPU time 0.86 seconds
Started Aug 10 05:08:47 PM PDT 24
Finished Aug 10 05:08:48 PM PDT 24
Peak memory 198596 kb
Host smart-08235f91-0058-4126-8bf8-b63ccbab9ea1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458400672 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.1458400672
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.4061522815
Short name T784
Test name
Test status
Simulation time 29898685 ps
CPU time 0.58 seconds
Started Aug 10 05:08:44 PM PDT 24
Finished Aug 10 05:08:45 PM PDT 24
Peak memory 195688 kb
Host smart-7a5a63a4-54f8-4e5b-8059-56e3ccfc3f2f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061522815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.4061522815
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.1490534132
Short name T800
Test name
Test status
Simulation time 27935257 ps
CPU time 0.66 seconds
Started Aug 10 05:08:45 PM PDT 24
Finished Aug 10 05:08:46 PM PDT 24
Peak memory 195200 kb
Host smart-8d07aaa7-4864-4edb-a80e-90839898d81d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490534132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.1490534132
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2332652784
Short name T87
Test name
Test status
Simulation time 103873745 ps
CPU time 0.74 seconds
Started Aug 10 05:08:46 PM PDT 24
Finished Aug 10 05:08:47 PM PDT 24
Peak memory 196440 kb
Host smart-54467179-44f9-46b8-971e-2398c59b7ec6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332652784 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.2332652784
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1275815218
Short name T817
Test name
Test status
Simulation time 92416925 ps
CPU time 2.11 seconds
Started Aug 10 05:08:45 PM PDT 24
Finished Aug 10 05:08:48 PM PDT 24
Peak memory 198752 kb
Host smart-4986a3a0-fc3b-4319-ac6d-4e6b84522065
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275815218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.1275815218
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.4058368226
Short name T774
Test name
Test status
Simulation time 341903089 ps
CPU time 0.97 seconds
Started Aug 10 05:08:45 PM PDT 24
Finished Aug 10 05:08:46 PM PDT 24
Peak memory 198100 kb
Host smart-2123640a-90bc-40d4-ad15-98f986926366
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058368226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.4058368226
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3138229467
Short name T806
Test name
Test status
Simulation time 52486331 ps
CPU time 1.47 seconds
Started Aug 10 05:08:46 PM PDT 24
Finished Aug 10 05:08:48 PM PDT 24
Peak memory 198776 kb
Host smart-cf0e9115-c629-4c13-9e59-544579e0b558
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138229467 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3138229467
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3084758714
Short name T730
Test name
Test status
Simulation time 45622028 ps
CPU time 0.57 seconds
Started Aug 10 05:08:45 PM PDT 24
Finished Aug 10 05:08:46 PM PDT 24
Peak memory 195096 kb
Host smart-8f87e183-e972-4d86-848c-6b835899e13a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084758714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3084758714
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.2402134165
Short name T814
Test name
Test status
Simulation time 11985512 ps
CPU time 0.58 seconds
Started Aug 10 05:08:48 PM PDT 24
Finished Aug 10 05:08:48 PM PDT 24
Peak memory 194484 kb
Host smart-27593eb6-3822-4c12-9449-f83f67cf2115
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402134165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.2402134165
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3417817948
Short name T89
Test name
Test status
Simulation time 182124470 ps
CPU time 0.69 seconds
Started Aug 10 05:08:47 PM PDT 24
Finished Aug 10 05:08:48 PM PDT 24
Peak memory 195592 kb
Host smart-071711c0-05eb-46d1-8262-2ee2fd1b1a26
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417817948 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.3417817948
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3112021556
Short name T714
Test name
Test status
Simulation time 20261881 ps
CPU time 0.93 seconds
Started Aug 10 05:08:47 PM PDT 24
Finished Aug 10 05:08:48 PM PDT 24
Peak memory 198660 kb
Host smart-a628b94e-dffd-4649-842f-ee9c6246e832
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112021556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.3112021556
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3476088503
Short name T48
Test name
Test status
Simulation time 98990798 ps
CPU time 1.48 seconds
Started Aug 10 05:08:46 PM PDT 24
Finished Aug 10 05:08:48 PM PDT 24
Peak memory 198748 kb
Host smart-e0fc400b-9acb-43e5-a922-c4da4b798374
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476088503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.3476088503
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3876897495
Short name T816
Test name
Test status
Simulation time 35736181 ps
CPU time 1.58 seconds
Started Aug 10 05:08:46 PM PDT 24
Finished Aug 10 05:08:48 PM PDT 24
Peak memory 198728 kb
Host smart-395d6708-9c8e-47eb-89fa-e3d7a16e09f1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876897495 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.3876897495
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3317336150
Short name T752
Test name
Test status
Simulation time 12881365 ps
CPU time 0.61 seconds
Started Aug 10 05:08:46 PM PDT 24
Finished Aug 10 05:08:47 PM PDT 24
Peak memory 194692 kb
Host smart-b6aa0959-d711-41ca-a57f-e99be915304a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317336150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3317336150
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.587121364
Short name T750
Test name
Test status
Simulation time 44385458 ps
CPU time 0.59 seconds
Started Aug 10 05:08:44 PM PDT 24
Finished Aug 10 05:08:45 PM PDT 24
Peak memory 194496 kb
Host smart-73e5bdbb-8668-41b4-8bb7-ffb388145170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587121364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.587121364
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3821452281
Short name T785
Test name
Test status
Simulation time 60764860 ps
CPU time 0.68 seconds
Started Aug 10 05:08:47 PM PDT 24
Finished Aug 10 05:08:47 PM PDT 24
Peak memory 195744 kb
Host smart-dae4b323-3b31-4d65-b4d6-07e887ea0fac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821452281 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.3821452281
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.879642642
Short name T724
Test name
Test status
Simulation time 94550201 ps
CPU time 2.35 seconds
Started Aug 10 05:08:46 PM PDT 24
Finished Aug 10 05:08:48 PM PDT 24
Peak memory 198708 kb
Host smart-6716a862-003c-46fa-8dbd-cd3a44266618
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879642642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.879642642
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3450704277
Short name T803
Test name
Test status
Simulation time 744160475 ps
CPU time 1.16 seconds
Started Aug 10 05:08:46 PM PDT 24
Finished Aug 10 05:08:47 PM PDT 24
Peak memory 198776 kb
Host smart-8643772c-ad9b-48b7-9473-b2d5119ae3cb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450704277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3450704277
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2118189610
Short name T524
Test name
Test status
Simulation time 15331228 ps
CPU time 0.63 seconds
Started Aug 10 05:14:59 PM PDT 24
Finished Aug 10 05:15:00 PM PDT 24
Peak memory 194372 kb
Host smart-69ffa127-6cf6-413b-b38b-a7f8da07d3f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118189610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2118189610
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.4269655861
Short name T314
Test name
Test status
Simulation time 16004743 ps
CPU time 0.75 seconds
Started Aug 10 05:15:00 PM PDT 24
Finished Aug 10 05:15:01 PM PDT 24
Peak memory 195248 kb
Host smart-7105fe6a-9d76-4d87-a48c-2877deee216d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269655861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.4269655861
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2892185864
Short name T24
Test name
Test status
Simulation time 1857725517 ps
CPU time 22.54 seconds
Started Aug 10 05:14:58 PM PDT 24
Finished Aug 10 05:15:20 PM PDT 24
Peak memory 196100 kb
Host smart-3545161a-82f8-4fd6-b2d6-3d9c760e308e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892185864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2892185864
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.276524843
Short name T19
Test name
Test status
Simulation time 145580222 ps
CPU time 1.03 seconds
Started Aug 10 05:14:59 PM PDT 24
Finished Aug 10 05:15:01 PM PDT 24
Peak memory 197728 kb
Host smart-2d6ff4ae-63d8-424c-bd8f-1a3693673ebb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276524843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.276524843
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.4076552459
Short name T285
Test name
Test status
Simulation time 1021735165 ps
CPU time 1.13 seconds
Started Aug 10 05:14:59 PM PDT 24
Finished Aug 10 05:15:00 PM PDT 24
Peak memory 196388 kb
Host smart-702470d0-d88b-41b5-bdf0-a2a2489629e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076552459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.4076552459
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1137961304
Short name T702
Test name
Test status
Simulation time 151944199 ps
CPU time 1.72 seconds
Started Aug 10 05:15:00 PM PDT 24
Finished Aug 10 05:15:02 PM PDT 24
Peak memory 196772 kb
Host smart-2f441329-e28f-4fee-8888-abaf6b7ed924
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137961304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1137961304
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.2086630756
Short name T645
Test name
Test status
Simulation time 389073282 ps
CPU time 2.13 seconds
Started Aug 10 05:15:00 PM PDT 24
Finished Aug 10 05:15:03 PM PDT 24
Peak memory 197708 kb
Host smart-3db41420-f754-49b0-afa5-3c600d6efbf0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086630756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
2086630756
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.2566930186
Short name T594
Test name
Test status
Simulation time 38289204 ps
CPU time 0.74 seconds
Started Aug 10 05:14:59 PM PDT 24
Finished Aug 10 05:15:00 PM PDT 24
Peak memory 196424 kb
Host smart-7e91789e-5f96-45f0-88cf-008b18733339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566930186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.2566930186
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.1062293432
Short name T258
Test name
Test status
Simulation time 165460495 ps
CPU time 0.98 seconds
Started Aug 10 05:15:00 PM PDT 24
Finished Aug 10 05:15:02 PM PDT 24
Peak memory 196324 kb
Host smart-a6114384-5428-4f20-8c58-32bdf29f106a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062293432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.1062293432
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.342674844
Short name T274
Test name
Test status
Simulation time 2695676777 ps
CPU time 5.3 seconds
Started Aug 10 05:14:59 PM PDT 24
Finished Aug 10 05:15:04 PM PDT 24
Peak memory 198596 kb
Host smart-a5d32ba1-e214-4ad1-beb6-0cc98e412703
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342674844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand
om_long_reg_writes_reg_reads.342674844
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.330355739
Short name T634
Test name
Test status
Simulation time 637746326 ps
CPU time 1.07 seconds
Started Aug 10 05:14:58 PM PDT 24
Finished Aug 10 05:15:00 PM PDT 24
Peak memory 196452 kb
Host smart-138e063e-20ab-4475-8583-94757d022ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330355739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.330355739
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.1565381581
Short name T15
Test name
Test status
Simulation time 43208133 ps
CPU time 1.35 seconds
Started Aug 10 05:15:00 PM PDT 24
Finished Aug 10 05:15:01 PM PDT 24
Peak memory 196864 kb
Host smart-d70dbd09-76b2-4935-b81b-8d860d1e17ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565381581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.1565381581
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.132829773
Short name T682
Test name
Test status
Simulation time 4616958228 ps
CPU time 118.31 seconds
Started Aug 10 05:15:01 PM PDT 24
Finished Aug 10 05:16:59 PM PDT 24
Peak memory 198776 kb
Host smart-73f1a1f0-d916-4b74-9344-6a08728a2c0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132829773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp
io_stress_all.132829773
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.2080631522
Short name T73
Test name
Test status
Simulation time 151068274788 ps
CPU time 1191 seconds
Started Aug 10 05:14:59 PM PDT 24
Finished Aug 10 05:34:50 PM PDT 24
Peak memory 198788 kb
Host smart-f34baa93-caba-4b04-b64d-1257b85fd48d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2080631522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.2080631522
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.3471330688
Short name T235
Test name
Test status
Simulation time 22163338 ps
CPU time 0.61 seconds
Started Aug 10 05:14:59 PM PDT 24
Finished Aug 10 05:15:00 PM PDT 24
Peak memory 194884 kb
Host smart-acd3ba2e-6b98-464a-b815-739ba72bf94a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471330688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.3471330688
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1436862130
Short name T431
Test name
Test status
Simulation time 28223459 ps
CPU time 0.77 seconds
Started Aug 10 05:15:01 PM PDT 24
Finished Aug 10 05:15:02 PM PDT 24
Peak memory 195660 kb
Host smart-89911035-05ed-4e98-9243-5d08a61f0e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436862130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1436862130
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.2045226436
Short name T586
Test name
Test status
Simulation time 605281191 ps
CPU time 7.27 seconds
Started Aug 10 05:14:57 PM PDT 24
Finished Aug 10 05:15:05 PM PDT 24
Peak memory 198460 kb
Host smart-59fb7fed-980d-480e-9942-0a0650121d49
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045226436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.2045226436
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.765622088
Short name T223
Test name
Test status
Simulation time 67368597 ps
CPU time 0.92 seconds
Started Aug 10 05:14:59 PM PDT 24
Finished Aug 10 05:15:00 PM PDT 24
Peak memory 197504 kb
Host smart-db723014-784d-4b8c-918d-096f5dd5d52c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765622088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.765622088
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.707384330
Short name T604
Test name
Test status
Simulation time 170040683 ps
CPU time 0.97 seconds
Started Aug 10 05:14:58 PM PDT 24
Finished Aug 10 05:14:59 PM PDT 24
Peak memory 198148 kb
Host smart-682a5626-250f-4521-8c4c-b72ded162bae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707384330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.707384330
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.3336718368
Short name T429
Test name
Test status
Simulation time 80469007 ps
CPU time 1.78 seconds
Started Aug 10 05:14:58 PM PDT 24
Finished Aug 10 05:15:00 PM PDT 24
Peak memory 197940 kb
Host smart-59a4a273-9fa7-4b2a-9f14-b8a51cfc4883
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336718368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.3336718368
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.2435231328
Short name T240
Test name
Test status
Simulation time 427051078 ps
CPU time 2.54 seconds
Started Aug 10 05:15:02 PM PDT 24
Finished Aug 10 05:15:05 PM PDT 24
Peak memory 197788 kb
Host smart-ffdcd2de-44d0-4e13-bbdb-0fb20f6b060c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435231328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
2435231328
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.1599425130
Short name T608
Test name
Test status
Simulation time 170664108 ps
CPU time 1.3 seconds
Started Aug 10 05:15:00 PM PDT 24
Finished Aug 10 05:15:02 PM PDT 24
Peak memory 197544 kb
Host smart-e6f6ebd3-11bf-43ee-ac1b-de930c0c6996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599425130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.1599425130
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.3002298868
Short name T670
Test name
Test status
Simulation time 136394104 ps
CPU time 0.87 seconds
Started Aug 10 05:15:01 PM PDT 24
Finished Aug 10 05:15:02 PM PDT 24
Peak memory 197152 kb
Host smart-a89cf07c-5cc2-4ca6-b53f-1896c492ad01
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002298868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.3002298868
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.141705432
Short name T177
Test name
Test status
Simulation time 51988058 ps
CPU time 1.22 seconds
Started Aug 10 05:15:05 PM PDT 24
Finished Aug 10 05:15:06 PM PDT 24
Peak memory 197208 kb
Host smart-d50831d2-912d-4ea6-bdd6-6463577ffd08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141705432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand
om_long_reg_writes_reg_reads.141705432
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3626925558
Short name T39
Test name
Test status
Simulation time 76277678 ps
CPU time 0.9 seconds
Started Aug 10 05:14:56 PM PDT 24
Finished Aug 10 05:14:57 PM PDT 24
Peak memory 214336 kb
Host smart-a622d553-bec2-449d-9088-8abed2373593
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626925558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3626925558
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.3676626104
Short name T503
Test name
Test status
Simulation time 88287460 ps
CPU time 1.26 seconds
Started Aug 10 05:14:59 PM PDT 24
Finished Aug 10 05:15:00 PM PDT 24
Peak memory 196408 kb
Host smart-4f64184a-b8b7-48b3-86bb-5a7f0f917168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676626104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3676626104
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.253120172
Short name T470
Test name
Test status
Simulation time 52896569 ps
CPU time 1.04 seconds
Started Aug 10 05:14:58 PM PDT 24
Finished Aug 10 05:14:59 PM PDT 24
Peak memory 196684 kb
Host smart-698bfea0-629f-4727-af36-effb4cc7f47e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253120172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.253120172
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.3323431056
Short name T338
Test name
Test status
Simulation time 3739440403 ps
CPU time 95.14 seconds
Started Aug 10 05:15:05 PM PDT 24
Finished Aug 10 05:16:40 PM PDT 24
Peak memory 198780 kb
Host smart-f74841f8-33b4-4d94-83a6-6f2d18378467
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323431056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.3323431056
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.4220055779
Short name T445
Test name
Test status
Simulation time 357710099653 ps
CPU time 1478.58 seconds
Started Aug 10 05:15:01 PM PDT 24
Finished Aug 10 05:39:39 PM PDT 24
Peak memory 198976 kb
Host smart-b14b1a70-a2b6-438f-9a1d-a56dcc4f4c1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4220055779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.4220055779
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.3741634620
Short name T219
Test name
Test status
Simulation time 13092436 ps
CPU time 0.62 seconds
Started Aug 10 05:15:25 PM PDT 24
Finished Aug 10 05:15:26 PM PDT 24
Peak memory 194392 kb
Host smart-52dbc8a0-161d-4719-89f9-87061a0b909b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741634620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.3741634620
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.694440532
Short name T548
Test name
Test status
Simulation time 49789383 ps
CPU time 0.7 seconds
Started Aug 10 05:15:22 PM PDT 24
Finished Aug 10 05:15:23 PM PDT 24
Peak memory 195748 kb
Host smart-ef50df56-bbd4-4981-b07d-df1b8f4b66c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694440532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.694440532
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.2777072410
Short name T533
Test name
Test status
Simulation time 974373965 ps
CPU time 8.3 seconds
Started Aug 10 05:15:23 PM PDT 24
Finished Aug 10 05:15:31 PM PDT 24
Peak memory 197352 kb
Host smart-19e8f758-db63-4eb4-9d58-0e4853ada201
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777072410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.2777072410
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.84537631
Short name T266
Test name
Test status
Simulation time 108652914 ps
CPU time 0.64 seconds
Started Aug 10 05:15:21 PM PDT 24
Finished Aug 10 05:15:21 PM PDT 24
Peak memory 195148 kb
Host smart-81933579-f928-411d-975c-b218d836128b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84537631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.84537631
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2903841106
Short name T321
Test name
Test status
Simulation time 432132143 ps
CPU time 1.51 seconds
Started Aug 10 05:15:25 PM PDT 24
Finished Aug 10 05:15:27 PM PDT 24
Peak memory 197552 kb
Host smart-4ae9c4a0-5dc0-4cea-9ed8-737b35343d26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903841106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2903841106
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3304710841
Short name T534
Test name
Test status
Simulation time 48201757 ps
CPU time 1.12 seconds
Started Aug 10 05:15:23 PM PDT 24
Finished Aug 10 05:15:25 PM PDT 24
Peak memory 197692 kb
Host smart-59feacb7-c1a1-40d4-9f24-b9b9f75d0ea6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304710841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3304710841
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2476752827
Short name T133
Test name
Test status
Simulation time 704439745 ps
CPU time 3.32 seconds
Started Aug 10 05:15:25 PM PDT 24
Finished Aug 10 05:15:29 PM PDT 24
Peak memory 198796 kb
Host smart-c6a75e36-ca1a-4852-9806-9f76b6b7be03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476752827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2476752827
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.161050183
Short name T372
Test name
Test status
Simulation time 62567266 ps
CPU time 1.23 seconds
Started Aug 10 05:15:23 PM PDT 24
Finished Aug 10 05:15:24 PM PDT 24
Peak memory 198624 kb
Host smart-6c2105dd-0317-4920-b57a-1270ce341038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161050183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.161050183
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.1229953356
Short name T613
Test name
Test status
Simulation time 31558408 ps
CPU time 0.85 seconds
Started Aug 10 05:15:26 PM PDT 24
Finished Aug 10 05:15:27 PM PDT 24
Peak memory 195852 kb
Host smart-fa90b845-da7b-4037-8014-0f5bc9d5e086
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229953356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.1229953356
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3248300563
Short name T409
Test name
Test status
Simulation time 427043299 ps
CPU time 2.78 seconds
Started Aug 10 05:15:23 PM PDT 24
Finished Aug 10 05:15:26 PM PDT 24
Peak memory 198516 kb
Host smart-c45b08c2-08b0-479c-a315-637b6065a0f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248300563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3248300563
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.1221644843
Short name T668
Test name
Test status
Simulation time 126211133 ps
CPU time 0.83 seconds
Started Aug 10 05:15:24 PM PDT 24
Finished Aug 10 05:15:25 PM PDT 24
Peak memory 195760 kb
Host smart-561e39b5-678b-4d14-9022-60e7055fca6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221644843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1221644843
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.836843576
Short name T689
Test name
Test status
Simulation time 60143551 ps
CPU time 1.4 seconds
Started Aug 10 05:15:28 PM PDT 24
Finished Aug 10 05:15:30 PM PDT 24
Peak memory 198632 kb
Host smart-e6709136-8a83-475d-abaa-dabf0f4ae927
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836843576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.836843576
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.201517447
Short name T190
Test name
Test status
Simulation time 1886043800 ps
CPU time 58.88 seconds
Started Aug 10 05:15:27 PM PDT 24
Finished Aug 10 05:16:26 PM PDT 24
Peak memory 198556 kb
Host smart-76f3abfd-c4e9-457a-ae41-0ac59929dfe4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201517447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.201517447
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.1429371753
Short name T3
Test name
Test status
Simulation time 542343989926 ps
CPU time 1462.71 seconds
Started Aug 10 05:15:27 PM PDT 24
Finished Aug 10 05:39:50 PM PDT 24
Peak memory 198820 kb
Host smart-b36932c3-9771-41ef-8651-26dad45a853a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1429371753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.1429371753
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3935025992
Short name T246
Test name
Test status
Simulation time 21686382 ps
CPU time 0.69 seconds
Started Aug 10 05:15:23 PM PDT 24
Finished Aug 10 05:15:24 PM PDT 24
Peak memory 195228 kb
Host smart-951436a8-886d-48ea-8fc5-ac208d7feca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935025992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3935025992
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.3567394506
Short name T226
Test name
Test status
Simulation time 201361344 ps
CPU time 10.43 seconds
Started Aug 10 05:15:27 PM PDT 24
Finished Aug 10 05:15:37 PM PDT 24
Peak memory 196288 kb
Host smart-c66578b9-e077-42f4-a906-3cc1794b450b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567394506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.3567394506
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.2939590945
Short name T683
Test name
Test status
Simulation time 24988940 ps
CPU time 0.67 seconds
Started Aug 10 05:15:25 PM PDT 24
Finished Aug 10 05:15:26 PM PDT 24
Peak memory 195672 kb
Host smart-bd6ec66d-0d93-418c-b7ba-5ab8668523f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939590945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.2939590945
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3855612933
Short name T125
Test name
Test status
Simulation time 382244611 ps
CPU time 1.41 seconds
Started Aug 10 05:15:26 PM PDT 24
Finished Aug 10 05:15:27 PM PDT 24
Peak memory 196352 kb
Host smart-8ca7a61b-2b6a-4a1d-b833-b4877bc92ea1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855612933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3855612933
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.661368066
Short name T28
Test name
Test status
Simulation time 160916808 ps
CPU time 1.87 seconds
Started Aug 10 05:15:23 PM PDT 24
Finished Aug 10 05:15:25 PM PDT 24
Peak memory 198752 kb
Host smart-317f1c5b-03f1-402b-9654-fc5ad46864c8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661368066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.gpio_intr_with_filter_rand_intr_event.661368066
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.1142053615
Short name T531
Test name
Test status
Simulation time 707731101 ps
CPU time 3.4 seconds
Started Aug 10 05:15:25 PM PDT 24
Finished Aug 10 05:15:29 PM PDT 24
Peak memory 197532 kb
Host smart-ad806e08-6a63-4e87-a0a7-3885aab4cbcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142053615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.1142053615
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.1645856205
Short name T375
Test name
Test status
Simulation time 298061254 ps
CPU time 1.08 seconds
Started Aug 10 05:15:21 PM PDT 24
Finished Aug 10 05:15:23 PM PDT 24
Peak memory 196492 kb
Host smart-edc8c7a1-73ca-4c1a-a88d-63dc5e91b45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645856205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.1645856205
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3722341321
Short name T349
Test name
Test status
Simulation time 184253910 ps
CPU time 1.03 seconds
Started Aug 10 05:15:27 PM PDT 24
Finished Aug 10 05:15:28 PM PDT 24
Peak memory 197124 kb
Host smart-64d77954-846a-4453-bbab-5bbea3dd9dbe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722341321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3722341321
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.2829507690
Short name T532
Test name
Test status
Simulation time 944947750 ps
CPU time 3.4 seconds
Started Aug 10 05:15:23 PM PDT 24
Finished Aug 10 05:15:26 PM PDT 24
Peak memory 198604 kb
Host smart-72fde70a-fd22-4383-8621-abf3481bc029
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829507690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.2829507690
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.2829564798
Short name T464
Test name
Test status
Simulation time 522879567 ps
CPU time 1.03 seconds
Started Aug 10 05:15:26 PM PDT 24
Finished Aug 10 05:15:27 PM PDT 24
Peak memory 196176 kb
Host smart-c6f00ab1-dc62-4d59-85f5-58e87ae0a34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829564798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.2829564798
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3874668888
Short name T527
Test name
Test status
Simulation time 322438532 ps
CPU time 1.28 seconds
Started Aug 10 05:15:26 PM PDT 24
Finished Aug 10 05:15:27 PM PDT 24
Peak memory 196124 kb
Host smart-cc3d03e2-9b18-4c4b-88ff-c9a4a2a8e36a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874668888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3874668888
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.64708323
Short name T4
Test name
Test status
Simulation time 70050015627 ps
CPU time 169.83 seconds
Started Aug 10 05:15:27 PM PDT 24
Finished Aug 10 05:18:17 PM PDT 24
Peak memory 198808 kb
Host smart-f1ced3f8-b310-4528-9f9a-c3aca7838148
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64708323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gp
io_stress_all.64708323
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1093435756
Short name T175
Test name
Test status
Simulation time 124294664 ps
CPU time 0.62 seconds
Started Aug 10 05:15:43 PM PDT 24
Finished Aug 10 05:15:43 PM PDT 24
Peak memory 194684 kb
Host smart-2d4ae9dd-6254-45c2-959a-7c1858ff7097
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093435756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1093435756
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2457364727
Short name T516
Test name
Test status
Simulation time 75564157 ps
CPU time 0.91 seconds
Started Aug 10 05:15:40 PM PDT 24
Finished Aug 10 05:15:42 PM PDT 24
Peak memory 196448 kb
Host smart-deb68729-2bc5-4ed6-a699-2a4dd4a89f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457364727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2457364727
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2449016360
Short name T225
Test name
Test status
Simulation time 1817014228 ps
CPU time 16.64 seconds
Started Aug 10 05:15:32 PM PDT 24
Finished Aug 10 05:15:49 PM PDT 24
Peak memory 197496 kb
Host smart-8d736c44-90eb-4b28-9398-4216a57fac37
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449016360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2449016360
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.2688270669
Short name T684
Test name
Test status
Simulation time 32584687 ps
CPU time 0.64 seconds
Started Aug 10 05:15:41 PM PDT 24
Finished Aug 10 05:15:42 PM PDT 24
Peak memory 195024 kb
Host smart-c7f48bf6-8f09-4d93-aa5e-6563b1415ac0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688270669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.2688270669
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.3586842663
Short name T138
Test name
Test status
Simulation time 63964819 ps
CPU time 1.02 seconds
Started Aug 10 05:15:43 PM PDT 24
Finished Aug 10 05:15:44 PM PDT 24
Peak memory 196296 kb
Host smart-d3b215b3-465a-4e4d-af69-b3f7dd8800e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586842663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.3586842663
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.253361434
Short name T334
Test name
Test status
Simulation time 41617933 ps
CPU time 1.68 seconds
Started Aug 10 05:15:41 PM PDT 24
Finished Aug 10 05:15:43 PM PDT 24
Peak memory 197316 kb
Host smart-25109a64-1749-4a45-84cd-cb68f3a8dca9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253361434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.253361434
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1521443749
Short name T152
Test name
Test status
Simulation time 75457182 ps
CPU time 2.3 seconds
Started Aug 10 05:15:41 PM PDT 24
Finished Aug 10 05:15:43 PM PDT 24
Peak memory 197612 kb
Host smart-1c6fdc6b-60a8-4226-b79c-5cba8057fa10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521443749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1521443749
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.1569454982
Short name T614
Test name
Test status
Simulation time 263273756 ps
CPU time 1.18 seconds
Started Aug 10 05:15:32 PM PDT 24
Finished Aug 10 05:15:33 PM PDT 24
Peak memory 196620 kb
Host smart-ed134c1a-9882-4c1b-9684-c53031ca572a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569454982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.1569454982
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.4290963902
Short name T308
Test name
Test status
Simulation time 203856247 ps
CPU time 1.17 seconds
Started Aug 10 05:15:43 PM PDT 24
Finished Aug 10 05:15:44 PM PDT 24
Peak memory 198608 kb
Host smart-c064ce12-b853-4fba-bf52-80d51fdaf2f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290963902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.4290963902
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2793214768
Short name T700
Test name
Test status
Simulation time 205443068 ps
CPU time 5.05 seconds
Started Aug 10 05:15:32 PM PDT 24
Finished Aug 10 05:15:38 PM PDT 24
Peak memory 198516 kb
Host smart-e6da4264-0733-458c-bf7b-4ad34edffb98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793214768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2793214768
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.23216120
Short name T703
Test name
Test status
Simulation time 60609717 ps
CPU time 1.08 seconds
Started Aug 10 05:15:27 PM PDT 24
Finished Aug 10 05:15:28 PM PDT 24
Peak memory 196160 kb
Host smart-98b01b5d-688d-4f51-9253-14e36093235a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23216120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.23216120
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.1868662680
Short name T500
Test name
Test status
Simulation time 505378292 ps
CPU time 1.19 seconds
Started Aug 10 05:15:28 PM PDT 24
Finished Aug 10 05:15:29 PM PDT 24
Peak memory 198604 kb
Host smart-31cd8f9b-5e2f-489b-acb9-6df31097fc5f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868662680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.1868662680
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.1179541692
Short name T5
Test name
Test status
Simulation time 128119809031 ps
CPU time 221.12 seconds
Started Aug 10 05:15:39 PM PDT 24
Finished Aug 10 05:19:21 PM PDT 24
Peak memory 198688 kb
Host smart-6f602761-5ba6-4c24-b048-c65f1b82c7b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179541692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.1179541692
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.3795612723
Short name T483
Test name
Test status
Simulation time 518388103948 ps
CPU time 2200.18 seconds
Started Aug 10 05:15:40 PM PDT 24
Finished Aug 10 05:52:21 PM PDT 24
Peak memory 198776 kb
Host smart-a73df211-693d-4a22-9df0-a55410fa024b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3795612723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.3795612723
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1768241856
Short name T479
Test name
Test status
Simulation time 17208473 ps
CPU time 0.57 seconds
Started Aug 10 05:15:42 PM PDT 24
Finished Aug 10 05:15:43 PM PDT 24
Peak memory 194432 kb
Host smart-10c6ccb7-14cc-4c16-9668-0ac6576cdc94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768241856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1768241856
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.1516503993
Short name T411
Test name
Test status
Simulation time 211612930 ps
CPU time 0.87 seconds
Started Aug 10 05:15:40 PM PDT 24
Finished Aug 10 05:15:41 PM PDT 24
Peak memory 197048 kb
Host smart-990f66d7-f4c2-4b05-ba0f-5aba8aed05e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516503993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.1516503993
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.732074654
Short name T301
Test name
Test status
Simulation time 856490344 ps
CPU time 22.57 seconds
Started Aug 10 05:15:44 PM PDT 24
Finished Aug 10 05:16:07 PM PDT 24
Peak memory 197596 kb
Host smart-40bda8e3-cf7a-4f06-950c-bf38e07f7ae2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732074654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stres
s.732074654
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.3514014067
Short name T248
Test name
Test status
Simulation time 142693575 ps
CPU time 1.01 seconds
Started Aug 10 05:15:39 PM PDT 24
Finished Aug 10 05:15:40 PM PDT 24
Peak memory 197672 kb
Host smart-8a154f5d-dcc5-4a96-ae2c-870d98ed9dad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514014067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.3514014067
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.1983429156
Short name T415
Test name
Test status
Simulation time 22538006 ps
CPU time 0.84 seconds
Started Aug 10 05:15:40 PM PDT 24
Finished Aug 10 05:15:41 PM PDT 24
Peak memory 196068 kb
Host smart-4b61b9b8-2b6b-4ff2-af03-0c5c80fd9977
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983429156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.1983429156
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3761314856
Short name T254
Test name
Test status
Simulation time 45546444 ps
CPU time 1.91 seconds
Started Aug 10 05:15:42 PM PDT 24
Finished Aug 10 05:15:44 PM PDT 24
Peak memory 198756 kb
Host smart-bee519f4-ed8f-461b-a146-60ecab6a6964
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761314856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3761314856
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.2199648807
Short name T663
Test name
Test status
Simulation time 222270106 ps
CPU time 2.5 seconds
Started Aug 10 05:15:42 PM PDT 24
Finished Aug 10 05:15:45 PM PDT 24
Peak memory 198648 kb
Host smart-f46e4185-034b-42f1-99d1-c89d0aeed564
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199648807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.2199648807
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.453607826
Short name T461
Test name
Test status
Simulation time 201847588 ps
CPU time 1.41 seconds
Started Aug 10 05:15:45 PM PDT 24
Finished Aug 10 05:15:47 PM PDT 24
Peak memory 197156 kb
Host smart-3d56ec14-1e74-4e0c-b1f7-60adaca58711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453607826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.453607826
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.1069814017
Short name T166
Test name
Test status
Simulation time 83385878 ps
CPU time 0.72 seconds
Started Aug 10 05:15:45 PM PDT 24
Finished Aug 10 05:15:46 PM PDT 24
Peak memory 195920 kb
Host smart-1ec9bbbe-de28-4629-ae2c-de2a2ee7c192
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069814017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.1069814017
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2722065321
Short name T561
Test name
Test status
Simulation time 776748836 ps
CPU time 3.74 seconds
Started Aug 10 05:15:41 PM PDT 24
Finished Aug 10 05:15:45 PM PDT 24
Peak memory 198420 kb
Host smart-9633ca5b-abde-42a0-a67f-8029f944c9a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722065321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.2722065321
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2610428102
Short name T149
Test name
Test status
Simulation time 40669655 ps
CPU time 0.77 seconds
Started Aug 10 05:15:41 PM PDT 24
Finished Aug 10 05:15:42 PM PDT 24
Peak memory 196404 kb
Host smart-d56ffcb4-f298-4d52-a135-866fbfc2358c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610428102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2610428102
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1421144069
Short name T268
Test name
Test status
Simulation time 115923948 ps
CPU time 1.01 seconds
Started Aug 10 05:15:40 PM PDT 24
Finished Aug 10 05:15:41 PM PDT 24
Peak memory 196144 kb
Host smart-1f48293d-b9fd-4bc3-bcf0-97bcca75ab75
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421144069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1421144069
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2751228913
Short name T416
Test name
Test status
Simulation time 12774164410 ps
CPU time 156.51 seconds
Started Aug 10 05:15:45 PM PDT 24
Finished Aug 10 05:18:22 PM PDT 24
Peak memory 198748 kb
Host smart-968dff26-3c72-4160-a533-1e1ec3aed2ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751228913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2751228913
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.2209989001
Short name T271
Test name
Test status
Simulation time 31286579 ps
CPU time 0.6 seconds
Started Aug 10 05:15:40 PM PDT 24
Finished Aug 10 05:15:40 PM PDT 24
Peak memory 194536 kb
Host smart-e3010acf-211c-4b49-a7cd-d67129e9a464
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209989001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.2209989001
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.234423801
Short name T193
Test name
Test status
Simulation time 47187529 ps
CPU time 0.87 seconds
Started Aug 10 05:15:41 PM PDT 24
Finished Aug 10 05:15:42 PM PDT 24
Peak memory 195716 kb
Host smart-7de36320-ed3c-417d-a9d1-a0e1bc289520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234423801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.234423801
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.3607052279
Short name T283
Test name
Test status
Simulation time 1323125417 ps
CPU time 19.85 seconds
Started Aug 10 05:15:40 PM PDT 24
Finished Aug 10 05:16:00 PM PDT 24
Peak memory 196032 kb
Host smart-1cdb59d1-76d4-4bc8-b452-9eec0a633515
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607052279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.3607052279
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.373251213
Short name T21
Test name
Test status
Simulation time 152050499 ps
CPU time 1.05 seconds
Started Aug 10 05:15:41 PM PDT 24
Finished Aug 10 05:15:42 PM PDT 24
Peak memory 198464 kb
Host smart-bcdc420e-14b9-4f87-8f58-2fd254e1f96a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373251213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.373251213
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2914013520
Short name T12
Test name
Test status
Simulation time 48161213 ps
CPU time 0.99 seconds
Started Aug 10 05:15:43 PM PDT 24
Finished Aug 10 05:15:44 PM PDT 24
Peak memory 196076 kb
Host smart-6b341019-e03a-4612-b7e4-922a53fb6349
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914013520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2914013520
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3631327647
Short name T202
Test name
Test status
Simulation time 200274826 ps
CPU time 2.21 seconds
Started Aug 10 05:15:45 PM PDT 24
Finished Aug 10 05:15:48 PM PDT 24
Peak memory 198356 kb
Host smart-786e043a-19eb-4404-9ad8-de8bff1b95e1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631327647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3631327647
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1636773247
Short name T82
Test name
Test status
Simulation time 256971546 ps
CPU time 1.56 seconds
Started Aug 10 05:15:41 PM PDT 24
Finished Aug 10 05:15:43 PM PDT 24
Peak memory 196412 kb
Host smart-ac8409db-19cb-4a8a-a50a-d20d823a648d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636773247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1636773247
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.594796241
Short name T643
Test name
Test status
Simulation time 70425362 ps
CPU time 1.29 seconds
Started Aug 10 05:15:44 PM PDT 24
Finished Aug 10 05:15:45 PM PDT 24
Peak memory 197472 kb
Host smart-7d41cd6c-9b14-4fac-999a-8136e5a069e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594796241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.594796241
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.92239812
Short name T570
Test name
Test status
Simulation time 190896684 ps
CPU time 1.18 seconds
Started Aug 10 05:15:42 PM PDT 24
Finished Aug 10 05:15:43 PM PDT 24
Peak memory 197708 kb
Host smart-c57076eb-81dd-457b-9f78-c4846ba242b2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92239812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullup_
pulldown.92239812
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.4163539173
Short name T324
Test name
Test status
Simulation time 123710614 ps
CPU time 5.59 seconds
Started Aug 10 05:15:44 PM PDT 24
Finished Aug 10 05:15:49 PM PDT 24
Peak memory 198404 kb
Host smart-32160f56-e676-408b-80b8-4f3a49ed0030
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163539173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.4163539173
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.2962009532
Short name T379
Test name
Test status
Simulation time 50214632 ps
CPU time 0.84 seconds
Started Aug 10 05:15:43 PM PDT 24
Finished Aug 10 05:15:44 PM PDT 24
Peak memory 196560 kb
Host smart-b660daa5-123a-4351-8309-7976343114c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962009532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.2962009532
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1748043430
Short name T603
Test name
Test status
Simulation time 38587437 ps
CPU time 1.04 seconds
Started Aug 10 05:15:42 PM PDT 24
Finished Aug 10 05:15:43 PM PDT 24
Peak memory 196964 kb
Host smart-2856167d-5296-4e51-aa4b-fd876c51a772
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748043430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1748043430
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.1122218548
Short name T292
Test name
Test status
Simulation time 13593450012 ps
CPU time 50.06 seconds
Started Aug 10 05:15:40 PM PDT 24
Finished Aug 10 05:16:30 PM PDT 24
Peak memory 198752 kb
Host smart-e03eecda-a2fc-4849-bf8e-46ef66b25729
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122218548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.1122218548
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.2430023105
Short name T471
Test name
Test status
Simulation time 947271953469 ps
CPU time 2453.62 seconds
Started Aug 10 05:15:45 PM PDT 24
Finished Aug 10 05:56:39 PM PDT 24
Peak memory 198824 kb
Host smart-498d4592-aa3f-431f-9fa2-86ee66afeee7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2430023105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.2430023105
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.2901162285
Short name T41
Test name
Test status
Simulation time 41933800 ps
CPU time 0.59 seconds
Started Aug 10 05:15:46 PM PDT 24
Finished Aug 10 05:15:46 PM PDT 24
Peak memory 194676 kb
Host smart-65288499-99d8-4be2-8b67-edc62b199a64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901162285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2901162285
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1348928521
Short name T536
Test name
Test status
Simulation time 25512251 ps
CPU time 0.69 seconds
Started Aug 10 05:15:44 PM PDT 24
Finished Aug 10 05:15:45 PM PDT 24
Peak memory 195240 kb
Host smart-db1e55f8-e954-495e-8606-079a28830cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348928521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1348928521
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.378448299
Short name T565
Test name
Test status
Simulation time 657415073 ps
CPU time 8.92 seconds
Started Aug 10 05:15:43 PM PDT 24
Finished Aug 10 05:15:52 PM PDT 24
Peak memory 197492 kb
Host smart-249b67c6-01bc-4ad4-a8a0-c8ed514f8826
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378448299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stres
s.378448299
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1537426968
Short name T580
Test name
Test status
Simulation time 49449205 ps
CPU time 0.88 seconds
Started Aug 10 05:15:44 PM PDT 24
Finished Aug 10 05:15:46 PM PDT 24
Peak memory 196428 kb
Host smart-c16dffc1-143a-4ef6-86fa-e762789c1581
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537426968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1537426968
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.311362468
Short name T346
Test name
Test status
Simulation time 41667956 ps
CPU time 0.96 seconds
Started Aug 10 05:15:46 PM PDT 24
Finished Aug 10 05:15:47 PM PDT 24
Peak memory 196384 kb
Host smart-1f42ca6e-34ac-4ef3-a329-0d35d4059517
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311362468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.311362468
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.310052649
Short name T278
Test name
Test status
Simulation time 80733026 ps
CPU time 3 seconds
Started Aug 10 05:15:47 PM PDT 24
Finished Aug 10 05:15:50 PM PDT 24
Peak memory 198672 kb
Host smart-9ec18b61-52f4-492d-b7e0-ffa799a4f327
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310052649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.gpio_intr_with_filter_rand_intr_event.310052649
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.266490077
Short name T209
Test name
Test status
Simulation time 895441039 ps
CPU time 2.34 seconds
Started Aug 10 05:15:44 PM PDT 24
Finished Aug 10 05:15:46 PM PDT 24
Peak memory 197576 kb
Host smart-f135b119-acb9-440e-992f-745da53e6f3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266490077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger.
266490077
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.3605195485
Short name T106
Test name
Test status
Simulation time 240841933 ps
CPU time 0.82 seconds
Started Aug 10 05:15:45 PM PDT 24
Finished Aug 10 05:15:46 PM PDT 24
Peak memory 195884 kb
Host smart-254a919e-11ef-44f0-a48d-55bb5032eca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605195485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.3605195485
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.4182594867
Short name T454
Test name
Test status
Simulation time 35884181 ps
CPU time 0.95 seconds
Started Aug 10 05:15:44 PM PDT 24
Finished Aug 10 05:15:45 PM PDT 24
Peak memory 196576 kb
Host smart-de1d64ca-6f7f-4c96-a6cd-f61b38dc2a28
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182594867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.4182594867
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.1896244610
Short name T10
Test name
Test status
Simulation time 5693162102 ps
CPU time 6.74 seconds
Started Aug 10 05:15:47 PM PDT 24
Finished Aug 10 05:15:53 PM PDT 24
Peak memory 198536 kb
Host smart-865679d5-f2a9-43a9-9c94-114f9f52d808
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896244610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.1896244610
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.631878486
Short name T216
Test name
Test status
Simulation time 117275108 ps
CPU time 1.45 seconds
Started Aug 10 05:15:44 PM PDT 24
Finished Aug 10 05:15:46 PM PDT 24
Peak memory 197400 kb
Host smart-860fac3d-35c4-4175-b42c-18319ce78874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631878486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.631878486
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.1012495509
Short name T13
Test name
Test status
Simulation time 64639510 ps
CPU time 1.01 seconds
Started Aug 10 05:15:44 PM PDT 24
Finished Aug 10 05:15:45 PM PDT 24
Peak memory 196088 kb
Host smart-c9285f86-5e2b-4365-aaaf-53716f1d7eb6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012495509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.1012495509
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.2744044896
Short name T306
Test name
Test status
Simulation time 3768833882 ps
CPU time 44.31 seconds
Started Aug 10 05:15:42 PM PDT 24
Finished Aug 10 05:16:27 PM PDT 24
Peak memory 198720 kb
Host smart-2ee7b282-fa11-4219-96ed-6f088e877e4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744044896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.2744044896
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.27957136
Short name T62
Test name
Test status
Simulation time 146256556401 ps
CPU time 1780.63 seconds
Started Aug 10 05:15:42 PM PDT 24
Finished Aug 10 05:45:23 PM PDT 24
Peak memory 198920 kb
Host smart-19cb03a0-9776-418f-9d28-f2e01f39a044
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=27957136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.27957136
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2423221188
Short name T558
Test name
Test status
Simulation time 24459805 ps
CPU time 0.58 seconds
Started Aug 10 05:15:44 PM PDT 24
Finished Aug 10 05:15:44 PM PDT 24
Peak memory 194380 kb
Host smart-7e3d44b9-2dba-4500-bfc9-17534c0a5508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423221188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2423221188
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3307954226
Short name T662
Test name
Test status
Simulation time 128701048 ps
CPU time 0.73 seconds
Started Aug 10 05:15:42 PM PDT 24
Finished Aug 10 05:15:42 PM PDT 24
Peak memory 194668 kb
Host smart-2808a91c-6d93-482d-ad2a-3c2ccc51cb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307954226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3307954226
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.4215356123
Short name T665
Test name
Test status
Simulation time 397640945 ps
CPU time 22.53 seconds
Started Aug 10 05:15:44 PM PDT 24
Finished Aug 10 05:16:07 PM PDT 24
Peak memory 198556 kb
Host smart-7d0d8cf6-3fe7-4014-a30f-2dc0607f4110
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215356123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.4215356123
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.3267807995
Short name T432
Test name
Test status
Simulation time 85569821 ps
CPU time 0.68 seconds
Started Aug 10 05:15:43 PM PDT 24
Finished Aug 10 05:15:44 PM PDT 24
Peak memory 195896 kb
Host smart-febf9f6e-d6f6-45ae-8ad8-78159e0abeb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267807995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.3267807995
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.2177915843
Short name T590
Test name
Test status
Simulation time 86319390 ps
CPU time 0.74 seconds
Started Aug 10 05:15:44 PM PDT 24
Finished Aug 10 05:15:45 PM PDT 24
Peak memory 195936 kb
Host smart-1dbf2739-79ea-4a45-a2c7-46be0424d1a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177915843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.2177915843
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.1813064898
Short name T357
Test name
Test status
Simulation time 51011570 ps
CPU time 2.06 seconds
Started Aug 10 05:15:43 PM PDT 24
Finished Aug 10 05:15:46 PM PDT 24
Peak memory 198648 kb
Host smart-78e4f1b4-3f1f-4671-884c-9bacd6e3e866
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813064898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.1813064898
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.1422876319
Short name T476
Test name
Test status
Simulation time 361870562 ps
CPU time 2.92 seconds
Started Aug 10 05:15:44 PM PDT 24
Finished Aug 10 05:15:47 PM PDT 24
Peak memory 198580 kb
Host smart-3d8180fb-ff0a-4ed4-b5d0-7ff51499090b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422876319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.1422876319
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.1320491552
Short name T249
Test name
Test status
Simulation time 208395803 ps
CPU time 1.15 seconds
Started Aug 10 05:15:43 PM PDT 24
Finished Aug 10 05:15:44 PM PDT 24
Peak memory 197332 kb
Host smart-44da696a-b271-4ff6-9c12-a239aedd1d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320491552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.1320491552
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.1874241387
Short name T273
Test name
Test status
Simulation time 20313988 ps
CPU time 0.87 seconds
Started Aug 10 05:15:47 PM PDT 24
Finished Aug 10 05:15:49 PM PDT 24
Peak memory 197916 kb
Host smart-824d6670-b5e9-4cbd-99b9-2ad6e2ab227e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874241387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.1874241387
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.955757141
Short name T674
Test name
Test status
Simulation time 164774599 ps
CPU time 1.65 seconds
Started Aug 10 05:15:44 PM PDT 24
Finished Aug 10 05:15:45 PM PDT 24
Peak memory 198520 kb
Host smart-808edb75-bd05-41f6-8476-9c1920960d4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955757141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ran
dom_long_reg_writes_reg_reads.955757141
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.3441972854
Short name T280
Test name
Test status
Simulation time 167773884 ps
CPU time 1.37 seconds
Started Aug 10 05:15:44 PM PDT 24
Finished Aug 10 05:15:46 PM PDT 24
Peak memory 198568 kb
Host smart-356c7a3c-d9e9-4968-b9bf-8de4092fb810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441972854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.3441972854
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.1133941310
Short name T305
Test name
Test status
Simulation time 59070423 ps
CPU time 1.06 seconds
Started Aug 10 05:15:43 PM PDT 24
Finished Aug 10 05:15:45 PM PDT 24
Peak memory 197436 kb
Host smart-080c1a25-4cc2-453a-bee9-e9530739329c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133941310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.1133941310
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.2938772417
Short name T134
Test name
Test status
Simulation time 7734518773 ps
CPU time 110.79 seconds
Started Aug 10 05:15:49 PM PDT 24
Finished Aug 10 05:17:40 PM PDT 24
Peak memory 198804 kb
Host smart-eb0d4667-7e60-4731-9ef4-9ddf1c21ae50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938772417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.2938772417
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.4065659839
Short name T669
Test name
Test status
Simulation time 19908776 ps
CPU time 0.57 seconds
Started Aug 10 05:15:44 PM PDT 24
Finished Aug 10 05:15:46 PM PDT 24
Peak memory 195208 kb
Host smart-65f8f14b-0a1d-4b0e-a45a-49dd30aa50da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065659839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.4065659839
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.4210438750
Short name T353
Test name
Test status
Simulation time 133551907 ps
CPU time 0.82 seconds
Started Aug 10 05:15:45 PM PDT 24
Finished Aug 10 05:15:46 PM PDT 24
Peak memory 196600 kb
Host smart-ef8bde69-3c34-4772-bde2-1c58ae3f9eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210438750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.4210438750
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.3660029960
Short name T201
Test name
Test status
Simulation time 1187505461 ps
CPU time 15.2 seconds
Started Aug 10 05:15:48 PM PDT 24
Finished Aug 10 05:16:04 PM PDT 24
Peak memory 196900 kb
Host smart-17f86ba2-57a6-4c47-9159-4bb22a534604
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660029960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.3660029960
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.3286025073
Short name T477
Test name
Test status
Simulation time 79501260 ps
CPU time 1.05 seconds
Started Aug 10 05:15:43 PM PDT 24
Finished Aug 10 05:15:44 PM PDT 24
Peak memory 198480 kb
Host smart-1cb34a61-6a09-4747-9458-63a1dfcfd483
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286025073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.3286025073
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3288556092
Short name T666
Test name
Test status
Simulation time 77113704 ps
CPU time 1.37 seconds
Started Aug 10 05:15:43 PM PDT 24
Finished Aug 10 05:15:44 PM PDT 24
Peak memory 196456 kb
Host smart-6c966c6d-ee58-4e97-a9a1-0888d54e6a76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288556092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3288556092
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.2683557997
Short name T329
Test name
Test status
Simulation time 66864195 ps
CPU time 0.91 seconds
Started Aug 10 05:15:43 PM PDT 24
Finished Aug 10 05:15:44 PM PDT 24
Peak memory 196436 kb
Host smart-60dabbc9-6bfa-40f8-b09e-24bb4eab642f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683557997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.2683557997
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.597428286
Short name T304
Test name
Test status
Simulation time 709284472 ps
CPU time 2.56 seconds
Started Aug 10 05:15:44 PM PDT 24
Finished Aug 10 05:15:47 PM PDT 24
Peak memory 197044 kb
Host smart-e78120cc-122c-4499-a428-558286973916
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597428286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
597428286
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.507506542
Short name T224
Test name
Test status
Simulation time 102478965 ps
CPU time 0.89 seconds
Started Aug 10 05:15:44 PM PDT 24
Finished Aug 10 05:15:45 PM PDT 24
Peak memory 196632 kb
Host smart-9ad6c64e-96cd-420d-b031-f142b4fcb888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507506542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.507506542
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.281791985
Short name T403
Test name
Test status
Simulation time 18903001 ps
CPU time 0.76 seconds
Started Aug 10 05:15:44 PM PDT 24
Finished Aug 10 05:15:45 PM PDT 24
Peak memory 196040 kb
Host smart-82e3530d-3420-48e1-8fd4-f27c7cf41a9b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281791985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup
_pulldown.281791985
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3067626648
Short name T426
Test name
Test status
Simulation time 90080020 ps
CPU time 4.16 seconds
Started Aug 10 05:15:44 PM PDT 24
Finished Aug 10 05:15:49 PM PDT 24
Peak memory 198576 kb
Host smart-71789069-d101-41d2-9eb7-71b1665462a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067626648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3067626648
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.61017160
Short name T169
Test name
Test status
Simulation time 216539078 ps
CPU time 1.5 seconds
Started Aug 10 05:15:45 PM PDT 24
Finished Aug 10 05:15:47 PM PDT 24
Peak memory 197448 kb
Host smart-ffc4d529-d902-46c3-9bce-3caa316723d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61017160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.61017160
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1069198836
Short name T354
Test name
Test status
Simulation time 94267702 ps
CPU time 1.58 seconds
Started Aug 10 05:15:45 PM PDT 24
Finished Aug 10 05:15:47 PM PDT 24
Peak memory 197184 kb
Host smart-00a694c4-6178-4553-b129-15410a84c2df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069198836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1069198836
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.3992231634
Short name T370
Test name
Test status
Simulation time 10315168047 ps
CPU time 143.78 seconds
Started Aug 10 05:15:47 PM PDT 24
Finished Aug 10 05:18:11 PM PDT 24
Peak memory 198824 kb
Host smart-ac9d22e7-4055-4737-90a8-80b0f18f00b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992231634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.3992231634
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.3365344724
Short name T76
Test name
Test status
Simulation time 57678456068 ps
CPU time 969.09 seconds
Started Aug 10 05:15:42 PM PDT 24
Finished Aug 10 05:31:51 PM PDT 24
Peak memory 198908 kb
Host smart-f2952253-0f4e-45e0-a74d-5f30496e864e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3365344724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.3365344724
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.2339055412
Short name T362
Test name
Test status
Simulation time 97437329 ps
CPU time 0.58 seconds
Started Aug 10 05:15:44 PM PDT 24
Finished Aug 10 05:15:45 PM PDT 24
Peak memory 194504 kb
Host smart-90761ec0-138a-4543-bac8-77579952521e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339055412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.2339055412
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2371821039
Short name T517
Test name
Test status
Simulation time 153157651 ps
CPU time 1 seconds
Started Aug 10 05:15:46 PM PDT 24
Finished Aug 10 05:15:47 PM PDT 24
Peak memory 197200 kb
Host smart-1f385dc7-c97c-4400-8c64-0edc1ed59092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371821039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2371821039
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.2301597097
Short name T478
Test name
Test status
Simulation time 391315625 ps
CPU time 6.34 seconds
Started Aug 10 05:15:42 PM PDT 24
Finished Aug 10 05:15:48 PM PDT 24
Peak memory 198616 kb
Host smart-2ecec816-8835-4602-9607-f72d61572270
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301597097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.2301597097
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.1290507042
Short name T501
Test name
Test status
Simulation time 113711245 ps
CPU time 0.7 seconds
Started Aug 10 05:15:47 PM PDT 24
Finished Aug 10 05:15:48 PM PDT 24
Peak memory 195868 kb
Host smart-f4c4aad2-7219-4ca6-b4da-786001d62a8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290507042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.1290507042
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2026431180
Short name T557
Test name
Test status
Simulation time 295820845 ps
CPU time 1.25 seconds
Started Aug 10 05:15:46 PM PDT 24
Finished Aug 10 05:15:47 PM PDT 24
Peak memory 197396 kb
Host smart-fc9efdc9-a176-4e08-8f53-b501bd58370b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026431180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2026431180
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.433669280
Short name T141
Test name
Test status
Simulation time 168934825 ps
CPU time 1.88 seconds
Started Aug 10 05:15:45 PM PDT 24
Finished Aug 10 05:15:47 PM PDT 24
Peak memory 198680 kb
Host smart-9f9f1f08-3401-42fa-811d-ed75695573cf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433669280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.gpio_intr_with_filter_rand_intr_event.433669280
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3469697232
Short name T61
Test name
Test status
Simulation time 1560603985 ps
CPU time 2.93 seconds
Started Aug 10 05:15:45 PM PDT 24
Finished Aug 10 05:15:48 PM PDT 24
Peak memory 197864 kb
Host smart-f5c3418d-0ef7-4b77-8414-ba9a35dc8f50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469697232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3469697232
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.3775942307
Short name T317
Test name
Test status
Simulation time 23889643 ps
CPU time 0.96 seconds
Started Aug 10 05:15:44 PM PDT 24
Finished Aug 10 05:15:46 PM PDT 24
Peak memory 196584 kb
Host smart-2d706d06-7d59-4771-b052-587a865db854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775942307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.3775942307
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1368201485
Short name T504
Test name
Test status
Simulation time 73190077 ps
CPU time 1.44 seconds
Started Aug 10 05:15:45 PM PDT 24
Finished Aug 10 05:15:47 PM PDT 24
Peak memory 197580 kb
Host smart-7b2d896a-148c-4245-9000-301bee1b0758
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368201485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1368201485
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1820608498
Short name T233
Test name
Test status
Simulation time 90614807 ps
CPU time 4.05 seconds
Started Aug 10 05:15:43 PM PDT 24
Finished Aug 10 05:15:48 PM PDT 24
Peak memory 198236 kb
Host smart-109bebd5-d2cf-47fb-b47b-b957b26a5678
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820608498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1820608498
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.3257374222
Short name T697
Test name
Test status
Simulation time 46598535 ps
CPU time 1.38 seconds
Started Aug 10 05:15:45 PM PDT 24
Finished Aug 10 05:15:47 PM PDT 24
Peak memory 196136 kb
Host smart-1cfb26b9-1844-4b92-b552-3765c1653b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257374222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.3257374222
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2488842749
Short name T284
Test name
Test status
Simulation time 80274374 ps
CPU time 0.9 seconds
Started Aug 10 05:15:47 PM PDT 24
Finished Aug 10 05:15:48 PM PDT 24
Peak memory 195676 kb
Host smart-b0d0d084-6960-40ff-9153-4be2f8aecb59
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488842749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2488842749
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.4224350439
Short name T243
Test name
Test status
Simulation time 28575507696 ps
CPU time 112.86 seconds
Started Aug 10 05:15:43 PM PDT 24
Finished Aug 10 05:17:36 PM PDT 24
Peak memory 198704 kb
Host smart-aae515af-d259-456f-8aa4-ad8e109dc864
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224350439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.4224350439
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.2486027774
Short name T406
Test name
Test status
Simulation time 77511618392 ps
CPU time 1869.62 seconds
Started Aug 10 05:15:42 PM PDT 24
Finished Aug 10 05:46:52 PM PDT 24
Peak memory 198840 kb
Host smart-f1b8dbfd-144b-48c3-ab0b-5731b34344f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2486027774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.2486027774
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.1109559128
Short name T309
Test name
Test status
Simulation time 17359769 ps
CPU time 0.58 seconds
Started Aug 10 05:15:56 PM PDT 24
Finished Aug 10 05:15:57 PM PDT 24
Peak memory 195396 kb
Host smart-4467fa1e-9336-48e8-954e-2604108ab78e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109559128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.1109559128
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3217066321
Short name T571
Test name
Test status
Simulation time 83276597 ps
CPU time 0.83 seconds
Started Aug 10 05:15:45 PM PDT 24
Finished Aug 10 05:15:46 PM PDT 24
Peak memory 194592 kb
Host smart-56335bcf-7169-4d88-b1c8-ad4243315f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217066321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3217066321
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.1749426375
Short name T128
Test name
Test status
Simulation time 1205746914 ps
CPU time 15.81 seconds
Started Aug 10 05:15:44 PM PDT 24
Finished Aug 10 05:16:01 PM PDT 24
Peak memory 198604 kb
Host smart-43c1e152-10b0-447c-8859-91df1813e437
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749426375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.1749426375
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.150993671
Short name T495
Test name
Test status
Simulation time 88260301 ps
CPU time 1.06 seconds
Started Aug 10 05:15:45 PM PDT 24
Finished Aug 10 05:15:46 PM PDT 24
Peak memory 197636 kb
Host smart-0b24d2df-e3e7-4029-8f6a-47776146c65f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150993671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.150993671
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1559238402
Short name T418
Test name
Test status
Simulation time 49080842 ps
CPU time 0.87 seconds
Started Aug 10 05:15:45 PM PDT 24
Finished Aug 10 05:15:46 PM PDT 24
Peak memory 196260 kb
Host smart-2d643797-d675-4068-9222-4151e867f676
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559238402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1559238402
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.65012093
Short name T383
Test name
Test status
Simulation time 151208787 ps
CPU time 2.91 seconds
Started Aug 10 05:15:45 PM PDT 24
Finished Aug 10 05:15:48 PM PDT 24
Peak memory 198692 kb
Host smart-f7726978-cd47-4ae7-a734-7f1499e73d0d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65012093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.gpio_intr_with_filter_rand_intr_event.65012093
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.135028101
Short name T217
Test name
Test status
Simulation time 24786006 ps
CPU time 0.9 seconds
Started Aug 10 05:15:44 PM PDT 24
Finished Aug 10 05:15:45 PM PDT 24
Peak memory 196832 kb
Host smart-40ce7e89-a9a5-4d62-89c4-39813802c633
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135028101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger.
135028101
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.3119662966
Short name T218
Test name
Test status
Simulation time 103752574 ps
CPU time 1.02 seconds
Started Aug 10 05:15:46 PM PDT 24
Finished Aug 10 05:15:47 PM PDT 24
Peak memory 196388 kb
Host smart-3e3af918-e527-4aa9-8bbe-7a83373fcf8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119662966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3119662966
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.230512390
Short name T171
Test name
Test status
Simulation time 51843434 ps
CPU time 1.06 seconds
Started Aug 10 05:15:44 PM PDT 24
Finished Aug 10 05:15:46 PM PDT 24
Peak memory 196484 kb
Host smart-eadc3141-8466-4fa8-b89e-ec789cef92be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230512390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullup
_pulldown.230512390
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.3916015436
Short name T555
Test name
Test status
Simulation time 420227095 ps
CPU time 2.1 seconds
Started Aug 10 05:15:45 PM PDT 24
Finished Aug 10 05:15:48 PM PDT 24
Peak memory 198616 kb
Host smart-637bce50-0625-44e0-bf91-359e994e3588
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916015436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.3916015436
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.424296338
Short name T396
Test name
Test status
Simulation time 36584534 ps
CPU time 1.1 seconds
Started Aug 10 05:15:46 PM PDT 24
Finished Aug 10 05:15:47 PM PDT 24
Peak memory 196276 kb
Host smart-f65049ec-bc31-4b6e-9736-db5f878cdde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424296338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.424296338
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.3374627174
Short name T376
Test name
Test status
Simulation time 74411417 ps
CPU time 1.29 seconds
Started Aug 10 05:15:46 PM PDT 24
Finished Aug 10 05:15:47 PM PDT 24
Peak memory 196896 kb
Host smart-807c1ade-6329-4d28-9dd8-d21f4e802235
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374627174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.3374627174
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.3925940934
Short name T318
Test name
Test status
Simulation time 6009648530 ps
CPU time 187.16 seconds
Started Aug 10 05:15:44 PM PDT 24
Finished Aug 10 05:18:52 PM PDT 24
Peak memory 198744 kb
Host smart-763cfd7e-7249-4c45-8b19-e2ac5aaf3784
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925940934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3925940934
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.4039144251
Short name T64
Test name
Test status
Simulation time 53979179042 ps
CPU time 1171.73 seconds
Started Aug 10 05:15:57 PM PDT 24
Finished Aug 10 05:35:29 PM PDT 24
Peak memory 198776 kb
Host smart-f425c2cf-c5b6-4ddc-ae52-ee6f77302bde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4039144251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.4039144251
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.3095413445
Short name T157
Test name
Test status
Simulation time 27443878 ps
CPU time 0.59 seconds
Started Aug 10 05:15:09 PM PDT 24
Finished Aug 10 05:15:10 PM PDT 24
Peak memory 194664 kb
Host smart-94aa3ef1-270b-4da8-abf2-b4bc4740e90e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095413445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.3095413445
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.2527719964
Short name T143
Test name
Test status
Simulation time 95892647 ps
CPU time 0.9 seconds
Started Aug 10 05:15:07 PM PDT 24
Finished Aug 10 05:15:08 PM PDT 24
Peak memory 197716 kb
Host smart-9197b78b-ba8b-4157-b6a7-41cb1b20c71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527719964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.2527719964
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.2356500679
Short name T449
Test name
Test status
Simulation time 132847463 ps
CPU time 6.78 seconds
Started Aug 10 05:15:07 PM PDT 24
Finished Aug 10 05:15:14 PM PDT 24
Peak memory 197428 kb
Host smart-e2bbf2dc-173b-4670-957a-0474189185d4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356500679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.2356500679
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.1722662085
Short name T330
Test name
Test status
Simulation time 298110224 ps
CPU time 0.8 seconds
Started Aug 10 05:15:06 PM PDT 24
Finished Aug 10 05:15:07 PM PDT 24
Peak memory 196336 kb
Host smart-2cfcce60-3743-48a5-b6d9-0b4a6e0433de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722662085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1722662085
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.268085571
Short name T435
Test name
Test status
Simulation time 28009565 ps
CPU time 0.94 seconds
Started Aug 10 05:15:07 PM PDT 24
Finished Aug 10 05:15:08 PM PDT 24
Peak memory 196336 kb
Host smart-0055a12f-aa98-471c-a5b5-fa98ca6f7366
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268085571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.268085571
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.1252483014
Short name T705
Test name
Test status
Simulation time 280713024 ps
CPU time 2.8 seconds
Started Aug 10 05:15:06 PM PDT 24
Finished Aug 10 05:15:09 PM PDT 24
Peak memory 196972 kb
Host smart-67da0fce-0c18-4d8c-8604-9e520c1689c9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252483014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.1252483014
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.3737094290
Short name T69
Test name
Test status
Simulation time 270865248 ps
CPU time 2.22 seconds
Started Aug 10 05:15:07 PM PDT 24
Finished Aug 10 05:15:09 PM PDT 24
Peak memory 197056 kb
Host smart-1ffdab95-6079-4d13-ad50-70b35948cedc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737094290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
3737094290
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3041270432
Short name T413
Test name
Test status
Simulation time 24921416 ps
CPU time 0.97 seconds
Started Aug 10 05:15:09 PM PDT 24
Finished Aug 10 05:15:10 PM PDT 24
Peak memory 196392 kb
Host smart-4f04dc47-5c96-4a86-af63-d804ff815815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041270432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3041270432
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.2113356629
Short name T126
Test name
Test status
Simulation time 46144136 ps
CPU time 1.02 seconds
Started Aug 10 05:15:09 PM PDT 24
Finished Aug 10 05:15:10 PM PDT 24
Peak memory 196396 kb
Host smart-bb2153ce-9df5-4df5-b299-c5077065ed6b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113356629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.2113356629
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1887904355
Short name T440
Test name
Test status
Simulation time 320223202 ps
CPU time 5.21 seconds
Started Aug 10 05:15:09 PM PDT 24
Finished Aug 10 05:15:14 PM PDT 24
Peak memory 198568 kb
Host smart-26185dba-465b-4fd6-b4a6-f6181e28a5b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887904355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1887904355
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.619423912
Short name T52
Test name
Test status
Simulation time 338068913 ps
CPU time 0.97 seconds
Started Aug 10 05:15:06 PM PDT 24
Finished Aug 10 05:15:08 PM PDT 24
Peak memory 215540 kb
Host smart-b2edb21a-cbda-41d8-b02a-92110f1ea6c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619423912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.619423912
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.3271020363
Short name T562
Test name
Test status
Simulation time 183899680 ps
CPU time 1.33 seconds
Started Aug 10 05:15:00 PM PDT 24
Finished Aug 10 05:15:01 PM PDT 24
Peak memory 197188 kb
Host smart-71b23353-87af-4965-a955-1930e6ff287f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271020363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.3271020363
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.1466680759
Short name T279
Test name
Test status
Simulation time 895475566 ps
CPU time 1.14 seconds
Started Aug 10 05:14:58 PM PDT 24
Finished Aug 10 05:14:59 PM PDT 24
Peak memory 196256 kb
Host smart-9691a1b8-9a4f-43ac-ae2f-afefd01e3716
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466680759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.1466680759
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1074329216
Short name T499
Test name
Test status
Simulation time 59310599305 ps
CPU time 187.15 seconds
Started Aug 10 05:15:08 PM PDT 24
Finished Aug 10 05:18:15 PM PDT 24
Peak memory 198700 kb
Host smart-a3ac5844-bb95-41c8-94fe-2ff1c002ae08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074329216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1074329216
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2839485468
Short name T146
Test name
Test status
Simulation time 33961059 ps
CPU time 0.57 seconds
Started Aug 10 05:16:02 PM PDT 24
Finished Aug 10 05:16:03 PM PDT 24
Peak memory 195208 kb
Host smart-e282c358-8304-433b-9e4d-ae14d7404d90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839485468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2839485468
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.596894767
Short name T16
Test name
Test status
Simulation time 52867682 ps
CPU time 0.86 seconds
Started Aug 10 05:15:55 PM PDT 24
Finished Aug 10 05:15:56 PM PDT 24
Peak memory 195800 kb
Host smart-2b45be56-fc2f-4c8b-b394-28e66ef340e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596894767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.596894767
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.959256499
Short name T401
Test name
Test status
Simulation time 758244321 ps
CPU time 21.11 seconds
Started Aug 10 05:15:52 PM PDT 24
Finished Aug 10 05:16:13 PM PDT 24
Peak memory 197172 kb
Host smart-04ecfa7b-83f8-4f73-b792-cdc6454cf50a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959256499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stres
s.959256499
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2111095690
Short name T203
Test name
Test status
Simulation time 30236631 ps
CPU time 0.71 seconds
Started Aug 10 05:16:00 PM PDT 24
Finished Aug 10 05:16:01 PM PDT 24
Peak memory 195784 kb
Host smart-43120d70-ee2a-471d-bc31-30aa3cee4c21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111095690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2111095690
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1144900222
Short name T75
Test name
Test status
Simulation time 32838345 ps
CPU time 0.99 seconds
Started Aug 10 05:15:53 PM PDT 24
Finished Aug 10 05:15:54 PM PDT 24
Peak memory 196416 kb
Host smart-b9ec7a9a-88d2-4dbf-b4a2-2548e8b76619
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144900222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1144900222
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.1825117945
Short name T538
Test name
Test status
Simulation time 155663885 ps
CPU time 2.01 seconds
Started Aug 10 05:15:53 PM PDT 24
Finished Aug 10 05:15:55 PM PDT 24
Peak memory 198680 kb
Host smart-ac0d80bf-2f64-424e-a8c5-03bc56757d9b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825117945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.1825117945
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3001232823
Short name T197
Test name
Test status
Simulation time 317109096 ps
CPU time 2.39 seconds
Started Aug 10 05:15:58 PM PDT 24
Finished Aug 10 05:16:01 PM PDT 24
Peak memory 197688 kb
Host smart-b642072c-7dd4-4dce-a756-7b10777330d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001232823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3001232823
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.3991078169
Short name T120
Test name
Test status
Simulation time 144220828 ps
CPU time 0.91 seconds
Started Aug 10 05:16:03 PM PDT 24
Finished Aug 10 05:16:04 PM PDT 24
Peak memory 197120 kb
Host smart-54b100b3-ff76-4866-9754-a098508cc36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991078169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.3991078169
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3948156056
Short name T459
Test name
Test status
Simulation time 106953348 ps
CPU time 1.11 seconds
Started Aug 10 05:15:53 PM PDT 24
Finished Aug 10 05:15:55 PM PDT 24
Peak memory 196504 kb
Host smart-63a653fa-f3a8-4b77-9f01-43784dbb7937
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948156056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3948156056
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.154383229
Short name T155
Test name
Test status
Simulation time 35946363 ps
CPU time 1.48 seconds
Started Aug 10 05:16:00 PM PDT 24
Finished Aug 10 05:16:02 PM PDT 24
Peak memory 198420 kb
Host smart-17f4e8f3-f84e-4989-b7f6-8da3214b1e7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154383229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.154383229
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.2157377847
Short name T181
Test name
Test status
Simulation time 621881581 ps
CPU time 1.36 seconds
Started Aug 10 05:15:57 PM PDT 24
Finished Aug 10 05:15:58 PM PDT 24
Peak memory 196852 kb
Host smart-f637e44b-bcea-4ccd-8c5d-54b4a7d5a284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157377847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2157377847
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3620767102
Short name T605
Test name
Test status
Simulation time 269538679 ps
CPU time 1.39 seconds
Started Aug 10 05:15:52 PM PDT 24
Finished Aug 10 05:15:54 PM PDT 24
Peak memory 196756 kb
Host smart-efa82484-1b4d-465b-9ba9-78eec33ea76b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620767102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3620767102
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2492167673
Short name T299
Test name
Test status
Simulation time 7103099350 ps
CPU time 177.05 seconds
Started Aug 10 05:15:54 PM PDT 24
Finished Aug 10 05:18:51 PM PDT 24
Peak memory 198780 kb
Host smart-b626a3b8-0b18-4abf-a411-4b466763a1ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492167673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2492167673
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.2321294048
Short name T522
Test name
Test status
Simulation time 13375475 ps
CPU time 0.62 seconds
Started Aug 10 05:15:56 PM PDT 24
Finished Aug 10 05:15:57 PM PDT 24
Peak memory 194676 kb
Host smart-e9b0b725-d83c-4bc3-ae9d-645ccfd1fcd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321294048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.2321294048
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.1715428672
Short name T498
Test name
Test status
Simulation time 35058289 ps
CPU time 0.71 seconds
Started Aug 10 05:15:57 PM PDT 24
Finished Aug 10 05:15:58 PM PDT 24
Peak memory 194516 kb
Host smart-35b32f2d-9f09-4298-aea5-6814cc72188d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715428672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.1715428672
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.1243946003
Short name T553
Test name
Test status
Simulation time 431398192 ps
CPU time 14.32 seconds
Started Aug 10 05:15:51 PM PDT 24
Finished Aug 10 05:16:06 PM PDT 24
Peak memory 196796 kb
Host smart-99d355ab-8623-40f8-9fe2-d8c7a690c3bd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243946003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.1243946003
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2077823407
Short name T581
Test name
Test status
Simulation time 64172027 ps
CPU time 0.85 seconds
Started Aug 10 05:15:53 PM PDT 24
Finished Aug 10 05:15:54 PM PDT 24
Peak memory 196360 kb
Host smart-34f9ef7c-7c03-47c6-8d99-99b1da403114
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077823407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2077823407
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.356106571
Short name T620
Test name
Test status
Simulation time 49335063 ps
CPU time 0.88 seconds
Started Aug 10 05:15:56 PM PDT 24
Finished Aug 10 05:15:58 PM PDT 24
Peak memory 196132 kb
Host smart-521202e5-2e4f-44d4-8de1-1eb5c640deef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356106571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.356106571
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.432055552
Short name T245
Test name
Test status
Simulation time 51489029 ps
CPU time 1.14 seconds
Started Aug 10 05:15:54 PM PDT 24
Finished Aug 10 05:15:55 PM PDT 24
Peak memory 198016 kb
Host smart-b974784e-6f98-4de2-8be9-d00651d0206d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432055552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.gpio_intr_with_filter_rand_intr_event.432055552
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1564420830
Short name T261
Test name
Test status
Simulation time 116184921 ps
CPU time 1.98 seconds
Started Aug 10 05:15:51 PM PDT 24
Finished Aug 10 05:15:53 PM PDT 24
Peak memory 197868 kb
Host smart-b525e1f7-8749-4a16-bba8-06e821853a8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564420830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1564420830
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1108546918
Short name T462
Test name
Test status
Simulation time 340452808 ps
CPU time 0.93 seconds
Started Aug 10 05:15:54 PM PDT 24
Finished Aug 10 05:15:55 PM PDT 24
Peak memory 196240 kb
Host smart-4dac8229-c170-45d7-9beb-b00ab6b47fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108546918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1108546918
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3838408612
Short name T625
Test name
Test status
Simulation time 461190076 ps
CPU time 1.23 seconds
Started Aug 10 05:15:54 PM PDT 24
Finished Aug 10 05:15:55 PM PDT 24
Peak memory 197688 kb
Host smart-174063b0-35c3-4cc1-a67e-cd03187704a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838408612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3838408612
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2456720187
Short name T355
Test name
Test status
Simulation time 303079262 ps
CPU time 5.19 seconds
Started Aug 10 05:15:56 PM PDT 24
Finished Aug 10 05:16:01 PM PDT 24
Peak memory 198608 kb
Host smart-46f1d7bf-c6aa-40e4-b79e-22cc8876dce2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456720187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2456720187
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.389673287
Short name T385
Test name
Test status
Simulation time 188976591 ps
CPU time 0.94 seconds
Started Aug 10 05:15:53 PM PDT 24
Finished Aug 10 05:15:54 PM PDT 24
Peak memory 197092 kb
Host smart-c5e0c0df-8cc0-4d57-bdb4-69889c101470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389673287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.389673287
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.641512156
Short name T145
Test name
Test status
Simulation time 43260424 ps
CPU time 1.24 seconds
Started Aug 10 05:15:54 PM PDT 24
Finished Aug 10 05:15:55 PM PDT 24
Peak memory 196848 kb
Host smart-351b9432-04fe-42ae-a2d3-49387fae7483
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641512156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.641512156
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.4134796821
Short name T530
Test name
Test status
Simulation time 6866177658 ps
CPU time 165.03 seconds
Started Aug 10 05:15:57 PM PDT 24
Finished Aug 10 05:18:42 PM PDT 24
Peak memory 198796 kb
Host smart-be3d1d03-854d-4e87-b84a-6c90eb9248eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134796821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.4134796821
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.2900239391
Short name T67
Test name
Test status
Simulation time 375798706478 ps
CPU time 802.68 seconds
Started Aug 10 05:16:00 PM PDT 24
Finished Aug 10 05:29:23 PM PDT 24
Peak memory 198780 kb
Host smart-6e1eff86-62f9-4724-9b76-21982e6fc3c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2900239391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.2900239391
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.13681808
Short name T497
Test name
Test status
Simulation time 14623585 ps
CPU time 0.67 seconds
Started Aug 10 05:15:54 PM PDT 24
Finished Aug 10 05:15:55 PM PDT 24
Peak memory 194456 kb
Host smart-221bb09b-b412-40e3-8867-ea644c08b1cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13681808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.13681808
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.955513407
Short name T515
Test name
Test status
Simulation time 108428835 ps
CPU time 0.77 seconds
Started Aug 10 05:15:55 PM PDT 24
Finished Aug 10 05:15:56 PM PDT 24
Peak memory 196456 kb
Host smart-58a06fd2-e386-4fcd-9c34-8313505c63b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955513407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.955513407
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.2743253901
Short name T290
Test name
Test status
Simulation time 1098136123 ps
CPU time 19.69 seconds
Started Aug 10 05:15:55 PM PDT 24
Finished Aug 10 05:16:15 PM PDT 24
Peak memory 198592 kb
Host smart-ba408b6f-2ac9-4086-877e-e5d62676d4ac
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743253901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.2743253901
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.190043486
Short name T688
Test name
Test status
Simulation time 29592622 ps
CPU time 0.67 seconds
Started Aug 10 05:15:52 PM PDT 24
Finished Aug 10 05:15:52 PM PDT 24
Peak memory 194976 kb
Host smart-4499d531-579d-4f68-8c5f-d776b039fa4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190043486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.190043486
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.3267681931
Short name T502
Test name
Test status
Simulation time 227716934 ps
CPU time 1.12 seconds
Started Aug 10 05:15:54 PM PDT 24
Finished Aug 10 05:15:56 PM PDT 24
Peak memory 196584 kb
Host smart-3013fa8d-7326-4d1a-abb2-f17cff08b74b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267681931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.3267681931
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2560603999
Short name T601
Test name
Test status
Simulation time 62735463 ps
CPU time 1.26 seconds
Started Aug 10 05:15:52 PM PDT 24
Finished Aug 10 05:15:53 PM PDT 24
Peak memory 197304 kb
Host smart-1e2a043f-05b0-478d-8e33-0251f255d0ef
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560603999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.2560603999
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.105507017
Short name T511
Test name
Test status
Simulation time 109214787 ps
CPU time 3.34 seconds
Started Aug 10 05:15:53 PM PDT 24
Finished Aug 10 05:15:57 PM PDT 24
Peak memory 197428 kb
Host smart-dc8333f1-ad42-4c7b-aa10-c00ebeb3965b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105507017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.
105507017
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.523292509
Short name T344
Test name
Test status
Simulation time 23207617 ps
CPU time 0.94 seconds
Started Aug 10 05:16:00 PM PDT 24
Finished Aug 10 05:16:01 PM PDT 24
Peak memory 196432 kb
Host smart-7b59092c-12fc-425d-b0d4-8c35ab24d293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523292509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.523292509
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2919439102
Short name T550
Test name
Test status
Simulation time 147474571 ps
CPU time 1.3 seconds
Started Aug 10 05:15:54 PM PDT 24
Finished Aug 10 05:15:55 PM PDT 24
Peak memory 197516 kb
Host smart-1f48a774-f235-4092-bf52-58d13bdabc9f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919439102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.2919439102
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.1337971041
Short name T456
Test name
Test status
Simulation time 63058586 ps
CPU time 1.19 seconds
Started Aug 10 05:16:03 PM PDT 24
Finished Aug 10 05:16:04 PM PDT 24
Peak memory 198452 kb
Host smart-1d5b18be-0699-4260-82f7-0b23d92ecbe6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337971041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.1337971041
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.1466253481
Short name T659
Test name
Test status
Simulation time 120122423 ps
CPU time 0.99 seconds
Started Aug 10 05:15:57 PM PDT 24
Finished Aug 10 05:15:59 PM PDT 24
Peak memory 196964 kb
Host smart-ebc2602e-1728-4ae3-ac56-d5e28e440c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466253481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1466253481
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.1593330399
Short name T554
Test name
Test status
Simulation time 215792643 ps
CPU time 1.58 seconds
Started Aug 10 05:15:53 PM PDT 24
Finished Aug 10 05:15:55 PM PDT 24
Peak memory 196076 kb
Host smart-8d26a6fe-210d-4ce4-b75d-c46b911c5efa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593330399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.1593330399
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.4153393582
Short name T463
Test name
Test status
Simulation time 39320885081 ps
CPU time 207.65 seconds
Started Aug 10 05:15:55 PM PDT 24
Finished Aug 10 05:19:23 PM PDT 24
Peak memory 198384 kb
Host smart-0e3b1bd6-cc8c-475d-a21e-4d76663b6f27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153393582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.4153393582
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.2976797622
Short name T55
Test name
Test status
Simulation time 31655025 ps
CPU time 0.6 seconds
Started Aug 10 05:15:54 PM PDT 24
Finished Aug 10 05:15:55 PM PDT 24
Peak memory 194452 kb
Host smart-f6c85bfc-78f2-4e4a-a040-24d8920997fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976797622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.2976797622
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.2802238809
Short name T676
Test name
Test status
Simulation time 31215937 ps
CPU time 0.87 seconds
Started Aug 10 05:15:54 PM PDT 24
Finished Aug 10 05:15:55 PM PDT 24
Peak memory 197860 kb
Host smart-638c4dda-6c26-4145-93f8-8a2aa8947dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802238809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.2802238809
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2405054455
Short name T612
Test name
Test status
Simulation time 7809861992 ps
CPU time 24.48 seconds
Started Aug 10 05:15:51 PM PDT 24
Finished Aug 10 05:16:16 PM PDT 24
Peak memory 198112 kb
Host smart-192f08b5-ebb0-4f7f-9402-b5c43c1271c3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405054455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2405054455
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.2768357032
Short name T22
Test name
Test status
Simulation time 64602312 ps
CPU time 0.69 seconds
Started Aug 10 05:15:56 PM PDT 24
Finished Aug 10 05:15:56 PM PDT 24
Peak memory 195824 kb
Host smart-d4743edb-2181-4fa2-8a9f-39b6a9760a02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768357032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.2768357032
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.425646208
Short name T653
Test name
Test status
Simulation time 332359485 ps
CPU time 1.32 seconds
Started Aug 10 05:15:56 PM PDT 24
Finished Aug 10 05:15:58 PM PDT 24
Peak memory 196732 kb
Host smart-02069f21-759a-43f5-a98f-420741741ae6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425646208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.425646208
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3990822416
Short name T552
Test name
Test status
Simulation time 328754838 ps
CPU time 3.34 seconds
Started Aug 10 05:15:51 PM PDT 24
Finished Aug 10 05:15:54 PM PDT 24
Peak memory 196784 kb
Host smart-28d1ad06-b087-40a9-9fe6-72a3c78b8491
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990822416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3990822416
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.3876383894
Short name T652
Test name
Test status
Simulation time 68292551 ps
CPU time 1.68 seconds
Started Aug 10 05:15:52 PM PDT 24
Finished Aug 10 05:15:54 PM PDT 24
Peak memory 196260 kb
Host smart-a24baa6f-9265-4570-9649-b780cff3a885
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876383894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.3876383894
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.579429814
Short name T451
Test name
Test status
Simulation time 37134809 ps
CPU time 1.23 seconds
Started Aug 10 05:15:55 PM PDT 24
Finished Aug 10 05:15:57 PM PDT 24
Peak memory 195360 kb
Host smart-4ab65774-c88b-422c-98b7-0f353cda8f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579429814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.579429814
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.3189289662
Short name T340
Test name
Test status
Simulation time 225761184 ps
CPU time 1.04 seconds
Started Aug 10 05:15:53 PM PDT 24
Finished Aug 10 05:15:54 PM PDT 24
Peak memory 196632 kb
Host smart-9c9e97a1-f691-4159-b75e-6ab5c1fd987d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189289662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.3189289662
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.2041062934
Short name T417
Test name
Test status
Simulation time 142011348 ps
CPU time 2.68 seconds
Started Aug 10 05:15:56 PM PDT 24
Finished Aug 10 05:15:59 PM PDT 24
Peak memory 198408 kb
Host smart-d98884c7-267d-417d-94b2-8cce63a616ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041062934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.2041062934
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.574015966
Short name T298
Test name
Test status
Simulation time 48471014 ps
CPU time 1.14 seconds
Started Aug 10 05:15:55 PM PDT 24
Finished Aug 10 05:15:57 PM PDT 24
Peak memory 196004 kb
Host smart-d175b2d7-b115-4780-9472-4edf57187927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574015966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.574015966
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.2933471539
Short name T60
Test name
Test status
Simulation time 1048031709 ps
CPU time 1.14 seconds
Started Aug 10 05:15:56 PM PDT 24
Finished Aug 10 05:15:58 PM PDT 24
Peak memory 195080 kb
Host smart-c7f04d1c-9930-4c03-91dd-de076650fbaf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933471539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.2933471539
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2539748628
Short name T655
Test name
Test status
Simulation time 127242515692 ps
CPU time 208.56 seconds
Started Aug 10 05:15:56 PM PDT 24
Finished Aug 10 05:19:25 PM PDT 24
Peak memory 198804 kb
Host smart-31a0af91-2bb4-4868-8174-495a67b98b26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539748628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2539748628
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.708339446
Short name T81
Test name
Test status
Simulation time 17984031 ps
CPU time 0.58 seconds
Started Aug 10 05:16:00 PM PDT 24
Finished Aug 10 05:16:01 PM PDT 24
Peak memory 194540 kb
Host smart-4b15062f-a91c-41bf-9bf9-58d400d3e9e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708339446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.708339446
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.4250793041
Short name T182
Test name
Test status
Simulation time 26262489 ps
CPU time 0.72 seconds
Started Aug 10 05:15:54 PM PDT 24
Finished Aug 10 05:15:54 PM PDT 24
Peak memory 194724 kb
Host smart-9328635b-670e-4723-8e55-f6ff22ac3daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250793041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.4250793041
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.739896937
Short name T428
Test name
Test status
Simulation time 8373920703 ps
CPU time 27.42 seconds
Started Aug 10 05:15:54 PM PDT 24
Finished Aug 10 05:16:22 PM PDT 24
Peak memory 197372 kb
Host smart-eff83e9b-a51b-4416-b8ac-1751c867b8a0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739896937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stres
s.739896937
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.3382776838
Short name T361
Test name
Test status
Simulation time 67551172 ps
CPU time 0.91 seconds
Started Aug 10 05:15:54 PM PDT 24
Finished Aug 10 05:15:55 PM PDT 24
Peak memory 196484 kb
Host smart-4408311d-fb8a-4d95-8385-8d6a4bb73417
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382776838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.3382776838
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.3870639159
Short name T154
Test name
Test status
Simulation time 44524121 ps
CPU time 0.9 seconds
Started Aug 10 05:15:54 PM PDT 24
Finished Aug 10 05:15:55 PM PDT 24
Peak memory 195972 kb
Host smart-66459fc6-e5cd-48c8-8844-70192e040baf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870639159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.3870639159
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.1864929067
Short name T637
Test name
Test status
Simulation time 195552751 ps
CPU time 1.32 seconds
Started Aug 10 05:15:53 PM PDT 24
Finished Aug 10 05:15:54 PM PDT 24
Peak memory 198592 kb
Host smart-3d396192-d760-48b8-812f-e59d39a14681
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864929067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.1864929067
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.2369107546
Short name T220
Test name
Test status
Simulation time 603787207 ps
CPU time 3.16 seconds
Started Aug 10 05:15:56 PM PDT 24
Finished Aug 10 05:16:00 PM PDT 24
Peak memory 198528 kb
Host smart-3ddff7a9-28f6-4274-aa69-a6ec3b96eca4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369107546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.2369107546
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.3103040295
Short name T78
Test name
Test status
Simulation time 53478932 ps
CPU time 1.34 seconds
Started Aug 10 05:15:54 PM PDT 24
Finished Aug 10 05:15:56 PM PDT 24
Peak memory 197540 kb
Host smart-d220df33-c2eb-4e0f-af77-808d39c7ae90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103040295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3103040295
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.948036182
Short name T208
Test name
Test status
Simulation time 56925900 ps
CPU time 0.98 seconds
Started Aug 10 05:15:54 PM PDT 24
Finished Aug 10 05:15:56 PM PDT 24
Peak memory 196324 kb
Host smart-db899b66-1b34-4da7-84d6-fa13601e421e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948036182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.948036182
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.1545810555
Short name T487
Test name
Test status
Simulation time 1429207619 ps
CPU time 5.04 seconds
Started Aug 10 05:16:02 PM PDT 24
Finished Aug 10 05:16:07 PM PDT 24
Peak memory 198472 kb
Host smart-8987610a-d466-412c-8cf4-29007eb716fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545810555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.1545810555
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.3492244380
Short name T295
Test name
Test status
Simulation time 318630687 ps
CPU time 1.13 seconds
Started Aug 10 05:15:55 PM PDT 24
Finished Aug 10 05:15:56 PM PDT 24
Peak memory 195948 kb
Host smart-3e8a74d4-4ac7-4f6e-897d-148b0f5f1d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492244380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.3492244380
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.4218827593
Short name T452
Test name
Test status
Simulation time 385748584 ps
CPU time 1.04 seconds
Started Aug 10 05:15:52 PM PDT 24
Finished Aug 10 05:15:53 PM PDT 24
Peak memory 197088 kb
Host smart-b91a7bf6-3207-4497-b17e-1bbb07429fd8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218827593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.4218827593
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3861001877
Short name T124
Test name
Test status
Simulation time 15481486398 ps
CPU time 228.38 seconds
Started Aug 10 05:16:03 PM PDT 24
Finished Aug 10 05:19:52 PM PDT 24
Peak memory 198672 kb
Host smart-02ac3b17-0e85-4906-b9a4-62569d2b4c43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861001877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3861001877
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1329473628
Short name T489
Test name
Test status
Simulation time 16325090 ps
CPU time 0.62 seconds
Started Aug 10 05:16:01 PM PDT 24
Finished Aug 10 05:16:02 PM PDT 24
Peak memory 195272 kb
Host smart-bebd22d8-7e47-46fa-8c74-453ee0db6702
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329473628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1329473628
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.28329212
Short name T256
Test name
Test status
Simulation time 396713174 ps
CPU time 0.93 seconds
Started Aug 10 05:16:02 PM PDT 24
Finished Aug 10 05:16:03 PM PDT 24
Peak memory 196432 kb
Host smart-14fb5558-30fd-4f4d-9463-f87cb49ad2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28329212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.28329212
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.213078031
Short name T491
Test name
Test status
Simulation time 2772953796 ps
CPU time 20.89 seconds
Started Aug 10 05:16:12 PM PDT 24
Finished Aug 10 05:16:33 PM PDT 24
Peak memory 198608 kb
Host smart-8a876d80-aa1d-4526-9578-a477dfbad014
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213078031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.213078031
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.2894242832
Short name T135
Test name
Test status
Simulation time 34139647 ps
CPU time 0.73 seconds
Started Aug 10 05:16:11 PM PDT 24
Finished Aug 10 05:16:12 PM PDT 24
Peak memory 195804 kb
Host smart-94ba2746-92ea-4e88-b32e-e99b89d7ddc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894242832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.2894242832
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2623018904
Short name T205
Test name
Test status
Simulation time 351089763 ps
CPU time 1.42 seconds
Started Aug 10 05:16:02 PM PDT 24
Finished Aug 10 05:16:04 PM PDT 24
Peak memory 197660 kb
Host smart-10022454-11fa-4a74-95be-78ecda24d2a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623018904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2623018904
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.1014259204
Short name T185
Test name
Test status
Simulation time 287482161 ps
CPU time 2.97 seconds
Started Aug 10 05:16:13 PM PDT 24
Finished Aug 10 05:16:16 PM PDT 24
Peak memory 198656 kb
Host smart-22f099ec-4e07-43bf-a2a5-5504c5e4ec77
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014259204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.1014259204
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.4058212468
Short name T589
Test name
Test status
Simulation time 265484223 ps
CPU time 3.11 seconds
Started Aug 10 05:16:03 PM PDT 24
Finished Aug 10 05:16:06 PM PDT 24
Peak memory 197696 kb
Host smart-d65c3d9a-0470-4901-afaf-814860fe0a8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058212468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.4058212468
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.3914813142
Short name T72
Test name
Test status
Simulation time 51099494 ps
CPU time 0.66 seconds
Started Aug 10 05:15:59 PM PDT 24
Finished Aug 10 05:16:00 PM PDT 24
Peak memory 195600 kb
Host smart-a616aa98-f64e-4d00-a95f-148f753112f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914813142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.3914813142
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.2441011598
Short name T466
Test name
Test status
Simulation time 26320135 ps
CPU time 1.08 seconds
Started Aug 10 05:16:02 PM PDT 24
Finished Aug 10 05:16:04 PM PDT 24
Peak memory 197292 kb
Host smart-6b314ee6-066a-4603-ad96-0a34eaed87e0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441011598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.2441011598
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.1183166843
Short name T547
Test name
Test status
Simulation time 93825358 ps
CPU time 4.53 seconds
Started Aug 10 05:16:00 PM PDT 24
Finished Aug 10 05:16:05 PM PDT 24
Peak memory 198532 kb
Host smart-8cd8e704-e5f9-4112-ba65-3d1dac190bb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183166843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.1183166843
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.1244261945
Short name T654
Test name
Test status
Simulation time 81916494 ps
CPU time 1.31 seconds
Started Aug 10 05:16:12 PM PDT 24
Finished Aug 10 05:16:13 PM PDT 24
Peak memory 197096 kb
Host smart-312f0f53-a8d0-4fd1-a783-4fa43a769f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244261945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.1244261945
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3774882204
Short name T399
Test name
Test status
Simulation time 134154247 ps
CPU time 1.3 seconds
Started Aug 10 05:16:03 PM PDT 24
Finished Aug 10 05:16:04 PM PDT 24
Peak memory 197248 kb
Host smart-4a5bc769-034b-49af-9445-fc304407d165
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774882204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3774882204
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.2094694833
Short name T433
Test name
Test status
Simulation time 5945039751 ps
CPU time 158.16 seconds
Started Aug 10 05:16:01 PM PDT 24
Finished Aug 10 05:18:39 PM PDT 24
Peak memory 198700 kb
Host smart-e3c109bc-a30d-43c5-bbd5-df16e23a5372
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094694833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.2094694833
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.2047203858
Short name T33
Test name
Test status
Simulation time 319317077366 ps
CPU time 1229.02 seconds
Started Aug 10 05:16:11 PM PDT 24
Finished Aug 10 05:36:41 PM PDT 24
Peak memory 198816 kb
Host smart-9284e9ac-c6a4-4038-9508-98d960528bd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2047203858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.2047203858
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.2113816501
Short name T698
Test name
Test status
Simulation time 13779657 ps
CPU time 0.61 seconds
Started Aug 10 05:16:01 PM PDT 24
Finished Aug 10 05:16:02 PM PDT 24
Peak memory 194364 kb
Host smart-ae465ef2-f2ef-4400-a8f0-2574eccbc52b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113816501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.2113816501
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2323109232
Short name T348
Test name
Test status
Simulation time 71464017 ps
CPU time 0.75 seconds
Started Aug 10 05:16:00 PM PDT 24
Finished Aug 10 05:16:01 PM PDT 24
Peak memory 196628 kb
Host smart-712e3261-73f0-43b5-8a67-d236a76c6e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323109232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2323109232
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.2748258197
Short name T617
Test name
Test status
Simulation time 394222974 ps
CPU time 12.89 seconds
Started Aug 10 05:16:01 PM PDT 24
Finished Aug 10 05:16:14 PM PDT 24
Peak memory 198476 kb
Host smart-e10307c1-747d-416b-a9e8-4f465417dd2b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748258197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.2748258197
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.791139247
Short name T641
Test name
Test status
Simulation time 44064254 ps
CPU time 0.69 seconds
Started Aug 10 05:16:00 PM PDT 24
Finished Aug 10 05:16:01 PM PDT 24
Peak memory 194988 kb
Host smart-f8604d38-acee-4c48-b996-cd02a7ba91b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791139247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.791139247
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2421150470
Short name T11
Test name
Test status
Simulation time 151657172 ps
CPU time 1.1 seconds
Started Aug 10 05:16:02 PM PDT 24
Finished Aug 10 05:16:03 PM PDT 24
Peak memory 197092 kb
Host smart-9bf11232-ca35-49a1-9405-45a2687f4a6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421150470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2421150470
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.1308736105
Short name T640
Test name
Test status
Simulation time 265603575 ps
CPU time 1.6 seconds
Started Aug 10 05:16:02 PM PDT 24
Finished Aug 10 05:16:04 PM PDT 24
Peak memory 198440 kb
Host smart-d373e8f3-37ac-4d6a-8664-8de6cf31d48c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308736105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.1308736105
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.1140815303
Short name T178
Test name
Test status
Simulation time 529873922 ps
CPU time 3.66 seconds
Started Aug 10 05:16:08 PM PDT 24
Finished Aug 10 05:16:12 PM PDT 24
Peak memory 198636 kb
Host smart-40f18b60-874d-4111-8f2c-af2d1ba770f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140815303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.1140815303
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2801986358
Short name T465
Test name
Test status
Simulation time 348845819 ps
CPU time 1.15 seconds
Started Aug 10 05:16:01 PM PDT 24
Finished Aug 10 05:16:02 PM PDT 24
Peak memory 197572 kb
Host smart-f0e35338-220d-468e-bb77-3502d7005163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801986358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2801986358
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.2263463570
Short name T161
Test name
Test status
Simulation time 230697339 ps
CPU time 1.13 seconds
Started Aug 10 05:16:10 PM PDT 24
Finished Aug 10 05:16:12 PM PDT 24
Peak memory 197348 kb
Host smart-1e0bd0cc-75a2-455a-8801-45f219d3ea30
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263463570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.2263463570
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.4047258701
Short name T213
Test name
Test status
Simulation time 195413726 ps
CPU time 2.25 seconds
Started Aug 10 05:16:02 PM PDT 24
Finished Aug 10 05:16:05 PM PDT 24
Peak memory 198532 kb
Host smart-409d920f-99c7-4da2-ac5e-8f6b066e1b66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047258701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.4047258701
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2721062333
Short name T359
Test name
Test status
Simulation time 310543285 ps
CPU time 1.12 seconds
Started Aug 10 05:16:05 PM PDT 24
Finished Aug 10 05:16:06 PM PDT 24
Peak memory 196688 kb
Host smart-4431d02c-8701-403e-a861-3fae5895e67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721062333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2721062333
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.822431970
Short name T545
Test name
Test status
Simulation time 420687539 ps
CPU time 0.95 seconds
Started Aug 10 05:16:01 PM PDT 24
Finished Aug 10 05:16:02 PM PDT 24
Peak memory 197468 kb
Host smart-88449437-8ce3-4d59-8873-1b5413047231
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822431970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.822431970
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.1951628213
Short name T632
Test name
Test status
Simulation time 24856949326 ps
CPU time 88.02 seconds
Started Aug 10 05:16:02 PM PDT 24
Finished Aug 10 05:17:30 PM PDT 24
Peak memory 198924 kb
Host smart-0f4d2ae4-e732-4353-b3d7-2268c677ebc5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951628213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.1951628213
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.2715323885
Short name T74
Test name
Test status
Simulation time 49591020 ps
CPU time 0.59 seconds
Started Aug 10 05:16:00 PM PDT 24
Finished Aug 10 05:16:01 PM PDT 24
Peak memory 195396 kb
Host smart-9e3ee724-8256-4896-b670-c5a389171c43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715323885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.2715323885
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.1851482968
Short name T45
Test name
Test status
Simulation time 45369414 ps
CPU time 0.87 seconds
Started Aug 10 05:16:04 PM PDT 24
Finished Aug 10 05:16:05 PM PDT 24
Peak memory 196852 kb
Host smart-81967c72-0e8d-441a-9845-07651fc2bb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851482968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.1851482968
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.4092608589
Short name T345
Test name
Test status
Simulation time 525911796 ps
CPU time 14.1 seconds
Started Aug 10 05:16:02 PM PDT 24
Finished Aug 10 05:16:16 PM PDT 24
Peak memory 197356 kb
Host smart-d78b4392-8ee1-402d-805c-374433b9b48d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092608589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.4092608589
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3310699151
Short name T442
Test name
Test status
Simulation time 230532811 ps
CPU time 0.88 seconds
Started Aug 10 05:15:59 PM PDT 24
Finished Aug 10 05:16:00 PM PDT 24
Peak memory 196464 kb
Host smart-dcbfe147-5711-4588-b9a2-c3f6b04e8814
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310699151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3310699151
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.62967246
Short name T316
Test name
Test status
Simulation time 48291572 ps
CPU time 1.26 seconds
Started Aug 10 05:15:59 PM PDT 24
Finished Aug 10 05:16:00 PM PDT 24
Peak memory 197640 kb
Host smart-4034eeaf-00c0-46e6-9255-f65800730e7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62967246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.62967246
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.2160802459
Short name T457
Test name
Test status
Simulation time 46877816 ps
CPU time 1.78 seconds
Started Aug 10 05:16:04 PM PDT 24
Finished Aug 10 05:16:06 PM PDT 24
Peak memory 197104 kb
Host smart-3c0d40ad-5053-4c2c-8bea-a93305fca77e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160802459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.2160802459
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1492684463
Short name T122
Test name
Test status
Simulation time 517415259 ps
CPU time 2.62 seconds
Started Aug 10 05:16:12 PM PDT 24
Finished Aug 10 05:16:15 PM PDT 24
Peak memory 197244 kb
Host smart-1f076365-61e8-4c4d-af09-9d6a67cf531c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492684463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1492684463
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.3762816207
Short name T132
Test name
Test status
Simulation time 42684862 ps
CPU time 1.2 seconds
Started Aug 10 05:16:01 PM PDT 24
Finished Aug 10 05:16:02 PM PDT 24
Peak memory 196616 kb
Host smart-b5808108-ace7-4ba0-829c-8efb13403cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762816207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.3762816207
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.4175833677
Short name T695
Test name
Test status
Simulation time 48899557 ps
CPU time 0.83 seconds
Started Aug 10 05:16:03 PM PDT 24
Finished Aug 10 05:16:04 PM PDT 24
Peak memory 195972 kb
Host smart-985b156c-2f02-476e-9d83-0c68ac48763f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175833677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.4175833677
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1204347405
Short name T111
Test name
Test status
Simulation time 422639338 ps
CPU time 5.6 seconds
Started Aug 10 05:16:03 PM PDT 24
Finished Aug 10 05:16:08 PM PDT 24
Peak memory 198544 kb
Host smart-e2cedcf5-3ab2-47bf-b665-d87f811e0b8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204347405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1204347405
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.1016993350
Short name T162
Test name
Test status
Simulation time 50650753 ps
CPU time 0.99 seconds
Started Aug 10 05:16:01 PM PDT 24
Finished Aug 10 05:16:02 PM PDT 24
Peak memory 197412 kb
Host smart-a76895bd-ee86-41a4-a536-966413d51898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016993350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.1016993350
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.2253991495
Short name T579
Test name
Test status
Simulation time 51930335 ps
CPU time 1.19 seconds
Started Aug 10 05:16:05 PM PDT 24
Finished Aug 10 05:16:07 PM PDT 24
Peak memory 196884 kb
Host smart-ed3a75a2-cd81-445e-bde3-819b42c77059
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253991495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.2253991495
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.656452935
Short name T251
Test name
Test status
Simulation time 11166153469 ps
CPU time 167.63 seconds
Started Aug 10 05:15:59 PM PDT 24
Finished Aug 10 05:18:47 PM PDT 24
Peak memory 198632 kb
Host smart-9ee27153-0991-4ec9-b772-7f85eadf87ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656452935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.g
pio_stress_all.656452935
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.229683987
Short name T42
Test name
Test status
Simulation time 121935966 ps
CPU time 0.57 seconds
Started Aug 10 05:16:03 PM PDT 24
Finished Aug 10 05:16:04 PM PDT 24
Peak memory 194400 kb
Host smart-77b3a407-073e-4898-9674-1c6663d40e42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229683987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.229683987
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.3038695908
Short name T569
Test name
Test status
Simulation time 145672755 ps
CPU time 0.7 seconds
Started Aug 10 05:16:05 PM PDT 24
Finished Aug 10 05:16:06 PM PDT 24
Peak memory 194732 kb
Host smart-438a92d6-2ff6-415a-85fb-a19085498a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038695908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.3038695908
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.1186069434
Short name T158
Test name
Test status
Simulation time 282693402 ps
CPU time 14.91 seconds
Started Aug 10 05:16:12 PM PDT 24
Finished Aug 10 05:16:27 PM PDT 24
Peak memory 195928 kb
Host smart-665e8c68-d4a1-4520-9900-41459e440918
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186069434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.1186069434
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.4135896712
Short name T397
Test name
Test status
Simulation time 88412915 ps
CPU time 1.02 seconds
Started Aug 10 05:16:03 PM PDT 24
Finished Aug 10 05:16:04 PM PDT 24
Peak memory 196944 kb
Host smart-6b31894d-6927-4251-a200-510e76b32ec5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135896712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.4135896712
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.3837485961
Short name T523
Test name
Test status
Simulation time 87182648 ps
CPU time 1.37 seconds
Started Aug 10 05:16:03 PM PDT 24
Finished Aug 10 05:16:04 PM PDT 24
Peak memory 198628 kb
Host smart-49740bff-a2a5-40ee-8051-9f64040e1f4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837485961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.3837485961
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3172574180
Short name T14
Test name
Test status
Simulation time 22076309 ps
CPU time 0.89 seconds
Started Aug 10 05:16:11 PM PDT 24
Finished Aug 10 05:16:12 PM PDT 24
Peak memory 196664 kb
Host smart-defe1875-ab5d-4d80-bdb5-e3a5cb46c83b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172574180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3172574180
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.988501080
Short name T342
Test name
Test status
Simulation time 215084931 ps
CPU time 1.87 seconds
Started Aug 10 05:16:05 PM PDT 24
Finished Aug 10 05:16:07 PM PDT 24
Peak memory 196464 kb
Host smart-40eb26d0-fd69-4136-933b-8945aa0678f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988501080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.
988501080
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.165347652
Short name T380
Test name
Test status
Simulation time 97839818 ps
CPU time 0.77 seconds
Started Aug 10 05:15:58 PM PDT 24
Finished Aug 10 05:15:59 PM PDT 24
Peak memory 195704 kb
Host smart-8288eaf3-2ece-4af5-9149-0b310f5d16f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165347652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.165347652
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2788081797
Short name T196
Test name
Test status
Simulation time 134795240 ps
CPU time 1.07 seconds
Started Aug 10 05:16:03 PM PDT 24
Finished Aug 10 05:16:05 PM PDT 24
Peak memory 196312 kb
Host smart-8b883e78-dfc3-4509-a001-d56ced57fc35
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788081797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2788081797
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.2151047303
Short name T7
Test name
Test status
Simulation time 770124499 ps
CPU time 4.45 seconds
Started Aug 10 05:16:12 PM PDT 24
Finished Aug 10 05:16:16 PM PDT 24
Peak memory 198248 kb
Host smart-62f01d02-6fc1-4f6c-bece-76e37e732799
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151047303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.2151047303
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.4263718013
Short name T699
Test name
Test status
Simulation time 75864253 ps
CPU time 1.15 seconds
Started Aug 10 05:16:03 PM PDT 24
Finished Aug 10 05:16:04 PM PDT 24
Peak memory 196124 kb
Host smart-c0ae8cc2-6285-41f3-a5d6-b224e8c8a461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263718013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.4263718013
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.643886392
Short name T270
Test name
Test status
Simulation time 203626973 ps
CPU time 1.09 seconds
Started Aug 10 05:16:04 PM PDT 24
Finished Aug 10 05:16:06 PM PDT 24
Peak memory 196092 kb
Host smart-a76db8fc-7e3a-4966-b395-006c86972279
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643886392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.643886392
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.1677896196
Short name T587
Test name
Test status
Simulation time 13534306757 ps
CPU time 154.53 seconds
Started Aug 10 05:16:01 PM PDT 24
Finished Aug 10 05:18:36 PM PDT 24
Peak memory 198720 kb
Host smart-ef196000-9f63-48ea-b8e5-7fb377c8401c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677896196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.1677896196
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.3862371924
Short name T549
Test name
Test status
Simulation time 25271071025 ps
CPU time 621.01 seconds
Started Aug 10 05:16:11 PM PDT 24
Finished Aug 10 05:26:33 PM PDT 24
Peak memory 198728 kb
Host smart-10a6dea2-e1cd-48dc-974a-1b7d43edc9b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3862371924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.3862371924
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.2402616344
Short name T200
Test name
Test status
Simulation time 13010246 ps
CPU time 0.58 seconds
Started Aug 10 05:16:11 PM PDT 24
Finished Aug 10 05:16:12 PM PDT 24
Peak memory 194692 kb
Host smart-3d30e4ec-1fa8-4319-be6b-9b0bef740093
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402616344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.2402616344
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.2127737757
Short name T469
Test name
Test status
Simulation time 24978637 ps
CPU time 0.64 seconds
Started Aug 10 05:16:10 PM PDT 24
Finished Aug 10 05:16:11 PM PDT 24
Peak memory 194612 kb
Host smart-0d943d47-53df-46ae-95f9-d08dd35e3481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127737757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.2127737757
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.1496579732
Short name T673
Test name
Test status
Simulation time 594795984 ps
CPU time 10.79 seconds
Started Aug 10 05:16:11 PM PDT 24
Finished Aug 10 05:16:22 PM PDT 24
Peak memory 198616 kb
Host smart-956d0f41-3a41-499c-b56c-9fa4841c967a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496579732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.1496579732
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.984875444
Short name T23
Test name
Test status
Simulation time 67897145 ps
CPU time 1.06 seconds
Started Aug 10 05:16:10 PM PDT 24
Finished Aug 10 05:16:11 PM PDT 24
Peak memory 197172 kb
Host smart-7a7acc2e-d9cb-4dec-a9b8-b1bfbd7869ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984875444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.984875444
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.950843123
Short name T228
Test name
Test status
Simulation time 168782744 ps
CPU time 1.31 seconds
Started Aug 10 05:16:12 PM PDT 24
Finished Aug 10 05:16:13 PM PDT 24
Peak memory 197696 kb
Host smart-298ef1d0-d027-4fe6-a638-9223bc0454a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950843123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.950843123
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2808717256
Short name T572
Test name
Test status
Simulation time 49700161 ps
CPU time 2.18 seconds
Started Aug 10 05:16:13 PM PDT 24
Finished Aug 10 05:16:15 PM PDT 24
Peak memory 198500 kb
Host smart-d9e4147a-90c1-4f1e-9a36-b1a96df12403
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808717256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2808717256
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1628271313
Short name T113
Test name
Test status
Simulation time 157784094 ps
CPU time 2.07 seconds
Started Aug 10 05:16:08 PM PDT 24
Finished Aug 10 05:16:10 PM PDT 24
Peak memory 197216 kb
Host smart-cbc2cbd6-e8d5-4cc9-ac8f-217205c6230d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628271313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1628271313
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.10059419
Short name T199
Test name
Test status
Simulation time 32212063 ps
CPU time 0.91 seconds
Started Aug 10 05:16:18 PM PDT 24
Finished Aug 10 05:16:19 PM PDT 24
Peak memory 197688 kb
Host smart-cc9b3a73-fc0c-4ad5-bc4e-faecf78744cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10059419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.10059419
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3561267414
Short name T584
Test name
Test status
Simulation time 53508257 ps
CPU time 1.27 seconds
Started Aug 10 05:16:14 PM PDT 24
Finished Aug 10 05:16:15 PM PDT 24
Peak memory 197652 kb
Host smart-97b8b7bd-1072-4d21-a836-71be170b5a31
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561267414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3561267414
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.2739475347
Short name T707
Test name
Test status
Simulation time 410033623 ps
CPU time 2.01 seconds
Started Aug 10 05:16:13 PM PDT 24
Finished Aug 10 05:16:15 PM PDT 24
Peak memory 198568 kb
Host smart-c7f97276-570f-48fc-bcb5-faa04e033fcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739475347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.2739475347
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.3707586714
Short name T265
Test name
Test status
Simulation time 72797592 ps
CPU time 1.25 seconds
Started Aug 10 05:16:09 PM PDT 24
Finished Aug 10 05:16:11 PM PDT 24
Peak memory 196408 kb
Host smart-46853b9a-6409-4ef1-a62d-1feea9aee521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707586714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.3707586714
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.4018815558
Short name T467
Test name
Test status
Simulation time 40507683 ps
CPU time 0.87 seconds
Started Aug 10 05:16:09 PM PDT 24
Finished Aug 10 05:16:10 PM PDT 24
Peak memory 195792 kb
Host smart-a4e2d975-5b62-45f1-8f78-eefca2ba723e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018815558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.4018815558
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.3155393820
Short name T263
Test name
Test status
Simulation time 8966324055 ps
CPU time 133.53 seconds
Started Aug 10 05:16:12 PM PDT 24
Finished Aug 10 05:18:26 PM PDT 24
Peak memory 198736 kb
Host smart-b3b06963-00be-4ab6-a6fd-4f1fe7400899
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155393820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.3155393820
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.1551071089
Short name T66
Test name
Test status
Simulation time 74576849745 ps
CPU time 469.41 seconds
Started Aug 10 05:16:11 PM PDT 24
Finished Aug 10 05:24:00 PM PDT 24
Peak memory 198864 kb
Host smart-841c5787-3fef-42e6-8496-4edcec038045
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1551071089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.1551071089
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2735556131
Short name T635
Test name
Test status
Simulation time 14675380 ps
CPU time 0.56 seconds
Started Aug 10 05:15:08 PM PDT 24
Finished Aug 10 05:15:09 PM PDT 24
Peak memory 194516 kb
Host smart-7ddff6d4-d6be-40ec-a8d1-2eaaf20b454a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735556131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2735556131
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3994347312
Short name T204
Test name
Test status
Simulation time 54344068 ps
CPU time 0.64 seconds
Started Aug 10 05:15:06 PM PDT 24
Finished Aug 10 05:15:07 PM PDT 24
Peak memory 194600 kb
Host smart-660a902e-967f-487e-a620-936bfd52286e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994347312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3994347312
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.3835185732
Short name T623
Test name
Test status
Simulation time 116698637 ps
CPU time 4.36 seconds
Started Aug 10 05:15:06 PM PDT 24
Finished Aug 10 05:15:10 PM PDT 24
Peak memory 196300 kb
Host smart-72e0aa99-30fb-4980-9a48-db46e13c40be
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835185732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.3835185732
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2084522858
Short name T633
Test name
Test status
Simulation time 105639241 ps
CPU time 0.78 seconds
Started Aug 10 05:15:10 PM PDT 24
Finished Aug 10 05:15:11 PM PDT 24
Peak memory 195148 kb
Host smart-c0573a58-0a26-4c1c-a243-38b893d46a3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084522858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2084522858
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2255669061
Short name T624
Test name
Test status
Simulation time 72192660 ps
CPU time 1.26 seconds
Started Aug 10 05:15:07 PM PDT 24
Finished Aug 10 05:15:08 PM PDT 24
Peak memory 196352 kb
Host smart-4b48fa76-770d-430f-bf4d-055e64ca331e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255669061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2255669061
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.333232760
Short name T142
Test name
Test status
Simulation time 87635820 ps
CPU time 3.53 seconds
Started Aug 10 05:15:12 PM PDT 24
Finished Aug 10 05:15:15 PM PDT 24
Peak memory 198620 kb
Host smart-151fe9a0-f29b-4396-aff4-c0b0e8dc98e4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333232760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.gpio_intr_with_filter_rand_intr_event.333232760
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.702964824
Short name T518
Test name
Test status
Simulation time 332185323 ps
CPU time 3.29 seconds
Started Aug 10 05:15:09 PM PDT 24
Finished Aug 10 05:15:13 PM PDT 24
Peak memory 197456 kb
Host smart-ade33521-2736-4f94-9e36-34d8d17a4101
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702964824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.702964824
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.2584682300
Short name T267
Test name
Test status
Simulation time 14290370 ps
CPU time 0.65 seconds
Started Aug 10 05:15:07 PM PDT 24
Finished Aug 10 05:15:08 PM PDT 24
Peak memory 194648 kb
Host smart-8060fa2c-41f3-45d0-8694-e3904de3a957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584682300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.2584682300
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2937246131
Short name T642
Test name
Test status
Simulation time 84925829 ps
CPU time 0.87 seconds
Started Aug 10 05:15:05 PM PDT 24
Finished Aug 10 05:15:06 PM PDT 24
Peak memory 197112 kb
Host smart-76cde874-90da-4fec-93c3-e8e3a9976e11
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937246131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.2937246131
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.4101937243
Short name T112
Test name
Test status
Simulation time 141825168 ps
CPU time 2.48 seconds
Started Aug 10 05:15:08 PM PDT 24
Finished Aug 10 05:15:10 PM PDT 24
Peak memory 198596 kb
Host smart-d92186ac-41ac-4af0-864b-005d61d6b163
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101937243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.4101937243
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.578977641
Short name T38
Test name
Test status
Simulation time 40566645 ps
CPU time 0.81 seconds
Started Aug 10 05:15:13 PM PDT 24
Finished Aug 10 05:15:14 PM PDT 24
Peak memory 214328 kb
Host smart-e6c76a64-553a-47c3-8c43-5b376cb81049
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578977641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.578977641
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.3793003855
Short name T54
Test name
Test status
Simulation time 158656137 ps
CPU time 1.03 seconds
Started Aug 10 05:15:06 PM PDT 24
Finished Aug 10 05:15:07 PM PDT 24
Peak memory 196896 kb
Host smart-d4d60596-ac44-45a3-872f-06a56155df9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793003855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3793003855
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.4054948703
Short name T366
Test name
Test status
Simulation time 334013385 ps
CPU time 1.21 seconds
Started Aug 10 05:15:09 PM PDT 24
Finished Aug 10 05:15:10 PM PDT 24
Peak memory 197344 kb
Host smart-7553d938-1b41-47e2-907c-c9aaef090326
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054948703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.4054948703
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.3112851311
Short name T505
Test name
Test status
Simulation time 27683125647 ps
CPU time 207.09 seconds
Started Aug 10 05:15:06 PM PDT 24
Finished Aug 10 05:18:33 PM PDT 24
Peak memory 198756 kb
Host smart-cee2acc2-d2cc-4056-8c21-3c4683a917be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112851311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.3112851311
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.1402620221
Short name T556
Test name
Test status
Simulation time 42157020 ps
CPU time 0.63 seconds
Started Aug 10 05:16:13 PM PDT 24
Finished Aug 10 05:16:14 PM PDT 24
Peak memory 194780 kb
Host smart-b6052c00-b502-4932-8329-5e4dae9c574b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402620221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1402620221
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.2964706681
Short name T537
Test name
Test status
Simulation time 348281475 ps
CPU time 0.95 seconds
Started Aug 10 05:16:17 PM PDT 24
Finished Aug 10 05:16:18 PM PDT 24
Peak memory 196396 kb
Host smart-41ad6c3d-148e-48dd-bab0-7fbff885d4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964706681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.2964706681
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.3875579927
Short name T541
Test name
Test status
Simulation time 462254591 ps
CPU time 13.39 seconds
Started Aug 10 05:16:09 PM PDT 24
Finished Aug 10 05:16:22 PM PDT 24
Peak memory 197452 kb
Host smart-494ff5d0-1171-4ebf-b839-01fa0c45a29b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875579927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.3875579927
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.3380401291
Short name T300
Test name
Test status
Simulation time 217963071 ps
CPU time 0.9 seconds
Started Aug 10 05:16:14 PM PDT 24
Finished Aug 10 05:16:15 PM PDT 24
Peak memory 197180 kb
Host smart-1dbb7bcd-5981-4f27-a2bf-f49649f81d53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380401291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3380401291
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.26514530
Short name T221
Test name
Test status
Simulation time 138809562 ps
CPU time 1.14 seconds
Started Aug 10 05:16:11 PM PDT 24
Finished Aug 10 05:16:12 PM PDT 24
Peak memory 196288 kb
Host smart-8917f82f-328e-48dd-b7e8-20b509884da7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26514530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.26514530
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.755168600
Short name T622
Test name
Test status
Simulation time 47939930 ps
CPU time 2.02 seconds
Started Aug 10 05:16:10 PM PDT 24
Finished Aug 10 05:16:12 PM PDT 24
Peak memory 198648 kb
Host smart-ddd2e270-720d-4c6f-8da3-d8d47fa1a195
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755168600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.gpio_intr_with_filter_rand_intr_event.755168600
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2574211897
Short name T167
Test name
Test status
Simulation time 294758302 ps
CPU time 1.41 seconds
Started Aug 10 05:16:12 PM PDT 24
Finished Aug 10 05:16:13 PM PDT 24
Peak memory 196404 kb
Host smart-d3ab97cc-a596-424e-96e4-8770faf74216
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574211897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2574211897
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.1579299866
Short name T80
Test name
Test status
Simulation time 150786468 ps
CPU time 1.04 seconds
Started Aug 10 05:16:10 PM PDT 24
Finished Aug 10 05:16:11 PM PDT 24
Peak memory 196696 kb
Host smart-b06a6ee7-9fc3-4838-9371-9e7f54aa2c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579299866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.1579299866
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.3891001085
Short name T229
Test name
Test status
Simulation time 103051083 ps
CPU time 0.74 seconds
Started Aug 10 05:16:13 PM PDT 24
Finished Aug 10 05:16:14 PM PDT 24
Peak memory 196500 kb
Host smart-99b523d0-6404-4952-a37a-f9c23c5d6cf3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891001085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.3891001085
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3141093463
Short name T398
Test name
Test status
Simulation time 37353284 ps
CPU time 1.82 seconds
Started Aug 10 05:16:10 PM PDT 24
Finished Aug 10 05:16:12 PM PDT 24
Peak memory 198484 kb
Host smart-80eb42c6-1533-4aeb-9cf2-1645b592d183
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141093463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.3141093463
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.1596906284
Short name T678
Test name
Test status
Simulation time 49483458 ps
CPU time 0.9 seconds
Started Aug 10 05:16:08 PM PDT 24
Finished Aug 10 05:16:09 PM PDT 24
Peak memory 195920 kb
Host smart-9837dcdb-cc3a-4bc2-ac4d-4ca3aeaf8e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596906284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.1596906284
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.3738409903
Short name T53
Test name
Test status
Simulation time 37232628 ps
CPU time 0.87 seconds
Started Aug 10 05:16:09 PM PDT 24
Finished Aug 10 05:16:10 PM PDT 24
Peak memory 195692 kb
Host smart-0e449f87-8ee3-47dd-817e-4d2859c8bac4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738409903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.3738409903
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.3053061830
Short name T238
Test name
Test status
Simulation time 10171389414 ps
CPU time 137.91 seconds
Started Aug 10 05:16:08 PM PDT 24
Finished Aug 10 05:18:26 PM PDT 24
Peak memory 198816 kb
Host smart-5c7b6b02-420a-4214-951c-35f406e3a315
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053061830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.3053061830
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.3771355358
Short name T65
Test name
Test status
Simulation time 129082587660 ps
CPU time 2272.05 seconds
Started Aug 10 05:16:10 PM PDT 24
Finished Aug 10 05:54:03 PM PDT 24
Peak memory 198932 kb
Host smart-a3e71b54-cdb2-465f-9618-9787a675fe83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3771355358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.3771355358
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.301391772
Short name T588
Test name
Test status
Simulation time 15003773 ps
CPU time 0.61 seconds
Started Aug 10 05:16:10 PM PDT 24
Finished Aug 10 05:16:11 PM PDT 24
Peak memory 196136 kb
Host smart-446e14e8-2e7c-44e1-b121-ab23384270ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301391772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.301391772
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.4276696193
Short name T472
Test name
Test status
Simulation time 43728020 ps
CPU time 0.88 seconds
Started Aug 10 05:16:11 PM PDT 24
Finished Aug 10 05:16:12 PM PDT 24
Peak memory 195840 kb
Host smart-e4f3d45f-951b-4f30-b65c-72953bca4dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276696193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.4276696193
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.747880832
Short name T180
Test name
Test status
Simulation time 352394738 ps
CPU time 3.65 seconds
Started Aug 10 05:16:10 PM PDT 24
Finished Aug 10 05:16:13 PM PDT 24
Peak memory 196316 kb
Host smart-6b1186a2-7d28-4299-b3f7-ec4d92a3f217
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747880832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.747880832
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.1676434153
Short name T9
Test name
Test status
Simulation time 72098213 ps
CPU time 0.91 seconds
Started Aug 10 05:16:10 PM PDT 24
Finished Aug 10 05:16:11 PM PDT 24
Peak memory 196436 kb
Host smart-ba7976d7-261d-4eb0-827b-04d7324d660c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676434153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.1676434153
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.257519827
Short name T510
Test name
Test status
Simulation time 32757517 ps
CPU time 1.02 seconds
Started Aug 10 05:16:11 PM PDT 24
Finished Aug 10 05:16:13 PM PDT 24
Peak memory 196544 kb
Host smart-1774b221-5efa-4597-bfe0-db38bc0a1825
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257519827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.257519827
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.2201677859
Short name T485
Test name
Test status
Simulation time 472752394 ps
CPU time 1.28 seconds
Started Aug 10 05:16:09 PM PDT 24
Finished Aug 10 05:16:11 PM PDT 24
Peak memory 197252 kb
Host smart-c4f7741c-5d6b-45a4-81c5-75b401c63cbf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201677859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.2201677859
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.1432684220
Short name T336
Test name
Test status
Simulation time 33953326 ps
CPU time 0.95 seconds
Started Aug 10 05:16:11 PM PDT 24
Finished Aug 10 05:16:12 PM PDT 24
Peak memory 195060 kb
Host smart-865200b2-a72e-49b3-8f9c-bf8f062cc956
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432684220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.1432684220
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.2661135710
Short name T582
Test name
Test status
Simulation time 152863199 ps
CPU time 0.69 seconds
Started Aug 10 05:16:13 PM PDT 24
Finished Aug 10 05:16:13 PM PDT 24
Peak memory 194856 kb
Host smart-ddbb02cd-0638-4813-8c93-070140dd8baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661135710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2661135710
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.41970943
Short name T374
Test name
Test status
Simulation time 48011672 ps
CPU time 1.16 seconds
Started Aug 10 05:16:10 PM PDT 24
Finished Aug 10 05:16:12 PM PDT 24
Peak memory 196532 kb
Host smart-8b247d4c-926f-447c-ba9d-6c0a3f698223
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41970943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullup_
pulldown.41970943
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1724639878
Short name T546
Test name
Test status
Simulation time 1079987828 ps
CPU time 5.51 seconds
Started Aug 10 05:16:19 PM PDT 24
Finished Aug 10 05:16:25 PM PDT 24
Peak memory 198432 kb
Host smart-0fbd3acf-2fd3-467b-821a-d07a4b53c6bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724639878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.1724639878
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.1863808415
Short name T269
Test name
Test status
Simulation time 73539221 ps
CPU time 1.21 seconds
Started Aug 10 05:16:10 PM PDT 24
Finished Aug 10 05:16:11 PM PDT 24
Peak memory 196392 kb
Host smart-cee5c150-5653-444b-a6cb-6c325fb1dcba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863808415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.1863808415
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.4151537790
Short name T184
Test name
Test status
Simulation time 70318451 ps
CPU time 1.16 seconds
Started Aug 10 05:16:11 PM PDT 24
Finished Aug 10 05:16:13 PM PDT 24
Peak memory 196460 kb
Host smart-f1e021dd-daf9-4aaa-8a4f-271effa75fa1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151537790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.4151537790
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.1153125998
Short name T59
Test name
Test status
Simulation time 14585488977 ps
CPU time 176.55 seconds
Started Aug 10 05:16:18 PM PDT 24
Finished Aug 10 05:19:14 PM PDT 24
Peak memory 198604 kb
Host smart-2d0f40f9-ba5b-4dce-babb-d1ffacf02b2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153125998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.1153125998
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.2364480415
Short name T68
Test name
Test status
Simulation time 105792905568 ps
CPU time 391.2 seconds
Started Aug 10 05:16:10 PM PDT 24
Finished Aug 10 05:22:41 PM PDT 24
Peak memory 198796 kb
Host smart-0b66a57d-6108-452f-9db0-a5b9c1f7ba79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2364480415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.2364480415
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.1707557478
Short name T320
Test name
Test status
Simulation time 15142853 ps
CPU time 0.63 seconds
Started Aug 10 05:16:24 PM PDT 24
Finished Aug 10 05:16:25 PM PDT 24
Peak memory 194512 kb
Host smart-49a82560-e37d-40d6-8403-b6c9c94a7830
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707557478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1707557478
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.3881713111
Short name T255
Test name
Test status
Simulation time 89506802 ps
CPU time 0.68 seconds
Started Aug 10 05:16:12 PM PDT 24
Finished Aug 10 05:16:13 PM PDT 24
Peak memory 194772 kb
Host smart-86198edb-7a33-4357-9720-f563ba496c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881713111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.3881713111
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.3753754187
Short name T333
Test name
Test status
Simulation time 925359679 ps
CPU time 23.49 seconds
Started Aug 10 05:16:11 PM PDT 24
Finished Aug 10 05:16:34 PM PDT 24
Peak memory 197448 kb
Host smart-a65c9731-3b31-46f1-af36-d086b8dda1cd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753754187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.3753754187
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.2362225271
Short name T450
Test name
Test status
Simulation time 62931955 ps
CPU time 0.66 seconds
Started Aug 10 05:16:11 PM PDT 24
Finished Aug 10 05:16:12 PM PDT 24
Peak memory 194852 kb
Host smart-7bfb3fe8-c8fc-4bdb-ad2f-e7e7072ffe94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362225271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.2362225271
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.2652146722
Short name T526
Test name
Test status
Simulation time 37086937 ps
CPU time 0.99 seconds
Started Aug 10 05:16:11 PM PDT 24
Finished Aug 10 05:16:13 PM PDT 24
Peak memory 196664 kb
Host smart-8adb8bf4-78f1-4747-9d32-e80daf73ee3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652146722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2652146722
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2553498781
Short name T607
Test name
Test status
Simulation time 302032428 ps
CPU time 3.22 seconds
Started Aug 10 05:16:11 PM PDT 24
Finished Aug 10 05:16:14 PM PDT 24
Peak memory 198468 kb
Host smart-ebeae8c1-7f37-4ab0-a475-83ca8d8a27c6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553498781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2553498781
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.3989570210
Short name T164
Test name
Test status
Simulation time 144681536 ps
CPU time 2.92 seconds
Started Aug 10 05:16:11 PM PDT 24
Finished Aug 10 05:16:15 PM PDT 24
Peak memory 197432 kb
Host smart-9b671397-e114-4691-a60d-6b39667fae3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989570210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.3989570210
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3983234491
Short name T77
Test name
Test status
Simulation time 248167761 ps
CPU time 1.36 seconds
Started Aug 10 05:16:10 PM PDT 24
Finished Aug 10 05:16:12 PM PDT 24
Peak memory 196420 kb
Host smart-90792405-62c3-4a81-98f4-14ae30c3006e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983234491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3983234491
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.3278682577
Short name T32
Test name
Test status
Simulation time 60761534 ps
CPU time 1.18 seconds
Started Aug 10 05:16:18 PM PDT 24
Finished Aug 10 05:16:19 PM PDT 24
Peak memory 197520 kb
Host smart-622a9212-e2dd-4e34-a6c2-2c44e42a52fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278682577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.3278682577
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1397785870
Short name T276
Test name
Test status
Simulation time 1352427517 ps
CPU time 5.6 seconds
Started Aug 10 05:16:11 PM PDT 24
Finished Aug 10 05:16:16 PM PDT 24
Peak memory 198428 kb
Host smart-3ef405ba-c6d1-4267-a264-e04141adbca9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397785870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.1397785870
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1030227255
Short name T127
Test name
Test status
Simulation time 872266133 ps
CPU time 1.35 seconds
Started Aug 10 05:16:13 PM PDT 24
Finished Aug 10 05:16:14 PM PDT 24
Peak memory 196228 kb
Host smart-ed163450-d2cd-4b98-95b2-5d9a2f979658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030227255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1030227255
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.1487353341
Short name T482
Test name
Test status
Simulation time 1138532647 ps
CPU time 1.46 seconds
Started Aug 10 05:16:11 PM PDT 24
Finished Aug 10 05:16:12 PM PDT 24
Peak memory 197412 kb
Host smart-1217b2d2-0e7d-4291-84c0-aa457c43a371
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487353341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.1487353341
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.3713124377
Short name T528
Test name
Test status
Simulation time 66689281361 ps
CPU time 143.43 seconds
Started Aug 10 05:16:26 PM PDT 24
Finished Aug 10 05:18:49 PM PDT 24
Peak memory 198572 kb
Host smart-c92b1984-7b97-4b79-ae4b-93ed5aa83186
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713124377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.3713124377
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.454280021
Short name T230
Test name
Test status
Simulation time 14187631 ps
CPU time 0.57 seconds
Started Aug 10 05:16:16 PM PDT 24
Finished Aug 10 05:16:17 PM PDT 24
Peak memory 194372 kb
Host smart-cb36f180-9b13-4d91-90c9-766b99834f99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454280021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.454280021
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.2046873162
Short name T79
Test name
Test status
Simulation time 85716327 ps
CPU time 0.89 seconds
Started Aug 10 05:16:19 PM PDT 24
Finished Aug 10 05:16:20 PM PDT 24
Peak memory 196852 kb
Host smart-b89ca247-dd39-4386-a97e-9c915ec038de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046873162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.2046873162
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.2517584555
Short name T691
Test name
Test status
Simulation time 1608894496 ps
CPU time 10.98 seconds
Started Aug 10 05:16:19 PM PDT 24
Finished Aug 10 05:16:30 PM PDT 24
Peak memory 196128 kb
Host smart-e9232bff-2b3c-42ab-8467-50e6c6de14a2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517584555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.2517584555
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.1118759342
Short name T649
Test name
Test status
Simulation time 99355476 ps
CPU time 1.22 seconds
Started Aug 10 05:16:17 PM PDT 24
Finished Aug 10 05:16:19 PM PDT 24
Peak memory 197124 kb
Host smart-24fe5ee2-2055-4e9f-920d-5fe2d2ec1188
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118759342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1118759342
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.3434454983
Short name T307
Test name
Test status
Simulation time 77996409 ps
CPU time 1.21 seconds
Started Aug 10 05:16:19 PM PDT 24
Finished Aug 10 05:16:20 PM PDT 24
Peak memory 197388 kb
Host smart-87098655-8666-4982-94cb-f6eb33d9409b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434454983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.3434454983
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.927691517
Short name T137
Test name
Test status
Simulation time 1180689404 ps
CPU time 3.57 seconds
Started Aug 10 05:16:16 PM PDT 24
Finished Aug 10 05:16:19 PM PDT 24
Peak memory 197092 kb
Host smart-15207503-747f-4be4-992e-738283e4defc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927691517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.gpio_intr_with_filter_rand_intr_event.927691517
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.4000032383
Short name T239
Test name
Test status
Simulation time 25870172 ps
CPU time 0.85 seconds
Started Aug 10 05:16:16 PM PDT 24
Finished Aug 10 05:16:17 PM PDT 24
Peak memory 195560 kb
Host smart-5e43faea-b4a3-4877-b56a-119238939a3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000032383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.4000032383
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.2214063907
Short name T486
Test name
Test status
Simulation time 132662768 ps
CPU time 0.79 seconds
Started Aug 10 05:16:15 PM PDT 24
Finished Aug 10 05:16:16 PM PDT 24
Peak memory 196628 kb
Host smart-02ee2770-5e64-43a9-96ba-dab141798bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214063907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.2214063907
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.2961454522
Short name T386
Test name
Test status
Simulation time 85017596 ps
CPU time 0.92 seconds
Started Aug 10 05:16:16 PM PDT 24
Finished Aug 10 05:16:17 PM PDT 24
Peak memory 196488 kb
Host smart-cdd479ec-3f71-4b72-b895-9e250f754a66
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961454522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.2961454522
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.899143356
Short name T661
Test name
Test status
Simulation time 1765781503 ps
CPU time 5.58 seconds
Started Aug 10 05:16:20 PM PDT 24
Finished Aug 10 05:16:26 PM PDT 24
Peak memory 198700 kb
Host smart-c344bb86-1072-4ec7-90ca-4df25c69282d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899143356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ran
dom_long_reg_writes_reg_reads.899143356
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.351333775
Short name T168
Test name
Test status
Simulation time 50189382 ps
CPU time 1.03 seconds
Started Aug 10 05:16:15 PM PDT 24
Finished Aug 10 05:16:16 PM PDT 24
Peak memory 196984 kb
Host smart-6e7786ed-7c5a-41ef-9642-360f8a0368d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351333775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.351333775
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.1313964254
Short name T151
Test name
Test status
Simulation time 85301806 ps
CPU time 1.38 seconds
Started Aug 10 05:16:19 PM PDT 24
Finished Aug 10 05:16:20 PM PDT 24
Peak memory 198760 kb
Host smart-13cc94ce-c66f-4536-a5e3-fc81f9bcfb98
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313964254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.1313964254
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3669954543
Short name T252
Test name
Test status
Simulation time 20903570304 ps
CPU time 69.1 seconds
Started Aug 10 05:16:17 PM PDT 24
Finished Aug 10 05:17:26 PM PDT 24
Peak memory 198632 kb
Host smart-5b31838c-92cc-49eb-bc0f-3e3544144407
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669954543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3669954543
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2585659891
Short name T667
Test name
Test status
Simulation time 68206884 ps
CPU time 0.59 seconds
Started Aug 10 05:16:27 PM PDT 24
Finished Aug 10 05:16:27 PM PDT 24
Peak memory 194456 kb
Host smart-8ed9cded-6ca8-414c-8989-3e002e7a6ce6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585659891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2585659891
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.803686991
Short name T253
Test name
Test status
Simulation time 152402765 ps
CPU time 1.07 seconds
Started Aug 10 05:16:17 PM PDT 24
Finished Aug 10 05:16:18 PM PDT 24
Peak memory 196524 kb
Host smart-18b08f23-b292-43cb-9332-b71ae6df7d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803686991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.803686991
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.997593050
Short name T297
Test name
Test status
Simulation time 493228028 ps
CPU time 14.38 seconds
Started Aug 10 05:16:26 PM PDT 24
Finished Aug 10 05:16:40 PM PDT 24
Peak memory 197328 kb
Host smart-d719851c-7ad9-470e-ae0a-6930002c6854
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997593050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stres
s.997593050
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3203510144
Short name T227
Test name
Test status
Simulation time 113596564 ps
CPU time 0.66 seconds
Started Aug 10 05:16:25 PM PDT 24
Finished Aug 10 05:16:26 PM PDT 24
Peak memory 195952 kb
Host smart-4f6d1e6c-233d-4a2c-9329-eddc436374e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203510144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3203510144
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1821491031
Short name T468
Test name
Test status
Simulation time 50054726 ps
CPU time 1.4 seconds
Started Aug 10 05:16:17 PM PDT 24
Finished Aug 10 05:16:19 PM PDT 24
Peak memory 198580 kb
Host smart-e9c3cb68-3d5b-4766-86f6-f72b3fcd997f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821491031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1821491031
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1853287664
Short name T323
Test name
Test status
Simulation time 96310021 ps
CPU time 3.75 seconds
Started Aug 10 05:16:17 PM PDT 24
Finished Aug 10 05:16:21 PM PDT 24
Peak memory 198524 kb
Host smart-15942580-531e-45fa-9509-4df4d8f0af18
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853287664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1853287664
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2043589519
Short name T373
Test name
Test status
Simulation time 683569046 ps
CPU time 3.1 seconds
Started Aug 10 05:16:16 PM PDT 24
Finished Aug 10 05:16:20 PM PDT 24
Peak memory 197768 kb
Host smart-478de516-270f-4a06-ba29-152e9633202b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043589519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2043589519
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.2178322222
Short name T690
Test name
Test status
Simulation time 32376677 ps
CPU time 0.9 seconds
Started Aug 10 05:16:17 PM PDT 24
Finished Aug 10 05:16:18 PM PDT 24
Peak memory 196036 kb
Host smart-db444546-7707-456e-8803-690d8037f3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178322222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2178322222
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.3073243800
Short name T400
Test name
Test status
Simulation time 20110887 ps
CPU time 0.64 seconds
Started Aug 10 05:16:19 PM PDT 24
Finished Aug 10 05:16:20 PM PDT 24
Peak memory 194888 kb
Host smart-968ac96a-91b1-4036-86a4-caf6cea1ba59
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073243800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.3073243800
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2843310580
Short name T367
Test name
Test status
Simulation time 236387055 ps
CPU time 1.37 seconds
Started Aug 10 05:16:27 PM PDT 24
Finished Aug 10 05:16:29 PM PDT 24
Peak memory 198572 kb
Host smart-bcf29f51-4dc6-432e-af01-3cea380bbeca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843310580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2843310580
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.1469237022
Short name T139
Test name
Test status
Simulation time 185201213 ps
CPU time 1.18 seconds
Started Aug 10 05:16:17 PM PDT 24
Finished Aug 10 05:16:19 PM PDT 24
Peak memory 196224 kb
Host smart-f26d6402-458c-4af7-b800-3ecad043affe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469237022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.1469237022
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.1071565901
Short name T627
Test name
Test status
Simulation time 355598001 ps
CPU time 1.05 seconds
Started Aug 10 05:16:25 PM PDT 24
Finished Aug 10 05:16:26 PM PDT 24
Peak memory 196100 kb
Host smart-2e5b932f-e5c3-441f-956e-949d5deec378
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071565901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.1071565901
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.206507423
Short name T520
Test name
Test status
Simulation time 22105458974 ps
CPU time 152.27 seconds
Started Aug 10 05:16:26 PM PDT 24
Finished Aug 10 05:18:59 PM PDT 24
Peak memory 198656 kb
Host smart-a2c04aee-41cc-4c2c-b521-4513d5b15c16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206507423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g
pio_stress_all.206507423
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.318983365
Short name T393
Test name
Test status
Simulation time 14086132 ps
CPU time 0.57 seconds
Started Aug 10 05:16:28 PM PDT 24
Finished Aug 10 05:16:28 PM PDT 24
Peak memory 194508 kb
Host smart-682f668e-5876-4bf9-ae72-1e67aafea2c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318983365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.318983365
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.1239292919
Short name T140
Test name
Test status
Simulation time 79269694 ps
CPU time 0.77 seconds
Started Aug 10 05:16:28 PM PDT 24
Finished Aug 10 05:16:29 PM PDT 24
Peak memory 195948 kb
Host smart-a1e27873-af51-4e3c-b773-a0c555c1c025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239292919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.1239292919
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.3715586875
Short name T350
Test name
Test status
Simulation time 199336087 ps
CPU time 10.85 seconds
Started Aug 10 05:16:34 PM PDT 24
Finished Aug 10 05:16:45 PM PDT 24
Peak memory 197336 kb
Host smart-7a2b8d1d-c785-4737-951c-37ddb352a70c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715586875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.3715586875
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2519181930
Short name T50
Test name
Test status
Simulation time 48957242 ps
CPU time 0.87 seconds
Started Aug 10 05:16:30 PM PDT 24
Finished Aug 10 05:16:31 PM PDT 24
Peak memory 196356 kb
Host smart-4b864676-1bf0-4818-8131-44e702b54cff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519181930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2519181930
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1886740548
Short name T289
Test name
Test status
Simulation time 63604129 ps
CPU time 0.97 seconds
Started Aug 10 05:16:28 PM PDT 24
Finished Aug 10 05:16:29 PM PDT 24
Peak memory 198064 kb
Host smart-f3794387-3e58-48af-90fb-704319a8ab54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886740548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1886740548
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.202037425
Short name T237
Test name
Test status
Simulation time 75098697 ps
CPU time 3.19 seconds
Started Aug 10 05:16:27 PM PDT 24
Finished Aug 10 05:16:30 PM PDT 24
Peak memory 198692 kb
Host smart-57acb76c-650a-4353-89e0-d1421698a097
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202037425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.gpio_intr_with_filter_rand_intr_event.202037425
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.4030640177
Short name T430
Test name
Test status
Simulation time 60854019 ps
CPU time 2 seconds
Started Aug 10 05:16:29 PM PDT 24
Finished Aug 10 05:16:31 PM PDT 24
Peak memory 197576 kb
Host smart-c0169b71-c0b5-495d-8fb4-9c34fc6a42f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030640177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.4030640177
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.1051571163
Short name T352
Test name
Test status
Simulation time 107565691 ps
CPU time 1.14 seconds
Started Aug 10 05:16:26 PM PDT 24
Finished Aug 10 05:16:28 PM PDT 24
Peak memory 196548 kb
Host smart-5d1b18ff-914c-44d7-80cd-e3074ef2d76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051571163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.1051571163
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.1822551050
Short name T332
Test name
Test status
Simulation time 47684197 ps
CPU time 0.79 seconds
Started Aug 10 05:16:28 PM PDT 24
Finished Aug 10 05:16:29 PM PDT 24
Peak memory 195764 kb
Host smart-7abd78b1-129c-4d2a-97dc-a362dec5215b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822551050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.1822551050
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_smoke.1776832381
Short name T474
Test name
Test status
Simulation time 120950630 ps
CPU time 1.18 seconds
Started Aug 10 05:16:27 PM PDT 24
Finished Aug 10 05:16:28 PM PDT 24
Peak memory 196084 kb
Host smart-ecc5e640-3e51-464f-88ba-44c0478a24b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776832381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.1776832381
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.1622003402
Short name T179
Test name
Test status
Simulation time 83138006 ps
CPU time 1.08 seconds
Started Aug 10 05:16:25 PM PDT 24
Finished Aug 10 05:16:26 PM PDT 24
Peak memory 196188 kb
Host smart-4bbcdaca-c200-404f-9da8-51103781e64a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622003402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.1622003402
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.3683453159
Short name T628
Test name
Test status
Simulation time 3275613452 ps
CPU time 40.22 seconds
Started Aug 10 05:16:28 PM PDT 24
Finished Aug 10 05:17:09 PM PDT 24
Peak memory 198640 kb
Host smart-f86979d5-d6ff-4970-b3ff-b017a0573fa4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683453159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.3683453159
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.1125555937
Short name T596
Test name
Test status
Simulation time 15194884 ps
CPU time 0.59 seconds
Started Aug 10 05:16:27 PM PDT 24
Finished Aug 10 05:16:28 PM PDT 24
Peak memory 194552 kb
Host smart-886f5e41-0852-4f5b-9c39-2e7304dbbc53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125555937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.1125555937
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.4071620456
Short name T147
Test name
Test status
Simulation time 240791495 ps
CPU time 0.88 seconds
Started Aug 10 05:16:27 PM PDT 24
Finished Aug 10 05:16:28 PM PDT 24
Peak memory 196864 kb
Host smart-9866d438-452d-4281-8da1-93bf9ebcc25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071620456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.4071620456
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.544472288
Short name T680
Test name
Test status
Simulation time 2616072902 ps
CPU time 20.72 seconds
Started Aug 10 05:16:28 PM PDT 24
Finished Aug 10 05:16:49 PM PDT 24
Peak memory 197020 kb
Host smart-c21e8803-5d1b-46e0-91a4-7ed807668d3a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544472288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stres
s.544472288
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2551082075
Short name T188
Test name
Test status
Simulation time 30256248 ps
CPU time 0.61 seconds
Started Aug 10 05:16:26 PM PDT 24
Finished Aug 10 05:16:27 PM PDT 24
Peak memory 194684 kb
Host smart-ae653e3e-6179-4f96-993a-d4acafb2c41c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551082075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2551082075
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.3558857687
Short name T296
Test name
Test status
Simulation time 533686728 ps
CPU time 1.05 seconds
Started Aug 10 05:16:27 PM PDT 24
Finished Aug 10 05:16:28 PM PDT 24
Peak memory 196576 kb
Host smart-388e1309-cfa9-4457-8998-0e86e45e2b07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558857687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.3558857687
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.1200592877
Short name T509
Test name
Test status
Simulation time 50711293 ps
CPU time 2.17 seconds
Started Aug 10 05:16:26 PM PDT 24
Finished Aug 10 05:16:28 PM PDT 24
Peak memory 198628 kb
Host smart-7df66262-25ff-481d-a965-d5669bc6d8af
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200592877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.1200592877
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.2631675715
Short name T105
Test name
Test status
Simulation time 53440732 ps
CPU time 1.25 seconds
Started Aug 10 05:16:26 PM PDT 24
Finished Aug 10 05:16:27 PM PDT 24
Peak memory 196980 kb
Host smart-64443ce5-161a-4b5c-ba0c-edb1e1541193
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631675715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.2631675715
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.1801529276
Short name T312
Test name
Test status
Simulation time 64136866 ps
CPU time 1.37 seconds
Started Aug 10 05:16:30 PM PDT 24
Finished Aug 10 05:16:31 PM PDT 24
Peak memory 196636 kb
Host smart-48875de0-0abb-43f1-a9bf-2aabb0cf3d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801529276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1801529276
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.3771780010
Short name T17
Test name
Test status
Simulation time 37920497 ps
CPU time 0.84 seconds
Started Aug 10 05:16:28 PM PDT 24
Finished Aug 10 05:16:29 PM PDT 24
Peak memory 196872 kb
Host smart-a67e410b-6a40-4eeb-9a49-c5be46e71bf9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771780010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.3771780010
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.2460229616
Short name T543
Test name
Test status
Simulation time 1222825202 ps
CPU time 4.24 seconds
Started Aug 10 05:16:28 PM PDT 24
Finished Aug 10 05:16:32 PM PDT 24
Peak memory 198480 kb
Host smart-bc6b3f7a-160e-46ed-a2a0-8c2836f2d410
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460229616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.2460229616
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.4055349135
Short name T599
Test name
Test status
Simulation time 28897631 ps
CPU time 0.94 seconds
Started Aug 10 05:16:29 PM PDT 24
Finished Aug 10 05:16:30 PM PDT 24
Peak memory 196200 kb
Host smart-3e6fbe3c-1589-4e54-ba2b-aa036f10954d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055349135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.4055349135
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.3644680155
Short name T551
Test name
Test status
Simulation time 66761523 ps
CPU time 1.27 seconds
Started Aug 10 05:16:25 PM PDT 24
Finished Aug 10 05:16:27 PM PDT 24
Peak memory 196548 kb
Host smart-7dcd2bf2-57c3-4a57-9e70-93eff00c8035
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644680155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.3644680155
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1220317018
Short name T302
Test name
Test status
Simulation time 2518066273 ps
CPU time 27.51 seconds
Started Aug 10 05:16:28 PM PDT 24
Finished Aug 10 05:16:55 PM PDT 24
Peak memory 198792 kb
Host smart-ad17afe3-0d43-407e-8182-7d7b803ea511
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220317018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1220317018
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.2074978417
Short name T458
Test name
Test status
Simulation time 14932726 ps
CPU time 0.61 seconds
Started Aug 10 05:16:27 PM PDT 24
Finished Aug 10 05:16:28 PM PDT 24
Peak memory 194504 kb
Host smart-c0d8f325-7833-4591-8cae-a50af51383d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074978417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.2074978417
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.1501046707
Short name T335
Test name
Test status
Simulation time 25567033 ps
CPU time 0.7 seconds
Started Aug 10 05:16:27 PM PDT 24
Finished Aug 10 05:16:28 PM PDT 24
Peak memory 194796 kb
Host smart-7990c806-c42b-464c-a1ce-66365c616e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501046707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.1501046707
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.2049598384
Short name T136
Test name
Test status
Simulation time 2697214330 ps
CPU time 23.96 seconds
Started Aug 10 05:16:27 PM PDT 24
Finished Aug 10 05:16:52 PM PDT 24
Peak memory 198608 kb
Host smart-6697cfcc-9417-4af0-8c44-b72fd2acc499
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049598384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.2049598384
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.2115940431
Short name T211
Test name
Test status
Simulation time 95262996 ps
CPU time 0.82 seconds
Started Aug 10 05:16:28 PM PDT 24
Finished Aug 10 05:16:29 PM PDT 24
Peak memory 196396 kb
Host smart-20aa1c35-7f4d-4f0e-bd5e-016c8a5e1e66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115940431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.2115940431
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2779434690
Short name T600
Test name
Test status
Simulation time 137177821 ps
CPU time 1.24 seconds
Started Aug 10 05:16:26 PM PDT 24
Finished Aug 10 05:16:28 PM PDT 24
Peak memory 196536 kb
Host smart-abad3553-b182-4424-9dd8-ea7b7fb54704
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779434690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2779434690
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.390086900
Short name T434
Test name
Test status
Simulation time 76503832 ps
CPU time 3.07 seconds
Started Aug 10 05:16:26 PM PDT 24
Finished Aug 10 05:16:30 PM PDT 24
Peak memory 198480 kb
Host smart-84622e4e-d6a4-417e-aedf-6f8c435f34d5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390086900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.gpio_intr_with_filter_rand_intr_event.390086900
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.1396920075
Short name T658
Test name
Test status
Simulation time 591601221 ps
CPU time 1.89 seconds
Started Aug 10 05:16:29 PM PDT 24
Finished Aug 10 05:16:31 PM PDT 24
Peak memory 196624 kb
Host smart-4f980796-2526-4d97-af28-3059ecd6d88c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396920075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.1396920075
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.1259770168
Short name T378
Test name
Test status
Simulation time 31655090 ps
CPU time 1.08 seconds
Started Aug 10 05:16:29 PM PDT 24
Finished Aug 10 05:16:30 PM PDT 24
Peak memory 196576 kb
Host smart-556260cb-1fc5-4225-be73-6860309fd964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259770168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.1259770168
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3967795576
Short name T493
Test name
Test status
Simulation time 59992440 ps
CPU time 1.25 seconds
Started Aug 10 05:16:26 PM PDT 24
Finished Aug 10 05:16:28 PM PDT 24
Peak memory 197144 kb
Host smart-e382ac02-89a5-48ed-bdb9-d555a38a495c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967795576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3967795576
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.167975943
Short name T414
Test name
Test status
Simulation time 227361874 ps
CPU time 5.45 seconds
Started Aug 10 05:16:26 PM PDT 24
Finished Aug 10 05:16:32 PM PDT 24
Peak memory 198532 kb
Host smart-5b4024e6-92eb-40ae-a060-2e0f7cee67bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167975943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ran
dom_long_reg_writes_reg_reads.167975943
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.826840651
Short name T404
Test name
Test status
Simulation time 92860174 ps
CPU time 0.85 seconds
Started Aug 10 05:16:26 PM PDT 24
Finished Aug 10 05:16:27 PM PDT 24
Peak memory 196644 kb
Host smart-5653bf09-b284-47c3-a6a3-967d6d052b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826840651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.826840651
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3149546902
Short name T242
Test name
Test status
Simulation time 1580011484 ps
CPU time 1.47 seconds
Started Aug 10 05:16:25 PM PDT 24
Finished Aug 10 05:16:27 PM PDT 24
Peak memory 196252 kb
Host smart-b1513bd9-3388-4d1f-9177-13b0627bc011
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149546902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3149546902
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.2039105025
Short name T1
Test name
Test status
Simulation time 56150679920 ps
CPU time 159.98 seconds
Started Aug 10 05:16:27 PM PDT 24
Finished Aug 10 05:19:08 PM PDT 24
Peak memory 198640 kb
Host smart-74887713-3b19-41a5-a0fb-1809d06f3a7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039105025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.2039105025
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2466957025
Short name T481
Test name
Test status
Simulation time 40162747 ps
CPU time 0.6 seconds
Started Aug 10 05:16:29 PM PDT 24
Finished Aug 10 05:16:30 PM PDT 24
Peak memory 195044 kb
Host smart-4eb0acf3-6b4f-4d91-a6dc-bf332bb497eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466957025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2466957025
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2326726532
Short name T231
Test name
Test status
Simulation time 64093414 ps
CPU time 0.86 seconds
Started Aug 10 05:16:28 PM PDT 24
Finished Aug 10 05:16:29 PM PDT 24
Peak memory 196524 kb
Host smart-8b52e08d-92a0-4f55-9a75-fe8bf710e6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326726532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2326726532
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1713041673
Short name T686
Test name
Test status
Simulation time 1991015954 ps
CPU time 16.86 seconds
Started Aug 10 05:16:27 PM PDT 24
Finished Aug 10 05:16:44 PM PDT 24
Peak memory 197604 kb
Host smart-cace6346-d45a-48c7-aa80-a31b12049803
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713041673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1713041673
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.1674031069
Short name T206
Test name
Test status
Simulation time 122309584 ps
CPU time 0.79 seconds
Started Aug 10 05:16:25 PM PDT 24
Finished Aug 10 05:16:26 PM PDT 24
Peak memory 196248 kb
Host smart-75df7a64-b673-4b4c-b745-3618516a790d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674031069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.1674031069
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3749396028
Short name T692
Test name
Test status
Simulation time 140631274 ps
CPU time 1.4 seconds
Started Aug 10 05:16:26 PM PDT 24
Finished Aug 10 05:16:28 PM PDT 24
Peak memory 198676 kb
Host smart-3d2f806a-a6ce-448d-80a4-7a8205fff284
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749396028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3749396028
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.724605854
Short name T407
Test name
Test status
Simulation time 78331088 ps
CPU time 1.31 seconds
Started Aug 10 05:16:29 PM PDT 24
Finished Aug 10 05:16:30 PM PDT 24
Peak memory 198472 kb
Host smart-5f0b7b6a-0b6c-4c9e-bdd5-4f7eaf9c6840
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724605854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.gpio_intr_with_filter_rand_intr_event.724605854
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.1542628483
Short name T118
Test name
Test status
Simulation time 309444717 ps
CPU time 3.24 seconds
Started Aug 10 05:16:28 PM PDT 24
Finished Aug 10 05:16:31 PM PDT 24
Peak memory 197704 kb
Host smart-935d65c9-3fb3-4685-af29-322b5f30cee9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542628483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.1542628483
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.4066331461
Short name T611
Test name
Test status
Simulation time 93212071 ps
CPU time 0.83 seconds
Started Aug 10 05:16:29 PM PDT 24
Finished Aug 10 05:16:30 PM PDT 24
Peak memory 196612 kb
Host smart-924f6865-feb2-4f49-a1f5-67fa31e83fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066331461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.4066331461
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1345918953
Short name T277
Test name
Test status
Simulation time 27539825 ps
CPU time 0.99 seconds
Started Aug 10 05:16:27 PM PDT 24
Finished Aug 10 05:16:29 PM PDT 24
Peak memory 196672 kb
Host smart-ce0e1e17-4c36-41d6-90ee-487531053a07
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345918953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1345918953
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.3552811094
Short name T693
Test name
Test status
Simulation time 50214282 ps
CPU time 2.3 seconds
Started Aug 10 05:16:29 PM PDT 24
Finished Aug 10 05:16:31 PM PDT 24
Peak memory 198400 kb
Host smart-7893c2a8-9b2c-4b65-a8e4-3732989ef11e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552811094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.3552811094
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.1918136996
Short name T685
Test name
Test status
Simulation time 207721788 ps
CPU time 1.09 seconds
Started Aug 10 05:16:28 PM PDT 24
Finished Aug 10 05:16:29 PM PDT 24
Peak memory 196404 kb
Host smart-9deb5498-5b50-4b09-ae7a-d7ced941e9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918136996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.1918136996
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3805426455
Short name T631
Test name
Test status
Simulation time 137971520 ps
CPU time 0.97 seconds
Started Aug 10 05:16:28 PM PDT 24
Finished Aug 10 05:16:29 PM PDT 24
Peak memory 196384 kb
Host smart-67842957-864f-4186-9ad9-a9e80d168d67
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805426455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3805426455
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.1964708736
Short name T638
Test name
Test status
Simulation time 9586483125 ps
CPU time 109.11 seconds
Started Aug 10 05:16:42 PM PDT 24
Finished Aug 10 05:18:31 PM PDT 24
Peak memory 198764 kb
Host smart-278a1740-eb05-4ecc-9090-91a154b63c5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964708736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.1964708736
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2075666479
Short name T425
Test name
Test status
Simulation time 11303742 ps
CPU time 0.58 seconds
Started Aug 10 05:16:27 PM PDT 24
Finished Aug 10 05:16:28 PM PDT 24
Peak memory 194384 kb
Host smart-ded109fe-f618-4b5f-9b74-3f95a48cc377
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075666479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2075666479
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.1144532655
Short name T660
Test name
Test status
Simulation time 33520355 ps
CPU time 0.85 seconds
Started Aug 10 05:16:31 PM PDT 24
Finished Aug 10 05:16:32 PM PDT 24
Peak memory 196648 kb
Host smart-5c2c311b-244c-4209-be9a-2d75a90c8573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144532655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.1144532655
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1219015297
Short name T371
Test name
Test status
Simulation time 587016715 ps
CPU time 8.06 seconds
Started Aug 10 05:16:31 PM PDT 24
Finished Aug 10 05:16:39 PM PDT 24
Peak memory 197516 kb
Host smart-55df9a87-24a0-4476-abff-db206845d31d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219015297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1219015297
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1430660670
Short name T8
Test name
Test status
Simulation time 151155145 ps
CPU time 0.69 seconds
Started Aug 10 05:16:34 PM PDT 24
Finished Aug 10 05:16:35 PM PDT 24
Peak memory 195328 kb
Host smart-65e75ad3-1128-4152-99ac-f6e82aee985f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430660670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1430660670
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.412685600
Short name T293
Test name
Test status
Simulation time 104313131 ps
CPU time 0.74 seconds
Started Aug 10 05:16:42 PM PDT 24
Finished Aug 10 05:16:43 PM PDT 24
Peak memory 195904 kb
Host smart-09f68649-04db-4ae5-a4d2-24ebb7b32b5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412685600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.412685600
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.267859873
Short name T475
Test name
Test status
Simulation time 55102062 ps
CPU time 1.38 seconds
Started Aug 10 05:16:29 PM PDT 24
Finished Aug 10 05:16:31 PM PDT 24
Peak memory 196976 kb
Host smart-0cefc748-128a-4e83-afb4-fb2ee366b11a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267859873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.gpio_intr_with_filter_rand_intr_event.267859873
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.1068348543
Short name T272
Test name
Test status
Simulation time 352791353 ps
CPU time 2 seconds
Started Aug 10 05:16:29 PM PDT 24
Finished Aug 10 05:16:31 PM PDT 24
Peak memory 196456 kb
Host smart-e30de5b6-1a93-40d8-a02f-17d466ef5fdd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068348543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.1068348543
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.3615015504
Short name T672
Test name
Test status
Simulation time 68951195 ps
CPU time 1.21 seconds
Started Aug 10 05:16:31 PM PDT 24
Finished Aug 10 05:16:32 PM PDT 24
Peak memory 196464 kb
Host smart-4d1a411f-be14-4cad-b850-fd75beeb6127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615015504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.3615015504
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3062207179
Short name T391
Test name
Test status
Simulation time 223525585 ps
CPU time 1.04 seconds
Started Aug 10 05:16:29 PM PDT 24
Finished Aug 10 05:16:31 PM PDT 24
Peak memory 196628 kb
Host smart-464cd558-01d2-4944-b764-7d21891d3e8d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062207179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3062207179
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1809355825
Short name T107
Test name
Test status
Simulation time 1205987991 ps
CPU time 4.86 seconds
Started Aug 10 05:16:28 PM PDT 24
Finished Aug 10 05:16:33 PM PDT 24
Peak memory 198404 kb
Host smart-da3d9fd8-5c65-4b47-a786-f14d3fe15b8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809355825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1809355825
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1565902178
Short name T341
Test name
Test status
Simulation time 84598011 ps
CPU time 1.42 seconds
Started Aug 10 05:16:31 PM PDT 24
Finished Aug 10 05:16:32 PM PDT 24
Peak memory 198632 kb
Host smart-c54f53a5-0129-44f4-b917-0121dff5e404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565902178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1565902178
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1657891074
Short name T319
Test name
Test status
Simulation time 135338031 ps
CPU time 1.3 seconds
Started Aug 10 05:16:28 PM PDT 24
Finished Aug 10 05:16:30 PM PDT 24
Peak memory 198424 kb
Host smart-d03f543a-09a5-4c29-ad0d-2a6d2f0e16bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657891074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1657891074
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.2325827540
Short name T172
Test name
Test status
Simulation time 2338939839 ps
CPU time 52.48 seconds
Started Aug 10 05:16:42 PM PDT 24
Finished Aug 10 05:17:35 PM PDT 24
Peak memory 198800 kb
Host smart-1e1c4885-56bd-49e4-b80c-4ec030a6a22c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325827540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.2325827540
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2130939964
Short name T708
Test name
Test status
Simulation time 14891355 ps
CPU time 0.58 seconds
Started Aug 10 05:15:05 PM PDT 24
Finished Aug 10 05:15:06 PM PDT 24
Peak memory 194684 kb
Host smart-9b383cdf-2fe4-4a47-a17b-a264d5ce505b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130939964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2130939964
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.932644047
Short name T148
Test name
Test status
Simulation time 23957251 ps
CPU time 0.79 seconds
Started Aug 10 05:15:06 PM PDT 24
Finished Aug 10 05:15:07 PM PDT 24
Peak memory 195900 kb
Host smart-9b98e55d-05db-43b6-8708-534f7a4ffb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932644047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.932644047
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1252829846
Short name T377
Test name
Test status
Simulation time 779231570 ps
CPU time 27.44 seconds
Started Aug 10 05:15:07 PM PDT 24
Finished Aug 10 05:15:35 PM PDT 24
Peak memory 198804 kb
Host smart-61ec57df-6e4b-495e-9d85-a4e98cf3706b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252829846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1252829846
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.1739104823
Short name T577
Test name
Test status
Simulation time 175257018 ps
CPU time 0.78 seconds
Started Aug 10 05:15:09 PM PDT 24
Finished Aug 10 05:15:10 PM PDT 24
Peak memory 195076 kb
Host smart-b9f9125b-10ae-4c1e-92e0-900af7e21af2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739104823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.1739104823
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.826413712
Short name T564
Test name
Test status
Simulation time 39338805 ps
CPU time 1.21 seconds
Started Aug 10 05:15:06 PM PDT 24
Finished Aug 10 05:15:07 PM PDT 24
Peak memory 196572 kb
Host smart-c0954913-d907-4dd9-88af-4b13251af165
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826413712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.826413712
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.870394160
Short name T591
Test name
Test status
Simulation time 88906024 ps
CPU time 3.45 seconds
Started Aug 10 05:15:09 PM PDT 24
Finished Aug 10 05:15:13 PM PDT 24
Peak memory 198632 kb
Host smart-611e1a39-3e49-4264-af04-a9ddf7ac57bc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870394160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.gpio_intr_with_filter_rand_intr_event.870394160
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.3862131215
Short name T519
Test name
Test status
Simulation time 291445813 ps
CPU time 2.62 seconds
Started Aug 10 05:15:08 PM PDT 24
Finished Aug 10 05:15:10 PM PDT 24
Peak memory 198648 kb
Host smart-6fbbe3c2-c7a4-4572-8a4c-8b0667dab8f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862131215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
3862131215
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.490123420
Short name T616
Test name
Test status
Simulation time 30445720 ps
CPU time 0.87 seconds
Started Aug 10 05:15:13 PM PDT 24
Finished Aug 10 05:15:14 PM PDT 24
Peak memory 197784 kb
Host smart-54fd1bfc-222c-4a47-b325-f43575bb60e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490123420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.490123420
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.363439062
Short name T71
Test name
Test status
Simulation time 99374227 ps
CPU time 1.21 seconds
Started Aug 10 05:15:07 PM PDT 24
Finished Aug 10 05:15:08 PM PDT 24
Peak memory 197884 kb
Host smart-61a11992-fed1-4e38-9a79-93cd119ec5f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363439062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.363439062
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.2018314017
Short name T507
Test name
Test status
Simulation time 547955468 ps
CPU time 2.63 seconds
Started Aug 10 05:15:06 PM PDT 24
Finished Aug 10 05:15:09 PM PDT 24
Peak memory 198596 kb
Host smart-5dfae008-d6ab-4439-b215-39c3ae61346c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018314017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.2018314017
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2005701575
Short name T51
Test name
Test status
Simulation time 145784884 ps
CPU time 0.81 seconds
Started Aug 10 05:15:08 PM PDT 24
Finished Aug 10 05:15:09 PM PDT 24
Peak memory 214324 kb
Host smart-7487b3e3-0dad-4bb3-b0fd-8eae53c9d0c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005701575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2005701575
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.349821390
Short name T328
Test name
Test status
Simulation time 276437960 ps
CPU time 1.09 seconds
Started Aug 10 05:15:10 PM PDT 24
Finished Aug 10 05:15:11 PM PDT 24
Peak memory 196316 kb
Host smart-df8dd470-bdfc-4fd5-a5c7-f2578512da45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349821390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.349821390
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.2494176915
Short name T195
Test name
Test status
Simulation time 173383551 ps
CPU time 1.21 seconds
Started Aug 10 05:15:08 PM PDT 24
Finished Aug 10 05:15:09 PM PDT 24
Peak memory 196008 kb
Host smart-6c65f880-92ec-44e1-a281-15c477c0c2a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494176915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.2494176915
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.432737027
Short name T542
Test name
Test status
Simulation time 56531194639 ps
CPU time 153.15 seconds
Started Aug 10 05:15:06 PM PDT 24
Finished Aug 10 05:17:39 PM PDT 24
Peak memory 198628 kb
Host smart-f37a7595-bb45-403e-bc3b-de30c4c3d972
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432737027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gp
io_stress_all.432737027
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.2857152887
Short name T567
Test name
Test status
Simulation time 175608122192 ps
CPU time 2104.04 seconds
Started Aug 10 05:15:11 PM PDT 24
Finished Aug 10 05:50:15 PM PDT 24
Peak memory 198828 kb
Host smart-adf71fa9-7a21-4d70-81e0-ceb112aade22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2857152887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.2857152887
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3049468295
Short name T389
Test name
Test status
Simulation time 19656017 ps
CPU time 0.59 seconds
Started Aug 10 05:16:39 PM PDT 24
Finished Aug 10 05:16:40 PM PDT 24
Peak memory 194532 kb
Host smart-ce7713e8-d583-4c8c-a7dc-d6ea9fcc07d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049468295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3049468295
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1600510163
Short name T264
Test name
Test status
Simulation time 68234680 ps
CPU time 0.68 seconds
Started Aug 10 05:16:30 PM PDT 24
Finished Aug 10 05:16:31 PM PDT 24
Peak memory 195312 kb
Host smart-1f58701e-103c-428d-9946-2977fb57567a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600510163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1600510163
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.3979115983
Short name T687
Test name
Test status
Simulation time 523405027 ps
CPU time 5.07 seconds
Started Aug 10 05:16:42 PM PDT 24
Finished Aug 10 05:16:47 PM PDT 24
Peak memory 196716 kb
Host smart-5900e7b8-5b7f-4841-bede-d72171b7f84b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979115983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.3979115983
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.1156328863
Short name T368
Test name
Test status
Simulation time 151084206 ps
CPU time 0.98 seconds
Started Aug 10 05:16:41 PM PDT 24
Finished Aug 10 05:16:42 PM PDT 24
Peak memory 198480 kb
Host smart-0750275d-6afe-480c-ab27-112e1c66f513
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156328863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.1156328863
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.687247985
Short name T189
Test name
Test status
Simulation time 202840222 ps
CPU time 0.97 seconds
Started Aug 10 05:16:30 PM PDT 24
Finished Aug 10 05:16:31 PM PDT 24
Peak memory 196656 kb
Host smart-7f4129f0-a363-4ab9-b4a0-0681b5bd3471
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687247985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.687247985
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.1742104585
Short name T257
Test name
Test status
Simulation time 106615519 ps
CPU time 1.25 seconds
Started Aug 10 05:16:29 PM PDT 24
Finished Aug 10 05:16:31 PM PDT 24
Peak memory 197436 kb
Host smart-05ad3e1d-ea7e-41f3-b7c2-4567b8712fd5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742104585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.1742104585
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.176098068
Short name T358
Test name
Test status
Simulation time 424445802 ps
CPU time 2.54 seconds
Started Aug 10 05:16:31 PM PDT 24
Finished Aug 10 05:16:34 PM PDT 24
Peak memory 197508 kb
Host smart-01169ef6-becd-434f-b980-dcac8f65e392
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176098068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.
176098068
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.3953036164
Short name T394
Test name
Test status
Simulation time 36621176 ps
CPU time 1.24 seconds
Started Aug 10 05:16:30 PM PDT 24
Finished Aug 10 05:16:31 PM PDT 24
Peak memory 197476 kb
Host smart-8e6c76c6-800b-47b6-baab-c0e7011fd32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953036164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.3953036164
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.1340478482
Short name T619
Test name
Test status
Simulation time 120935996 ps
CPU time 0.68 seconds
Started Aug 10 05:16:30 PM PDT 24
Finished Aug 10 05:16:31 PM PDT 24
Peak memory 194880 kb
Host smart-e2447fe5-5427-4a91-b57b-7212c5f647ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340478482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.1340478482
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2424694174
Short name T57
Test name
Test status
Simulation time 90527796 ps
CPU time 4.17 seconds
Started Aug 10 05:16:41 PM PDT 24
Finished Aug 10 05:16:45 PM PDT 24
Peak memory 198488 kb
Host smart-6beec5fd-67fa-44ec-b8d3-506db9c3bbb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424694174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2424694174
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2275499133
Short name T186
Test name
Test status
Simulation time 497029649 ps
CPU time 1.31 seconds
Started Aug 10 05:16:29 PM PDT 24
Finished Aug 10 05:16:31 PM PDT 24
Peak memory 196876 kb
Host smart-c27b47d3-c85c-42cb-b037-f49d6537e343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275499133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2275499133
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.1599061339
Short name T410
Test name
Test status
Simulation time 148900287 ps
CPU time 1.17 seconds
Started Aug 10 05:16:35 PM PDT 24
Finished Aug 10 05:16:36 PM PDT 24
Peak memory 196320 kb
Host smart-56c0658a-1707-4122-a78b-7ba5a30366c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599061339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.1599061339
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3787804199
Short name T484
Test name
Test status
Simulation time 6036011791 ps
CPU time 163.75 seconds
Started Aug 10 05:16:36 PM PDT 24
Finished Aug 10 05:19:20 PM PDT 24
Peak memory 198556 kb
Host smart-98254afe-e4aa-45ae-95e6-9b6a076682d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787804199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3787804199
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.2410300616
Short name T104
Test name
Test status
Simulation time 63709597575 ps
CPU time 303.83 seconds
Started Aug 10 05:16:42 PM PDT 24
Finished Aug 10 05:21:46 PM PDT 24
Peak memory 198832 kb
Host smart-affa1c01-8a4e-4f9d-936a-45aa23d5944e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2410300616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.2410300616
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.3579978889
Short name T488
Test name
Test status
Simulation time 12961709 ps
CPU time 0.61 seconds
Started Aug 10 05:16:39 PM PDT 24
Finished Aug 10 05:16:40 PM PDT 24
Peak memory 194652 kb
Host smart-19be7b10-8740-4fb5-9ea4-d1c6580572f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579978889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.3579978889
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.3395435385
Short name T402
Test name
Test status
Simulation time 107328468 ps
CPU time 0.74 seconds
Started Aug 10 05:16:41 PM PDT 24
Finished Aug 10 05:16:42 PM PDT 24
Peak memory 195876 kb
Host smart-fa30dc41-4540-4260-81db-b07d6cac0adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395435385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.3395435385
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.3327008302
Short name T247
Test name
Test status
Simulation time 806258191 ps
CPU time 8.66 seconds
Started Aug 10 05:16:34 PM PDT 24
Finished Aug 10 05:16:43 PM PDT 24
Peak memory 198448 kb
Host smart-5a6ac385-2db9-46db-8668-03629d798b01
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327008302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.3327008302
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.3322583547
Short name T437
Test name
Test status
Simulation time 417097860 ps
CPU time 1.12 seconds
Started Aug 10 05:16:40 PM PDT 24
Finished Aug 10 05:16:42 PM PDT 24
Peak memory 197232 kb
Host smart-4b0c9068-63e3-44c7-ad01-0f6ee2545195
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322583547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.3322583547
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.425603651
Short name T421
Test name
Test status
Simulation time 175708422 ps
CPU time 0.96 seconds
Started Aug 10 05:16:41 PM PDT 24
Finished Aug 10 05:16:42 PM PDT 24
Peak memory 196480 kb
Host smart-3d257e42-2195-4bc9-b62c-0c22ddd2bdd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425603651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.425603651
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.473786075
Short name T315
Test name
Test status
Simulation time 89823561 ps
CPU time 3.56 seconds
Started Aug 10 05:16:35 PM PDT 24
Finished Aug 10 05:16:39 PM PDT 24
Peak memory 198456 kb
Host smart-acb1c6a7-eac3-4e7d-8889-1b8c77eb260a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473786075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.gpio_intr_with_filter_rand_intr_event.473786075
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2007301147
Short name T322
Test name
Test status
Simulation time 1703110566 ps
CPU time 3.13 seconds
Started Aug 10 05:16:39 PM PDT 24
Finished Aug 10 05:16:42 PM PDT 24
Peak memory 197592 kb
Host smart-ee2b2ad7-4c62-46e9-b691-eea014d48148
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007301147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.2007301147
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.2269387081
Short name T626
Test name
Test status
Simulation time 62999520 ps
CPU time 0.69 seconds
Started Aug 10 05:16:36 PM PDT 24
Finished Aug 10 05:16:37 PM PDT 24
Peak memory 194880 kb
Host smart-ca3f981b-f520-40e6-9e58-dd31a977a250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269387081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.2269387081
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3308712758
Short name T583
Test name
Test status
Simulation time 33820976 ps
CPU time 1.19 seconds
Started Aug 10 05:16:35 PM PDT 24
Finished Aug 10 05:16:36 PM PDT 24
Peak memory 196420 kb
Host smart-a8f9cd6e-fb0b-4fb6-b92d-bea42e2820a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308712758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.3308712758
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.461864875
Short name T455
Test name
Test status
Simulation time 2538151287 ps
CPU time 3.17 seconds
Started Aug 10 05:16:38 PM PDT 24
Finished Aug 10 05:16:42 PM PDT 24
Peak memory 198684 kb
Host smart-623649e4-ab7d-4a52-9558-525f6c0dfa2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461864875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ran
dom_long_reg_writes_reg_reads.461864875
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.1546830585
Short name T303
Test name
Test status
Simulation time 42188048 ps
CPU time 0.92 seconds
Started Aug 10 05:16:40 PM PDT 24
Finished Aug 10 05:16:41 PM PDT 24
Peak memory 196992 kb
Host smart-42843bb7-7f49-4720-882a-1f062f303a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546830585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.1546830585
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.1504574074
Short name T286
Test name
Test status
Simulation time 84084772 ps
CPU time 1.09 seconds
Started Aug 10 05:16:41 PM PDT 24
Finished Aug 10 05:16:42 PM PDT 24
Peak memory 196848 kb
Host smart-8c7ad07a-5b6b-4f1e-a7b1-5c36e93c3afd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504574074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.1504574074
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.3190761985
Short name T681
Test name
Test status
Simulation time 19262421513 ps
CPU time 63.57 seconds
Started Aug 10 05:16:33 PM PDT 24
Finished Aug 10 05:17:37 PM PDT 24
Peak memory 198676 kb
Host smart-94b46f0f-f499-4e8f-b312-b9bd68eede11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190761985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.3190761985
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3827250608
Short name T412
Test name
Test status
Simulation time 40598178 ps
CPU time 0.59 seconds
Started Aug 10 05:16:42 PM PDT 24
Finished Aug 10 05:16:43 PM PDT 24
Peak memory 194396 kb
Host smart-51102a16-6381-4a9a-b7ad-21e3d67c71a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827250608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3827250608
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.2748289837
Short name T173
Test name
Test status
Simulation time 63512040 ps
CPU time 0.86 seconds
Started Aug 10 05:16:33 PM PDT 24
Finished Aug 10 05:16:34 PM PDT 24
Peak memory 195820 kb
Host smart-4c8d7474-5f77-493e-aebd-5e94be2ca100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748289837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.2748289837
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3778534996
Short name T560
Test name
Test status
Simulation time 537298489 ps
CPU time 11.05 seconds
Started Aug 10 05:16:36 PM PDT 24
Finished Aug 10 05:16:47 PM PDT 24
Peak memory 198528 kb
Host smart-5e675c50-41d7-4bee-82ea-dc1dd4b89a1c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778534996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3778534996
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.2879685929
Short name T392
Test name
Test status
Simulation time 88892259 ps
CPU time 1.02 seconds
Started Aug 10 05:16:34 PM PDT 24
Finished Aug 10 05:16:36 PM PDT 24
Peak memory 197088 kb
Host smart-0f1f6b91-989b-4765-a507-c6ab7a57d009
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879685929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.2879685929
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.4035868844
Short name T701
Test name
Test status
Simulation time 34563777 ps
CPU time 0.75 seconds
Started Aug 10 05:16:39 PM PDT 24
Finished Aug 10 05:16:40 PM PDT 24
Peak memory 196800 kb
Host smart-d2d536af-c0f2-481d-a7ae-1c960d2044cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035868844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.4035868844
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.4234750366
Short name T629
Test name
Test status
Simulation time 93153262 ps
CPU time 2.15 seconds
Started Aug 10 05:16:34 PM PDT 24
Finished Aug 10 05:16:36 PM PDT 24
Peak memory 196668 kb
Host smart-549098b8-d899-4de8-acb1-3d5d71c907eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234750366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.4234750366
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.1250029565
Short name T704
Test name
Test status
Simulation time 58452691 ps
CPU time 0.8 seconds
Started Aug 10 05:16:35 PM PDT 24
Finished Aug 10 05:16:36 PM PDT 24
Peak memory 195996 kb
Host smart-6c0c2756-94ad-4c40-9ad0-cbe84fb196ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250029565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.1250029565
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.3758398322
Short name T160
Test name
Test status
Simulation time 56735195 ps
CPU time 1.06 seconds
Started Aug 10 05:16:41 PM PDT 24
Finished Aug 10 05:16:43 PM PDT 24
Peak memory 196412 kb
Host smart-0aa86385-cf79-4868-8595-0d70e85e3610
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758398322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.3758398322
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2974001034
Short name T6
Test name
Test status
Simulation time 3345592274 ps
CPU time 4.36 seconds
Started Aug 10 05:16:35 PM PDT 24
Finished Aug 10 05:16:40 PM PDT 24
Peak memory 198692 kb
Host smart-bfa09f35-0b07-4021-a044-931afacc4035
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974001034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2974001034
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3415433759
Short name T144
Test name
Test status
Simulation time 513752712 ps
CPU time 1.23 seconds
Started Aug 10 05:16:34 PM PDT 24
Finished Aug 10 05:16:35 PM PDT 24
Peak memory 197076 kb
Host smart-775c8e69-4b74-4236-8209-c2e2bc659eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415433759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3415433759
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.681232121
Short name T514
Test name
Test status
Simulation time 44423557 ps
CPU time 1.27 seconds
Started Aug 10 05:16:33 PM PDT 24
Finished Aug 10 05:16:34 PM PDT 24
Peak memory 196300 kb
Host smart-07bd6a77-47cf-443f-9554-61fb66853178
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681232121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.681232121
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.589719276
Short name T636
Test name
Test status
Simulation time 6931677456 ps
CPU time 161.5 seconds
Started Aug 10 05:16:33 PM PDT 24
Finished Aug 10 05:19:14 PM PDT 24
Peak memory 198652 kb
Host smart-aa0e37f5-77bf-43c8-9851-f68d710ea7c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589719276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.g
pio_stress_all.589719276
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1372347005
Short name T496
Test name
Test status
Simulation time 51753720 ps
CPU time 0.58 seconds
Started Aug 10 05:16:41 PM PDT 24
Finished Aug 10 05:16:42 PM PDT 24
Peak memory 195184 kb
Host smart-f8b52679-a85c-42da-bb11-16b63ac7a81b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372347005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1372347005
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.3087867527
Short name T187
Test name
Test status
Simulation time 389959523 ps
CPU time 0.92 seconds
Started Aug 10 05:16:35 PM PDT 24
Finished Aug 10 05:16:36 PM PDT 24
Peak memory 196976 kb
Host smart-6cfb50c5-f6be-4f55-b90f-76abaeefa2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087867527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.3087867527
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1589109798
Short name T163
Test name
Test status
Simulation time 416826185 ps
CPU time 20.55 seconds
Started Aug 10 05:16:35 PM PDT 24
Finished Aug 10 05:16:56 PM PDT 24
Peak memory 198504 kb
Host smart-802a2d78-5a09-43cd-9424-302df1b2f7ba
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589109798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1589109798
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.787426563
Short name T381
Test name
Test status
Simulation time 312037835 ps
CPU time 1 seconds
Started Aug 10 05:16:39 PM PDT 24
Finished Aug 10 05:16:40 PM PDT 24
Peak memory 197200 kb
Host smart-7c4d089e-9ff4-4e8d-bd08-4bb579d71b87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787426563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.787426563
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.1190779427
Short name T420
Test name
Test status
Simulation time 42788913 ps
CPU time 0.97 seconds
Started Aug 10 05:16:36 PM PDT 24
Finished Aug 10 05:16:38 PM PDT 24
Peak memory 197208 kb
Host smart-52707538-6711-4271-a82a-fe504c3df354
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190779427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.1190779427
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.238663879
Short name T310
Test name
Test status
Simulation time 234750430 ps
CPU time 2.55 seconds
Started Aug 10 05:16:36 PM PDT 24
Finished Aug 10 05:16:38 PM PDT 24
Peak memory 198632 kb
Host smart-e4aa74cc-0c30-4907-afba-9d177d39eaa8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238663879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.gpio_intr_with_filter_rand_intr_event.238663879
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3568580395
Short name T650
Test name
Test status
Simulation time 260237428 ps
CPU time 3.94 seconds
Started Aug 10 05:16:49 PM PDT 24
Finished Aug 10 05:16:53 PM PDT 24
Peak memory 196252 kb
Host smart-686b6534-5a21-4939-88ee-cb6c8e914c8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568580395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3568580395
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2758472949
Short name T585
Test name
Test status
Simulation time 126251412 ps
CPU time 0.79 seconds
Started Aug 10 05:16:40 PM PDT 24
Finished Aug 10 05:16:41 PM PDT 24
Peak memory 195848 kb
Host smart-847d9c33-20d9-4911-8fa6-70a7bd6db635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758472949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2758472949
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3857064877
Short name T529
Test name
Test status
Simulation time 28126951 ps
CPU time 0.96 seconds
Started Aug 10 05:16:34 PM PDT 24
Finished Aug 10 05:16:35 PM PDT 24
Peak memory 197296 kb
Host smart-878baa23-7df7-47bd-8abb-1e4db020c342
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857064877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3857064877
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.148012954
Short name T20
Test name
Test status
Simulation time 283906963 ps
CPU time 3.66 seconds
Started Aug 10 05:16:40 PM PDT 24
Finished Aug 10 05:16:44 PM PDT 24
Peak memory 198548 kb
Host smart-8c895cc4-4e9b-4083-9500-64d32105ea82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148012954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ran
dom_long_reg_writes_reg_reads.148012954
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.1658286143
Short name T347
Test name
Test status
Simulation time 469149606 ps
CPU time 1.43 seconds
Started Aug 10 05:16:35 PM PDT 24
Finished Aug 10 05:16:37 PM PDT 24
Peak memory 197396 kb
Host smart-8ce7363a-2ccf-4005-8dbb-295a921dd0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658286143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.1658286143
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.2218364158
Short name T395
Test name
Test status
Simulation time 282511651 ps
CPU time 1.26 seconds
Started Aug 10 05:16:42 PM PDT 24
Finished Aug 10 05:16:44 PM PDT 24
Peak memory 196948 kb
Host smart-055ca0c4-aa11-47a8-bc4c-a7441fc7e9b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218364158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.2218364158
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.2317572985
Short name T109
Test name
Test status
Simulation time 29741607745 ps
CPU time 215.44 seconds
Started Aug 10 05:16:37 PM PDT 24
Finished Aug 10 05:20:13 PM PDT 24
Peak memory 198756 kb
Host smart-96f27b75-571d-4ea8-a9d8-aae51ce0e65f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317572985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.2317572985
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.985909213
Short name T657
Test name
Test status
Simulation time 34086146 ps
CPU time 0.61 seconds
Started Aug 10 05:16:46 PM PDT 24
Finished Aug 10 05:16:46 PM PDT 24
Peak memory 195212 kb
Host smart-e110d1fb-5acc-4c04-a6d8-68759da7de78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985909213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.985909213
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.602694101
Short name T573
Test name
Test status
Simulation time 32446950 ps
CPU time 0.78 seconds
Started Aug 10 05:16:38 PM PDT 24
Finished Aug 10 05:16:39 PM PDT 24
Peak memory 195780 kb
Host smart-8b688272-3c2c-4b01-b5ee-c31fbe49bf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602694101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.602694101
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.3487365302
Short name T262
Test name
Test status
Simulation time 333733972 ps
CPU time 8.32 seconds
Started Aug 10 05:16:51 PM PDT 24
Finished Aug 10 05:17:00 PM PDT 24
Peak memory 195968 kb
Host smart-3eed603e-5475-44a4-9e2d-02d3b128bbb7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487365302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.3487365302
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.1032732402
Short name T535
Test name
Test status
Simulation time 582609221 ps
CPU time 1.12 seconds
Started Aug 10 05:16:42 PM PDT 24
Finished Aug 10 05:16:44 PM PDT 24
Peak memory 198520 kb
Host smart-a4cad196-0042-4594-907d-1c913556c0b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032732402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.1032732402
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.976254003
Short name T153
Test name
Test status
Simulation time 109829025 ps
CPU time 1.01 seconds
Started Aug 10 05:16:41 PM PDT 24
Finished Aug 10 05:16:42 PM PDT 24
Peak memory 197248 kb
Host smart-0942982f-5f95-45b1-ab79-c62a70d751c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976254003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.976254003
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1509047953
Short name T156
Test name
Test status
Simulation time 157525967 ps
CPU time 3.19 seconds
Started Aug 10 05:16:43 PM PDT 24
Finished Aug 10 05:16:46 PM PDT 24
Peak memory 198748 kb
Host smart-9977b182-ce2c-457f-b496-c98f31d913a4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509047953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1509047953
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.4167205853
Short name T331
Test name
Test status
Simulation time 524372198 ps
CPU time 3.3 seconds
Started Aug 10 05:16:42 PM PDT 24
Finished Aug 10 05:16:46 PM PDT 24
Peak memory 197344 kb
Host smart-86d8eb7c-4d3e-4e34-a414-a9262f3b184b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167205853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.4167205853
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.1026813226
Short name T513
Test name
Test status
Simulation time 73406296 ps
CPU time 0.83 seconds
Started Aug 10 05:16:34 PM PDT 24
Finished Aug 10 05:16:35 PM PDT 24
Peak memory 196624 kb
Host smart-55893800-3271-49fc-a81b-a3c1ea49ab15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026813226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.1026813226
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3457958764
Short name T460
Test name
Test status
Simulation time 19783096 ps
CPU time 0.72 seconds
Started Aug 10 05:16:36 PM PDT 24
Finished Aug 10 05:16:37 PM PDT 24
Peak memory 195888 kb
Host smart-c17505a9-e3ef-450c-96e4-0f73b62f61e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457958764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3457958764
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.4093154533
Short name T343
Test name
Test status
Simulation time 117086837 ps
CPU time 5.56 seconds
Started Aug 10 05:16:42 PM PDT 24
Finished Aug 10 05:16:47 PM PDT 24
Peak memory 198564 kb
Host smart-6d06cead-6c11-4459-b95e-93cec23fd84d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093154533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.4093154533
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.841797449
Short name T439
Test name
Test status
Simulation time 192287465 ps
CPU time 1.27 seconds
Started Aug 10 05:16:36 PM PDT 24
Finished Aug 10 05:16:38 PM PDT 24
Peak memory 198460 kb
Host smart-2bb6e0b6-0ec7-46a3-a522-480da4e9d6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841797449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.841797449
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.2561477813
Short name T294
Test name
Test status
Simulation time 85667198 ps
CPU time 0.9 seconds
Started Aug 10 05:16:41 PM PDT 24
Finished Aug 10 05:16:43 PM PDT 24
Peak memory 195768 kb
Host smart-b6aa2cb0-b718-4784-8ec2-2a8c4683853a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561477813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.2561477813
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.2977082491
Short name T183
Test name
Test status
Simulation time 12458940306 ps
CPU time 44.1 seconds
Started Aug 10 05:16:41 PM PDT 24
Finished Aug 10 05:17:26 PM PDT 24
Peak memory 198552 kb
Host smart-150ccdf2-ecfb-4b84-83f5-81bad18c03b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977082491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.2977082491
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3169067037
Short name T677
Test name
Test status
Simulation time 12222915 ps
CPU time 0.59 seconds
Started Aug 10 05:16:47 PM PDT 24
Finished Aug 10 05:16:48 PM PDT 24
Peak memory 196048 kb
Host smart-1fa41464-d990-49ed-8737-e5010a956164
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169067037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3169067037
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.1781698227
Short name T438
Test name
Test status
Simulation time 38853218 ps
CPU time 0.85 seconds
Started Aug 10 05:16:42 PM PDT 24
Finished Aug 10 05:16:43 PM PDT 24
Peak memory 196620 kb
Host smart-d8f5a6d4-5be9-4e1c-8df9-28850d8583c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781698227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.1781698227
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2872609906
Short name T215
Test name
Test status
Simulation time 561728804 ps
CPU time 8.72 seconds
Started Aug 10 05:16:45 PM PDT 24
Finished Aug 10 05:16:54 PM PDT 24
Peak memory 198584 kb
Host smart-24d5260e-5a75-4714-bc3d-067d40034779
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872609906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2872609906
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1988457790
Short name T630
Test name
Test status
Simulation time 120450273 ps
CPU time 1.01 seconds
Started Aug 10 05:16:57 PM PDT 24
Finished Aug 10 05:16:58 PM PDT 24
Peak memory 198460 kb
Host smart-0c54049e-c2b3-4e3a-b8fc-39915fdc0b22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988457790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1988457790
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.2533741279
Short name T241
Test name
Test status
Simulation time 76467252 ps
CPU time 1.06 seconds
Started Aug 10 05:16:45 PM PDT 24
Finished Aug 10 05:16:47 PM PDT 24
Peak memory 196484 kb
Host smart-dbf09777-40bc-4e35-a5fe-3d6e21a038bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533741279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.2533741279
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1376578641
Short name T369
Test name
Test status
Simulation time 259468833 ps
CPU time 2.81 seconds
Started Aug 10 05:16:44 PM PDT 24
Finished Aug 10 05:16:47 PM PDT 24
Peak memory 198696 kb
Host smart-dea52dbe-68a3-448c-a055-e3c4284ac744
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376578641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1376578641
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.1501743071
Short name T210
Test name
Test status
Simulation time 120821574 ps
CPU time 3.28 seconds
Started Aug 10 05:16:46 PM PDT 24
Finished Aug 10 05:16:50 PM PDT 24
Peak memory 198636 kb
Host smart-695b8514-a117-46f1-8653-8ede8947bb64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501743071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.1501743071
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.192490030
Short name T427
Test name
Test status
Simulation time 27481065 ps
CPU time 1.02 seconds
Started Aug 10 05:16:50 PM PDT 24
Finished Aug 10 05:16:51 PM PDT 24
Peak memory 196444 kb
Host smart-8574ace8-df4a-4a39-a39c-628b962a303a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192490030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.192490030
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.1198499597
Short name T618
Test name
Test status
Simulation time 1037755872 ps
CPU time 1.17 seconds
Started Aug 10 05:16:44 PM PDT 24
Finished Aug 10 05:16:45 PM PDT 24
Peak memory 196524 kb
Host smart-a4a50f54-694e-48dd-a596-2715b8400f03
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198499597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.1198499597
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2397609384
Short name T119
Test name
Test status
Simulation time 392187885 ps
CPU time 4.62 seconds
Started Aug 10 05:16:41 PM PDT 24
Finished Aug 10 05:16:45 PM PDT 24
Peak memory 198560 kb
Host smart-7c2e1104-4dd3-46d4-ad39-b673a67e2a2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397609384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2397609384
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1769382074
Short name T521
Test name
Test status
Simulation time 36923754 ps
CPU time 1.17 seconds
Started Aug 10 05:16:41 PM PDT 24
Finished Aug 10 05:16:43 PM PDT 24
Peak memory 196868 kb
Host smart-2c219a5f-d4c3-478e-8b80-f6ebd8c301ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769382074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1769382074
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.3971389186
Short name T436
Test name
Test status
Simulation time 285615697 ps
CPU time 1.24 seconds
Started Aug 10 05:16:46 PM PDT 24
Finished Aug 10 05:16:48 PM PDT 24
Peak memory 198452 kb
Host smart-0f7a2f5d-efea-4e81-9216-5ef055f3eaf2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971389186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.3971389186
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.3960732122
Short name T525
Test name
Test status
Simulation time 5330457491 ps
CPU time 151.02 seconds
Started Aug 10 05:16:40 PM PDT 24
Finished Aug 10 05:19:11 PM PDT 24
Peak memory 198616 kb
Host smart-5700aed7-d86e-4abc-abb0-51e25463182b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960732122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.3960732122
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.1897888466
Short name T408
Test name
Test status
Simulation time 33574599 ps
CPU time 0.57 seconds
Started Aug 10 05:16:48 PM PDT 24
Finished Aug 10 05:16:48 PM PDT 24
Peak memory 194376 kb
Host smart-8f07f1b4-9d2f-4a2a-9a79-f0b5ad1ba7d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897888466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.1897888466
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.4045683585
Short name T212
Test name
Test status
Simulation time 31440898 ps
CPU time 0.83 seconds
Started Aug 10 05:16:46 PM PDT 24
Finished Aug 10 05:16:47 PM PDT 24
Peak memory 196604 kb
Host smart-9c78a2c1-c44d-4027-b722-3696276fccda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045683585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.4045683585
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.458770645
Short name T260
Test name
Test status
Simulation time 2592492681 ps
CPU time 15.51 seconds
Started Aug 10 05:16:40 PM PDT 24
Finished Aug 10 05:16:56 PM PDT 24
Peak memory 198796 kb
Host smart-17d0c418-eaaa-4b91-a6b4-6bf18884ed19
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458770645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stres
s.458770645
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.2975691273
Short name T506
Test name
Test status
Simulation time 123393220 ps
CPU time 1.01 seconds
Started Aug 10 05:16:44 PM PDT 24
Finished Aug 10 05:16:45 PM PDT 24
Peak memory 197608 kb
Host smart-7d444f80-7f9f-4b9b-983c-b5696ef5217a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975691273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2975691273
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.1908917018
Short name T207
Test name
Test status
Simulation time 97894924 ps
CPU time 0.69 seconds
Started Aug 10 05:16:43 PM PDT 24
Finished Aug 10 05:16:43 PM PDT 24
Peak memory 194112 kb
Host smart-dcfebae1-dfdd-4022-831b-f11bf62f1ab1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908917018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.1908917018
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.1002680358
Short name T117
Test name
Test status
Simulation time 56795309 ps
CPU time 2.29 seconds
Started Aug 10 05:16:44 PM PDT 24
Finished Aug 10 05:16:47 PM PDT 24
Peak memory 196844 kb
Host smart-00b486a2-b21d-47f1-94a2-acc472ead923
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002680358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.1002680358
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3311984160
Short name T473
Test name
Test status
Simulation time 348024641 ps
CPU time 2.16 seconds
Started Aug 10 05:16:45 PM PDT 24
Finished Aug 10 05:16:48 PM PDT 24
Peak memory 197164 kb
Host smart-22f3fcc6-290b-4baf-94a4-1d4becc85d4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311984160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3311984160
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.1055627361
Short name T490
Test name
Test status
Simulation time 49900757 ps
CPU time 0.66 seconds
Started Aug 10 05:16:46 PM PDT 24
Finished Aug 10 05:16:47 PM PDT 24
Peak memory 194688 kb
Host smart-acc945e5-9ed4-42ef-aed8-cfe8f7436aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055627361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.1055627361
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2077399142
Short name T244
Test name
Test status
Simulation time 369666556 ps
CPU time 1.32 seconds
Started Aug 10 05:16:47 PM PDT 24
Finished Aug 10 05:16:49 PM PDT 24
Peak memory 197000 kb
Host smart-af29653f-2561-4182-b5bb-882c2f0caa89
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077399142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2077399142
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.3213466291
Short name T563
Test name
Test status
Simulation time 1851105227 ps
CPU time 5.32 seconds
Started Aug 10 05:16:47 PM PDT 24
Finished Aug 10 05:16:52 PM PDT 24
Peak memory 198616 kb
Host smart-402f5de7-2445-4a90-a559-e0c0bc36eecc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213466291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.3213466291
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.1631945307
Short name T26
Test name
Test status
Simulation time 190664761 ps
CPU time 1.05 seconds
Started Aug 10 05:16:49 PM PDT 24
Finished Aug 10 05:16:50 PM PDT 24
Peak memory 196908 kb
Host smart-075c6e52-a1fe-4d6d-830c-843ec464155c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631945307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.1631945307
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1087270101
Short name T29
Test name
Test status
Simulation time 74730847 ps
CPU time 1.27 seconds
Started Aug 10 05:16:43 PM PDT 24
Finished Aug 10 05:16:44 PM PDT 24
Peak memory 197068 kb
Host smart-7cdf3ae8-75f3-4958-a64b-14644adb5bd5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087270101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1087270101
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.531789360
Short name T443
Test name
Test status
Simulation time 15074567329 ps
CPU time 28.9 seconds
Started Aug 10 05:16:45 PM PDT 24
Finished Aug 10 05:17:14 PM PDT 24
Peak memory 198712 kb
Host smart-1ec1ffe4-3a58-4d35-bd2d-98608502d82c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531789360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.g
pio_stress_all.531789360
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.1287826456
Short name T259
Test name
Test status
Simulation time 47964829 ps
CPU time 0.56 seconds
Started Aug 10 05:16:45 PM PDT 24
Finished Aug 10 05:16:46 PM PDT 24
Peak memory 195500 kb
Host smart-205d4007-4f1b-4aa8-9dab-1c7c4d7bb926
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287826456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1287826456
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.2496509762
Short name T387
Test name
Test status
Simulation time 23427752 ps
CPU time 0.78 seconds
Started Aug 10 05:16:50 PM PDT 24
Finished Aug 10 05:16:52 PM PDT 24
Peak memory 196444 kb
Host smart-889b4511-e9d1-4f08-a1b7-e3319ba9b657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496509762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.2496509762
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.1013364025
Short name T566
Test name
Test status
Simulation time 78784285 ps
CPU time 3.96 seconds
Started Aug 10 05:16:45 PM PDT 24
Finished Aug 10 05:16:49 PM PDT 24
Peak memory 195932 kb
Host smart-25e46700-d692-4273-8096-9a73fe1f7906
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013364025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.1013364025
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.3562079836
Short name T356
Test name
Test status
Simulation time 152476938 ps
CPU time 1.07 seconds
Started Aug 10 05:16:43 PM PDT 24
Finished Aug 10 05:16:44 PM PDT 24
Peak memory 197196 kb
Host smart-97d0ef06-cc45-4f2f-a4e1-3b9ac5f13eae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562079836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.3562079836
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1871388506
Short name T559
Test name
Test status
Simulation time 37298160 ps
CPU time 0.89 seconds
Started Aug 10 05:16:42 PM PDT 24
Finished Aug 10 05:16:43 PM PDT 24
Peak memory 196028 kb
Host smart-a45dd07a-833d-4bac-b8bc-eb7f8d066aec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871388506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1871388506
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.895961029
Short name T621
Test name
Test status
Simulation time 149465445 ps
CPU time 3.21 seconds
Started Aug 10 05:16:44 PM PDT 24
Finished Aug 10 05:16:47 PM PDT 24
Peak memory 198528 kb
Host smart-a74556d2-b7e9-4827-9e1d-f709a665ba1e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895961029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.895961029
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3800931565
Short name T291
Test name
Test status
Simulation time 107275344 ps
CPU time 0.95 seconds
Started Aug 10 05:16:45 PM PDT 24
Finished Aug 10 05:16:46 PM PDT 24
Peak memory 196092 kb
Host smart-a9be8fe6-5db4-4f89-9819-7509440bc208
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800931565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3800931565
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.1908015865
Short name T480
Test name
Test status
Simulation time 133715658 ps
CPU time 1.14 seconds
Started Aug 10 05:16:44 PM PDT 24
Finished Aug 10 05:16:45 PM PDT 24
Peak memory 197244 kb
Host smart-89602387-16d1-4f2f-a828-931cdcf4ad37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908015865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.1908015865
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1968549201
Short name T287
Test name
Test status
Simulation time 23045164 ps
CPU time 0.86 seconds
Started Aug 10 05:16:43 PM PDT 24
Finished Aug 10 05:16:44 PM PDT 24
Peak memory 197060 kb
Host smart-88b07c45-f75f-4021-ac30-1fa6770ed9a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968549201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1968549201
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.3997297863
Short name T494
Test name
Test status
Simulation time 46621847 ps
CPU time 1.66 seconds
Started Aug 10 05:16:44 PM PDT 24
Finished Aug 10 05:16:46 PM PDT 24
Peak memory 198480 kb
Host smart-5b6413c9-f858-44d2-8dab-314c5020e1ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997297863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.3997297863
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1439598784
Short name T609
Test name
Test status
Simulation time 71976415 ps
CPU time 1.4 seconds
Started Aug 10 05:16:44 PM PDT 24
Finished Aug 10 05:16:45 PM PDT 24
Peak memory 198536 kb
Host smart-2a490218-d4ed-4e76-a329-3dbe059b8032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439598784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1439598784
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2088843843
Short name T664
Test name
Test status
Simulation time 82637644 ps
CPU time 1.18 seconds
Started Aug 10 05:16:48 PM PDT 24
Finished Aug 10 05:16:49 PM PDT 24
Peak memory 196092 kb
Host smart-eae9128f-c17c-49ad-8961-37da15d24340
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088843843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.2088843843
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3647417447
Short name T130
Test name
Test status
Simulation time 13135632762 ps
CPU time 63.23 seconds
Started Aug 10 05:16:45 PM PDT 24
Finished Aug 10 05:17:48 PM PDT 24
Peak memory 198772 kb
Host smart-6a35cba9-0148-4c38-843f-3fed34ca11be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647417447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3647417447
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.1095360507
Short name T313
Test name
Test status
Simulation time 17264054 ps
CPU time 0.58 seconds
Started Aug 10 05:16:54 PM PDT 24
Finished Aug 10 05:16:55 PM PDT 24
Peak memory 194688 kb
Host smart-a8a58aa5-c8c0-402c-b158-0f85c904f4a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095360507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.1095360507
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.1920230829
Short name T578
Test name
Test status
Simulation time 73783815 ps
CPU time 0.99 seconds
Started Aug 10 05:16:50 PM PDT 24
Finished Aug 10 05:16:52 PM PDT 24
Peak memory 197164 kb
Host smart-2f5bbc7c-7e74-42cd-a384-c2a3ad62f116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920230829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.1920230829
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.184355483
Short name T198
Test name
Test status
Simulation time 153015062 ps
CPU time 5.82 seconds
Started Aug 10 05:16:50 PM PDT 24
Finished Aug 10 05:16:56 PM PDT 24
Peak memory 197784 kb
Host smart-a504bdbb-0b2b-4cb1-bfb5-065f2219ec61
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184355483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stres
s.184355483
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.1031979205
Short name T593
Test name
Test status
Simulation time 90304519 ps
CPU time 0.79 seconds
Started Aug 10 05:17:01 PM PDT 24
Finished Aug 10 05:17:02 PM PDT 24
Peak memory 196360 kb
Host smart-487b2e96-f561-433f-8dd1-f016834d924b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031979205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.1031979205
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.343430071
Short name T539
Test name
Test status
Simulation time 59979458 ps
CPU time 0.95 seconds
Started Aug 10 05:16:45 PM PDT 24
Finished Aug 10 05:16:46 PM PDT 24
Peak memory 196664 kb
Host smart-706f103a-2b38-4791-80f3-e4500722cf62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343430071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.343430071
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.1451783109
Short name T108
Test name
Test status
Simulation time 64776952 ps
CPU time 1 seconds
Started Aug 10 05:16:46 PM PDT 24
Finished Aug 10 05:16:48 PM PDT 24
Peak memory 196708 kb
Host smart-6497292d-dd08-422b-9927-c0bf634c19e4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451783109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.1451783109
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.191645751
Short name T575
Test name
Test status
Simulation time 69630780 ps
CPU time 1.06 seconds
Started Aug 10 05:16:48 PM PDT 24
Finished Aug 10 05:16:49 PM PDT 24
Peak memory 195892 kb
Host smart-1219cd57-b701-4db5-87b4-83803046030a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191645751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger.
191645751
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1326921068
Short name T544
Test name
Test status
Simulation time 88496116 ps
CPU time 0.99 seconds
Started Aug 10 05:16:51 PM PDT 24
Finished Aug 10 05:16:52 PM PDT 24
Peak memory 196488 kb
Host smart-c3857b2e-a153-4723-9144-c15bd251b8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326921068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1326921068
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.1553368545
Short name T129
Test name
Test status
Simulation time 49004862 ps
CPU time 1.11 seconds
Started Aug 10 05:16:49 PM PDT 24
Finished Aug 10 05:16:50 PM PDT 24
Peak memory 196432 kb
Host smart-52729c8a-e6f4-4489-be8d-04c142da6112
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553368545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.1553368545
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3945800952
Short name T214
Test name
Test status
Simulation time 485959094 ps
CPU time 4.15 seconds
Started Aug 10 05:16:58 PM PDT 24
Finished Aug 10 05:17:02 PM PDT 24
Peak memory 198432 kb
Host smart-771243e6-f59d-4984-9f19-ef24ee7eb242
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945800952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.3945800952
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.4106307563
Short name T679
Test name
Test status
Simulation time 96550865 ps
CPU time 0.84 seconds
Started Aug 10 05:16:44 PM PDT 24
Finished Aug 10 05:16:45 PM PDT 24
Peak memory 195804 kb
Host smart-693e5371-4e78-41e5-856d-c8cb4d7326e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106307563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.4106307563
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.877524231
Short name T671
Test name
Test status
Simulation time 314697036 ps
CPU time 1.52 seconds
Started Aug 10 05:16:43 PM PDT 24
Finished Aug 10 05:16:44 PM PDT 24
Peak memory 197936 kb
Host smart-4a7bd70a-47e5-47c0-bbea-eaae738a111a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877524231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.877524231
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.1591650546
Short name T492
Test name
Test status
Simulation time 1431439292 ps
CPU time 36.09 seconds
Started Aug 10 05:16:51 PM PDT 24
Finished Aug 10 05:17:27 PM PDT 24
Peak memory 198584 kb
Host smart-48bce0e6-1636-4f30-8de3-c65a59bf9f3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591650546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.1591650546
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.4090355741
Short name T405
Test name
Test status
Simulation time 29617716 ps
CPU time 0.64 seconds
Started Aug 10 05:16:58 PM PDT 24
Finished Aug 10 05:16:59 PM PDT 24
Peak memory 194732 kb
Host smart-9419a9bc-0cee-41cc-990a-72058dfa1ba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090355741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.4090355741
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.608740984
Short name T165
Test name
Test status
Simulation time 56426544 ps
CPU time 0.86 seconds
Started Aug 10 05:16:55 PM PDT 24
Finished Aug 10 05:16:56 PM PDT 24
Peak memory 197136 kb
Host smart-ec897c27-6c98-4dab-b508-c4298e8fae86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608740984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.608740984
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.3495055740
Short name T706
Test name
Test status
Simulation time 301917449 ps
CPU time 15.61 seconds
Started Aug 10 05:16:57 PM PDT 24
Finished Aug 10 05:17:13 PM PDT 24
Peak memory 197548 kb
Host smart-021157ed-7a1c-4082-aab8-b7e218b7415a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495055740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.3495055740
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2430788707
Short name T110
Test name
Test status
Simulation time 52785180 ps
CPU time 0.83 seconds
Started Aug 10 05:16:54 PM PDT 24
Finished Aug 10 05:16:55 PM PDT 24
Peak memory 196360 kb
Host smart-04ee1835-4d98-4846-8c73-fe17ec552cab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430788707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2430788707
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.145816165
Short name T512
Test name
Test status
Simulation time 33893720 ps
CPU time 1.02 seconds
Started Aug 10 05:16:58 PM PDT 24
Finished Aug 10 05:16:59 PM PDT 24
Peak memory 196268 kb
Host smart-a47b9588-e927-497f-bf0d-83a4e5a74bd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145816165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.145816165
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.3223019676
Short name T441
Test name
Test status
Simulation time 61525834 ps
CPU time 2.6 seconds
Started Aug 10 05:16:54 PM PDT 24
Finished Aug 10 05:16:57 PM PDT 24
Peak memory 198724 kb
Host smart-08a207f1-d287-44da-9a0a-75021fb89df9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223019676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.3223019676
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.593747552
Short name T419
Test name
Test status
Simulation time 210273979 ps
CPU time 1.76 seconds
Started Aug 10 05:16:50 PM PDT 24
Finished Aug 10 05:16:53 PM PDT 24
Peak memory 196444 kb
Host smart-c6f18b43-0310-46a4-acc3-0efe83b909ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593747552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.
593747552
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1521058764
Short name T444
Test name
Test status
Simulation time 40620526 ps
CPU time 0.73 seconds
Started Aug 10 05:16:54 PM PDT 24
Finished Aug 10 05:16:55 PM PDT 24
Peak memory 194720 kb
Host smart-32bb9b79-cf95-4de0-b769-40ac98b7635f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521058764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1521058764
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.2222375447
Short name T70
Test name
Test status
Simulation time 209916392 ps
CPU time 0.92 seconds
Started Aug 10 05:17:00 PM PDT 24
Finished Aug 10 05:17:01 PM PDT 24
Peak memory 196448 kb
Host smart-e24783aa-831e-4d4a-9021-d939c16420fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222375447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.2222375447
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.3286666860
Short name T606
Test name
Test status
Simulation time 95271411 ps
CPU time 2.39 seconds
Started Aug 10 05:16:50 PM PDT 24
Finished Aug 10 05:16:53 PM PDT 24
Peak memory 198588 kb
Host smart-55652031-fcc9-4e99-9066-cb004d518a1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286666860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.3286666860
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.104984353
Short name T696
Test name
Test status
Simulation time 34254034 ps
CPU time 0.94 seconds
Started Aug 10 05:16:52 PM PDT 24
Finished Aug 10 05:16:53 PM PDT 24
Peak memory 195796 kb
Host smart-12db5326-eb0f-4db0-8e0f-3933b51def69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104984353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.104984353
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.631800687
Short name T694
Test name
Test status
Simulation time 261106080 ps
CPU time 1.39 seconds
Started Aug 10 05:16:53 PM PDT 24
Finished Aug 10 05:16:54 PM PDT 24
Peak memory 198400 kb
Host smart-ba607826-f0f9-4eab-b2c8-ff8387b664e6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631800687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.631800687
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.1133603298
Short name T598
Test name
Test status
Simulation time 2637316748 ps
CPU time 63.45 seconds
Started Aug 10 05:16:56 PM PDT 24
Finished Aug 10 05:18:00 PM PDT 24
Peak memory 198748 kb
Host smart-c450567b-e072-4b89-a1d9-7ea1b31f8853
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133603298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.1133603298
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.756712876
Short name T250
Test name
Test status
Simulation time 12555150 ps
CPU time 0.58 seconds
Started Aug 10 05:15:15 PM PDT 24
Finished Aug 10 05:15:16 PM PDT 24
Peak memory 194420 kb
Host smart-499cb71d-a357-4b0b-b74e-af340ce1d734
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756712876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.756712876
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.1331225819
Short name T595
Test name
Test status
Simulation time 17345106 ps
CPU time 0.69 seconds
Started Aug 10 05:15:14 PM PDT 24
Finished Aug 10 05:15:15 PM PDT 24
Peak memory 195224 kb
Host smart-0a28106f-e561-4537-9c42-53d1b6d0c3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331225819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.1331225819
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.1203028199
Short name T56
Test name
Test status
Simulation time 395728843 ps
CPU time 5.01 seconds
Started Aug 10 05:15:13 PM PDT 24
Finished Aug 10 05:15:18 PM PDT 24
Peak memory 195964 kb
Host smart-b3ab8e85-9be5-46b2-9c40-5e235d424438
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203028199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.1203028199
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3807257812
Short name T610
Test name
Test status
Simulation time 46249760 ps
CPU time 0.68 seconds
Started Aug 10 05:15:18 PM PDT 24
Finished Aug 10 05:15:19 PM PDT 24
Peak memory 195192 kb
Host smart-0da9c556-0a60-48e9-9f39-e1c54c2165a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807257812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3807257812
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.305419309
Short name T170
Test name
Test status
Simulation time 138651694 ps
CPU time 1.21 seconds
Started Aug 10 05:15:14 PM PDT 24
Finished Aug 10 05:15:15 PM PDT 24
Peak memory 196320 kb
Host smart-e5f20621-2f90-480d-b44f-b98fa0044d8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305419309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.305419309
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.348186099
Short name T540
Test name
Test status
Simulation time 176571592 ps
CPU time 2.02 seconds
Started Aug 10 05:15:15 PM PDT 24
Finished Aug 10 05:15:17 PM PDT 24
Peak memory 198456 kb
Host smart-cb6a5e01-811b-47b8-99ba-a6fbaa9c648b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348186099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.gpio_intr_with_filter_rand_intr_event.348186099
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.4241466543
Short name T447
Test name
Test status
Simulation time 441129500 ps
CPU time 3.28 seconds
Started Aug 10 05:15:13 PM PDT 24
Finished Aug 10 05:15:16 PM PDT 24
Peak memory 197564 kb
Host smart-9dc7a0bd-c287-4fbe-8bf1-5eff09f003d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241466543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
4241466543
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1102035711
Short name T646
Test name
Test status
Simulation time 164012070 ps
CPU time 0.75 seconds
Started Aug 10 05:15:06 PM PDT 24
Finished Aug 10 05:15:07 PM PDT 24
Peak memory 195920 kb
Host smart-0ed4cb62-04ff-416d-b0b8-596465a10578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102035711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1102035711
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.770592169
Short name T651
Test name
Test status
Simulation time 132009054 ps
CPU time 0.95 seconds
Started Aug 10 05:15:15 PM PDT 24
Finished Aug 10 05:15:17 PM PDT 24
Peak memory 197176 kb
Host smart-df0c6595-c691-469a-ae8f-9c5db44a6e21
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770592169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup_
pulldown.770592169
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.1208927049
Short name T568
Test name
Test status
Simulation time 394483388 ps
CPU time 5.53 seconds
Started Aug 10 05:15:14 PM PDT 24
Finished Aug 10 05:15:20 PM PDT 24
Peak memory 198772 kb
Host smart-4fc80015-2d48-4aab-b302-1ddea5868258
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208927049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.1208927049
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1963670006
Short name T390
Test name
Test status
Simulation time 36976154 ps
CPU time 0.88 seconds
Started Aug 10 05:15:07 PM PDT 24
Finished Aug 10 05:15:08 PM PDT 24
Peak memory 195748 kb
Host smart-3a36d90b-7510-41c6-ba4c-c62d295bf875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963670006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1963670006
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3575401764
Short name T30
Test name
Test status
Simulation time 235843655 ps
CPU time 1.26 seconds
Started Aug 10 05:15:06 PM PDT 24
Finished Aug 10 05:15:08 PM PDT 24
Peak memory 197416 kb
Host smart-b0d30c48-efc3-43be-8f8f-93157b85db33
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575401764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3575401764
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1916285935
Short name T423
Test name
Test status
Simulation time 13572745744 ps
CPU time 99.76 seconds
Started Aug 10 05:15:14 PM PDT 24
Finished Aug 10 05:16:54 PM PDT 24
Peak memory 198792 kb
Host smart-e6f412eb-6f98-442a-a5dd-702a3a58307b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916285935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1916285935
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.111733202
Short name T236
Test name
Test status
Simulation time 53020759 ps
CPU time 0.6 seconds
Started Aug 10 05:15:15 PM PDT 24
Finished Aug 10 05:15:16 PM PDT 24
Peak memory 194728 kb
Host smart-41d08645-3dad-46e5-b6a0-a4aee6115f72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111733202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.111733202
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.1665812225
Short name T446
Test name
Test status
Simulation time 54883748 ps
CPU time 0.77 seconds
Started Aug 10 05:15:15 PM PDT 24
Finished Aug 10 05:15:16 PM PDT 24
Peak memory 195948 kb
Host smart-b54bca49-1dc2-47fd-aab5-753e99458e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665812225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.1665812225
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.3425616275
Short name T453
Test name
Test status
Simulation time 579070307 ps
CPU time 19.02 seconds
Started Aug 10 05:15:18 PM PDT 24
Finished Aug 10 05:15:37 PM PDT 24
Peak memory 197244 kb
Host smart-e8a671f5-bcb3-4ed2-9a58-2bb48f84a35a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425616275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.3425616275
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.641206426
Short name T422
Test name
Test status
Simulation time 336648158 ps
CPU time 0.69 seconds
Started Aug 10 05:15:15 PM PDT 24
Finished Aug 10 05:15:16 PM PDT 24
Peak memory 195308 kb
Host smart-fea1091e-1d57-45d8-8aba-d50d3efa0af2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641206426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.641206426
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.1638328081
Short name T675
Test name
Test status
Simulation time 141037353 ps
CPU time 1.22 seconds
Started Aug 10 05:15:14 PM PDT 24
Finished Aug 10 05:15:15 PM PDT 24
Peak memory 196676 kb
Host smart-cd17043f-49d6-413b-a344-6bb5e0e3b853
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638328081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.1638328081
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.1224160012
Short name T597
Test name
Test status
Simulation time 229033667 ps
CPU time 2.32 seconds
Started Aug 10 05:15:14 PM PDT 24
Finished Aug 10 05:15:17 PM PDT 24
Peak memory 198620 kb
Host smart-03076d35-9624-4290-bca8-101343e82dad
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224160012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.1224160012
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1844082277
Short name T656
Test name
Test status
Simulation time 112064156 ps
CPU time 2.16 seconds
Started Aug 10 05:15:15 PM PDT 24
Finished Aug 10 05:15:18 PM PDT 24
Peak memory 196688 kb
Host smart-2bb5ac2e-ec54-41f5-a54c-ab25ad023fe2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844082277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1844082277
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.2912925943
Short name T325
Test name
Test status
Simulation time 51291437 ps
CPU time 1.05 seconds
Started Aug 10 05:15:12 PM PDT 24
Finished Aug 10 05:15:13 PM PDT 24
Peak memory 196504 kb
Host smart-5a716fbf-ab4d-4cc1-91d0-d19b9e72263f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912925943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.2912925943
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.374131063
Short name T281
Test name
Test status
Simulation time 89429416 ps
CPU time 0.99 seconds
Started Aug 10 05:15:13 PM PDT 24
Finished Aug 10 05:15:15 PM PDT 24
Peak memory 196628 kb
Host smart-5bb9c695-9fa4-4dcc-9814-3acd9b2b5208
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374131063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.374131063
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.3557943717
Short name T311
Test name
Test status
Simulation time 378726223 ps
CPU time 6.02 seconds
Started Aug 10 05:15:12 PM PDT 24
Finished Aug 10 05:15:18 PM PDT 24
Peak memory 198480 kb
Host smart-fcf66180-f5d7-470c-8ec9-6ccb5c71e97f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557943717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.3557943717
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.1486398447
Short name T25
Test name
Test status
Simulation time 1522511397 ps
CPU time 1.31 seconds
Started Aug 10 05:15:13 PM PDT 24
Finished Aug 10 05:15:15 PM PDT 24
Peak memory 197284 kb
Host smart-4f57b0ed-d87f-469f-89cc-1fc7f7726cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486398447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1486398447
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.967026746
Short name T574
Test name
Test status
Simulation time 85452930 ps
CPU time 1.33 seconds
Started Aug 10 05:15:15 PM PDT 24
Finished Aug 10 05:15:17 PM PDT 24
Peak memory 196288 kb
Host smart-1a267e16-bc89-42c6-b3b9-c7a44d4ea6bd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967026746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.967026746
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3123444042
Short name T222
Test name
Test status
Simulation time 108910839250 ps
CPU time 172.19 seconds
Started Aug 10 05:15:15 PM PDT 24
Finished Aug 10 05:18:08 PM PDT 24
Peak memory 198696 kb
Host smart-9b07cbbd-9850-4381-b172-4d0e2486e596
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123444042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3123444042
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.1745282405
Short name T602
Test name
Test status
Simulation time 14514446 ps
CPU time 0.66 seconds
Started Aug 10 05:15:18 PM PDT 24
Finished Aug 10 05:15:19 PM PDT 24
Peak memory 195352 kb
Host smart-7e22e95b-287a-4db0-b006-a1ab9a8ae9ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745282405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.1745282405
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.1595933658
Short name T382
Test name
Test status
Simulation time 44567901 ps
CPU time 0.87 seconds
Started Aug 10 05:15:15 PM PDT 24
Finished Aug 10 05:15:15 PM PDT 24
Peak memory 197784 kb
Host smart-45ccb3ed-83d9-4647-b37b-acbeb05a9b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595933658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.1595933658
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2731377120
Short name T194
Test name
Test status
Simulation time 111239348 ps
CPU time 3.7 seconds
Started Aug 10 05:15:15 PM PDT 24
Finished Aug 10 05:15:19 PM PDT 24
Peak memory 196732 kb
Host smart-98b29e5f-4b87-4098-a701-4658e332a2ff
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731377120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2731377120
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.3403038809
Short name T232
Test name
Test status
Simulation time 698852903 ps
CPU time 0.82 seconds
Started Aug 10 05:15:15 PM PDT 24
Finished Aug 10 05:15:15 PM PDT 24
Peak memory 196592 kb
Host smart-b4c24cd5-3dea-400f-bec4-6013e8f67737
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403038809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.3403038809
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.1851633767
Short name T339
Test name
Test status
Simulation time 28701371 ps
CPU time 0.73 seconds
Started Aug 10 05:15:14 PM PDT 24
Finished Aug 10 05:15:15 PM PDT 24
Peak memory 194900 kb
Host smart-b9f2af60-93bc-4455-aa9f-20c79a211838
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851633767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.1851633767
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3319248111
Short name T448
Test name
Test status
Simulation time 94896406 ps
CPU time 1.96 seconds
Started Aug 10 05:15:14 PM PDT 24
Finished Aug 10 05:15:16 PM PDT 24
Peak memory 198768 kb
Host smart-c462518b-cb9c-41f5-bfb7-13e3805c9ccc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319248111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3319248111
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.130902750
Short name T234
Test name
Test status
Simulation time 85435239 ps
CPU time 1.24 seconds
Started Aug 10 05:15:13 PM PDT 24
Finished Aug 10 05:15:14 PM PDT 24
Peak memory 196984 kb
Host smart-2161e963-2326-49c0-86cf-789d99646069
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130902750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.130902750
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.2383745639
Short name T327
Test name
Test status
Simulation time 95181420 ps
CPU time 1.1 seconds
Started Aug 10 05:15:12 PM PDT 24
Finished Aug 10 05:15:14 PM PDT 24
Peak memory 197416 kb
Host smart-9600b828-8161-4061-b11b-0bfc9a9916e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383745639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.2383745639
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.1089946048
Short name T615
Test name
Test status
Simulation time 326656514 ps
CPU time 0.96 seconds
Started Aug 10 05:15:14 PM PDT 24
Finished Aug 10 05:15:15 PM PDT 24
Peak memory 197088 kb
Host smart-6f1bcd6b-26a5-4860-ad99-159049268581
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089946048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.1089946048
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.2879553012
Short name T576
Test name
Test status
Simulation time 340520057 ps
CPU time 3.88 seconds
Started Aug 10 05:15:15 PM PDT 24
Finished Aug 10 05:15:19 PM PDT 24
Peak memory 198540 kb
Host smart-146f4f22-d9b6-4c32-a5ce-87c6a0d2334b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879553012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.2879553012
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.2410977194
Short name T58
Test name
Test status
Simulation time 60826614 ps
CPU time 1.43 seconds
Started Aug 10 05:15:18 PM PDT 24
Finished Aug 10 05:15:20 PM PDT 24
Peak memory 196988 kb
Host smart-e598e21b-737a-46b0-92e3-929e68eeb071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410977194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.2410977194
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.307005985
Short name T648
Test name
Test status
Simulation time 101913731 ps
CPU time 0.94 seconds
Started Aug 10 05:15:13 PM PDT 24
Finished Aug 10 05:15:15 PM PDT 24
Peak memory 196860 kb
Host smart-dfb46606-d16a-4922-9cc1-b9e6c2ddd872
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307005985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.307005985
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.1691372563
Short name T27
Test name
Test status
Simulation time 16443214945 ps
CPU time 113.12 seconds
Started Aug 10 05:15:17 PM PDT 24
Finished Aug 10 05:17:10 PM PDT 24
Peak memory 198684 kb
Host smart-30ce4475-56ec-41f2-b724-59351dc4dfb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691372563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.1691372563
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.262646559
Short name T192
Test name
Test status
Simulation time 61099171 ps
CPU time 0.56 seconds
Started Aug 10 05:15:22 PM PDT 24
Finished Aug 10 05:15:23 PM PDT 24
Peak memory 195088 kb
Host smart-1a5fd272-d93a-407e-a398-6993b8197e4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262646559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.262646559
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.2101187242
Short name T282
Test name
Test status
Simulation time 26152904 ps
CPU time 0.84 seconds
Started Aug 10 05:15:26 PM PDT 24
Finished Aug 10 05:15:27 PM PDT 24
Peak memory 195744 kb
Host smart-fa4c6cb9-a221-427b-8584-acddc70c8f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101187242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.2101187242
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.3837992695
Short name T176
Test name
Test status
Simulation time 4658068289 ps
CPU time 8.33 seconds
Started Aug 10 05:15:25 PM PDT 24
Finished Aug 10 05:15:33 PM PDT 24
Peak memory 197648 kb
Host smart-59612d1c-9695-4234-8ac9-41100ce25e50
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837992695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.3837992695
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.3165486371
Short name T159
Test name
Test status
Simulation time 197702679 ps
CPU time 0.83 seconds
Started Aug 10 05:15:23 PM PDT 24
Finished Aug 10 05:15:24 PM PDT 24
Peak memory 196552 kb
Host smart-4b763c20-0c7d-4521-b998-8631439c2692
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165486371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.3165486371
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.799059261
Short name T363
Test name
Test status
Simulation time 53879100 ps
CPU time 0.98 seconds
Started Aug 10 05:15:22 PM PDT 24
Finished Aug 10 05:15:23 PM PDT 24
Peak memory 197416 kb
Host smart-180e5aab-7226-4b30-b56d-44e737ea2952
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799059261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.799059261
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.4148388145
Short name T275
Test name
Test status
Simulation time 139792509 ps
CPU time 1.57 seconds
Started Aug 10 05:15:23 PM PDT 24
Finished Aug 10 05:15:25 PM PDT 24
Peak memory 196812 kb
Host smart-fe48975b-8fcc-47d2-8d07-51eb61292627
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148388145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.4148388145
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.1655236170
Short name T647
Test name
Test status
Simulation time 73926883 ps
CPU time 1.99 seconds
Started Aug 10 05:15:20 PM PDT 24
Finished Aug 10 05:15:22 PM PDT 24
Peak memory 196400 kb
Host smart-a44272d6-9e39-4326-89fc-2e816115d757
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655236170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
1655236170
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3048576977
Short name T592
Test name
Test status
Simulation time 37957624 ps
CPU time 0.71 seconds
Started Aug 10 05:15:26 PM PDT 24
Finished Aug 10 05:15:26 PM PDT 24
Peak memory 194984 kb
Host smart-6ab0744f-f64f-4176-9083-770923abd844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048576977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3048576977
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.298166192
Short name T639
Test name
Test status
Simulation time 276006990 ps
CPU time 1.31 seconds
Started Aug 10 05:15:25 PM PDT 24
Finished Aug 10 05:15:26 PM PDT 24
Peak memory 197636 kb
Host smart-678f5b37-f1e3-40c2-8f4d-2473c904c324
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298166192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup_
pulldown.298166192
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.2872353715
Short name T364
Test name
Test status
Simulation time 358319835 ps
CPU time 5.6 seconds
Started Aug 10 05:15:27 PM PDT 24
Finished Aug 10 05:15:33 PM PDT 24
Peak memory 198528 kb
Host smart-fdcbdfc5-6879-4c61-8177-12b11f5339ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872353715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.2872353715
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.2318863067
Short name T424
Test name
Test status
Simulation time 140867856 ps
CPU time 1.09 seconds
Started Aug 10 05:15:15 PM PDT 24
Finished Aug 10 05:15:17 PM PDT 24
Peak memory 196156 kb
Host smart-92baba26-3a72-45f0-af9d-7a44a443e423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318863067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.2318863067
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.1889849350
Short name T191
Test name
Test status
Simulation time 69438052 ps
CPU time 0.89 seconds
Started Aug 10 05:15:14 PM PDT 24
Finished Aug 10 05:15:15 PM PDT 24
Peak memory 196956 kb
Host smart-b909d819-bb17-490f-b656-fde33b339e14
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889849350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.1889849350
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.601587811
Short name T288
Test name
Test status
Simulation time 76741643304 ps
CPU time 126.94 seconds
Started Aug 10 05:15:27 PM PDT 24
Finished Aug 10 05:17:34 PM PDT 24
Peak memory 198708 kb
Host smart-5da7606a-35ba-4eaf-a759-e8c143cc2975
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601587811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gp
io_stress_all.601587811
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.2399995574
Short name T508
Test name
Test status
Simulation time 89026435681 ps
CPU time 2005.6 seconds
Started Aug 10 05:15:24 PM PDT 24
Finished Aug 10 05:48:50 PM PDT 24
Peak memory 198876 kb
Host smart-e6478c09-8e46-45ae-a219-ba5b7583d3a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2399995574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.2399995574
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.4145674012
Short name T365
Test name
Test status
Simulation time 13743737 ps
CPU time 0.59 seconds
Started Aug 10 05:15:27 PM PDT 24
Finished Aug 10 05:15:27 PM PDT 24
Peak memory 194672 kb
Host smart-a0ca3392-e232-473c-adb5-529e69940aed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145674012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.4145674012
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.3612363507
Short name T337
Test name
Test status
Simulation time 34907582 ps
CPU time 0.77 seconds
Started Aug 10 05:15:23 PM PDT 24
Finished Aug 10 05:15:24 PM PDT 24
Peak memory 195672 kb
Host smart-83c206e2-78f5-43aa-b3f6-8a139904a0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612363507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.3612363507
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.571741956
Short name T384
Test name
Test status
Simulation time 496284355 ps
CPU time 25.48 seconds
Started Aug 10 05:15:25 PM PDT 24
Finished Aug 10 05:15:51 PM PDT 24
Peak memory 197544 kb
Host smart-5ed85c4b-cf69-458f-99ed-b4b9a494ac46
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571741956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stress
.571741956
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.3990844524
Short name T174
Test name
Test status
Simulation time 169976978 ps
CPU time 0.96 seconds
Started Aug 10 05:15:25 PM PDT 24
Finished Aug 10 05:15:26 PM PDT 24
Peak memory 197048 kb
Host smart-b0801549-e595-461c-b703-406f4fa52442
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990844524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.3990844524
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.200608379
Short name T131
Test name
Test status
Simulation time 433079282 ps
CPU time 1.21 seconds
Started Aug 10 05:15:26 PM PDT 24
Finished Aug 10 05:15:27 PM PDT 24
Peak memory 196628 kb
Host smart-fea785b1-1afb-4e37-8180-f907f4b585c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200608379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.200608379
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.2407317524
Short name T326
Test name
Test status
Simulation time 59378725 ps
CPU time 2.47 seconds
Started Aug 10 05:15:23 PM PDT 24
Finished Aug 10 05:15:26 PM PDT 24
Peak memory 198660 kb
Host smart-9d3fa59e-0218-493e-be4b-160bcca176bc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407317524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.2407317524
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.2099673333
Short name T351
Test name
Test status
Simulation time 242101395 ps
CPU time 2.86 seconds
Started Aug 10 05:15:21 PM PDT 24
Finished Aug 10 05:15:24 PM PDT 24
Peak memory 197844 kb
Host smart-797b2c65-6c1b-4978-91d6-904696b36e2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099673333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
2099673333
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.3224695668
Short name T123
Test name
Test status
Simulation time 529723082 ps
CPU time 1.26 seconds
Started Aug 10 05:15:24 PM PDT 24
Finished Aug 10 05:15:25 PM PDT 24
Peak memory 197212 kb
Host smart-cfe45128-aae3-4e3a-862d-d9e06d174ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224695668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.3224695668
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2686661031
Short name T150
Test name
Test status
Simulation time 114271304 ps
CPU time 1.21 seconds
Started Aug 10 05:15:23 PM PDT 24
Finished Aug 10 05:15:25 PM PDT 24
Peak memory 197628 kb
Host smart-dac0d1d7-e6fb-4f95-a2f5-a6f3bc770f96
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686661031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.2686661031
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.4261299202
Short name T360
Test name
Test status
Simulation time 303828948 ps
CPU time 4.49 seconds
Started Aug 10 05:15:27 PM PDT 24
Finished Aug 10 05:15:32 PM PDT 24
Peak memory 198600 kb
Host smart-d1bdab75-dca6-4530-b46a-b4d5bf492c88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261299202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.4261299202
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.669110305
Short name T388
Test name
Test status
Simulation time 322416594 ps
CPU time 1.26 seconds
Started Aug 10 05:15:25 PM PDT 24
Finished Aug 10 05:15:26 PM PDT 24
Peak memory 196308 kb
Host smart-d5f7ef1a-58f2-4c38-8200-8e026d637e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669110305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.669110305
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.3327371419
Short name T644
Test name
Test status
Simulation time 59015539 ps
CPU time 1.14 seconds
Started Aug 10 05:15:26 PM PDT 24
Finished Aug 10 05:15:28 PM PDT 24
Peak memory 196128 kb
Host smart-810f1555-3cd7-4983-8f4d-b434472c26a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327371419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.3327371419
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.2809229508
Short name T121
Test name
Test status
Simulation time 7800537167 ps
CPU time 102.77 seconds
Started Aug 10 05:15:27 PM PDT 24
Finished Aug 10 05:17:10 PM PDT 24
Peak memory 198668 kb
Host smart-030e8b55-d1c1-4094-b381-8aad2b2e4329
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809229508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.2809229508
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.1421689096
Short name T63
Test name
Test status
Simulation time 19951304950 ps
CPU time 331.36 seconds
Started Aug 10 05:15:23 PM PDT 24
Finished Aug 10 05:20:55 PM PDT 24
Peak memory 198904 kb
Host smart-5b6ed948-95f5-4a63-9d97-947498742aac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1421689096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.1421689096
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.411751095
Short name T858
Test name
Test status
Simulation time 82359892 ps
CPU time 0.88 seconds
Started Aug 10 05:11:02 PM PDT 24
Finished Aug 10 05:11:03 PM PDT 24
Peak memory 195292 kb
Host smart-ed822f97-90ad-4d45-ad29-87e2f81f60b0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=411751095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.411751095
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2823131497
Short name T877
Test name
Test status
Simulation time 34145978 ps
CPU time 1.03 seconds
Started Aug 10 05:11:05 PM PDT 24
Finished Aug 10 05:11:06 PM PDT 24
Peak memory 196544 kb
Host smart-545242a4-de50-46e9-ae36-0381d9c6a681
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823131497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2823131497
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.549379576
Short name T886
Test name
Test status
Simulation time 193698251 ps
CPU time 1.08 seconds
Started Aug 10 05:11:04 PM PDT 24
Finished Aug 10 05:11:05 PM PDT 24
Peak memory 196428 kb
Host smart-0f2e96bd-bd28-40d0-910f-89c0bd2332ec
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=549379576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.549379576
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.896916190
Short name T882
Test name
Test status
Simulation time 106743519 ps
CPU time 1.17 seconds
Started Aug 10 05:11:04 PM PDT 24
Finished Aug 10 05:11:06 PM PDT 24
Peak memory 197916 kb
Host smart-c2d2c3eb-af0b-4292-b559-fa26d864b3db
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896916190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.896916190
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2267191975
Short name T920
Test name
Test status
Simulation time 164452649 ps
CPU time 1.42 seconds
Started Aug 10 05:11:13 PM PDT 24
Finished Aug 10 05:11:14 PM PDT 24
Peak memory 196520 kb
Host smart-092eccff-3bfc-44eb-92c5-d7ce192a9517
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2267191975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.2267191975
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2656188811
Short name T862
Test name
Test status
Simulation time 108401262 ps
CPU time 1.04 seconds
Started Aug 10 05:11:13 PM PDT 24
Finished Aug 10 05:11:14 PM PDT 24
Peak memory 198000 kb
Host smart-c1e878ca-5353-4ac5-9a5d-098142ed75a7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656188811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2656188811
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2179195916
Short name T914
Test name
Test status
Simulation time 100037036 ps
CPU time 0.85 seconds
Started Aug 10 05:11:13 PM PDT 24
Finished Aug 10 05:11:14 PM PDT 24
Peak memory 195444 kb
Host smart-3187cb5a-2128-4222-8ff6-d3fd47fba7a5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2179195916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.2179195916
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4140225268
Short name T863
Test name
Test status
Simulation time 114892238 ps
CPU time 1.03 seconds
Started Aug 10 05:11:12 PM PDT 24
Finished Aug 10 05:11:13 PM PDT 24
Peak memory 195592 kb
Host smart-2b5f55c8-f918-4743-acef-1cff21981de6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140225268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4140225268
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.4037161237
Short name T879
Test name
Test status
Simulation time 112904943 ps
CPU time 1.21 seconds
Started Aug 10 05:11:14 PM PDT 24
Finished Aug 10 05:11:15 PM PDT 24
Peak memory 196448 kb
Host smart-09f3abda-979e-4fad-bc65-8b4c2400d34e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4037161237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.4037161237
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2097638057
Short name T923
Test name
Test status
Simulation time 98901541 ps
CPU time 1 seconds
Started Aug 10 05:11:14 PM PDT 24
Finished Aug 10 05:11:15 PM PDT 24
Peak memory 196540 kb
Host smart-ff5eaa5b-5c08-48b5-8fbd-b14c52a60f30
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097638057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2097638057
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3659507514
Short name T844
Test name
Test status
Simulation time 96715159 ps
CPU time 0.8 seconds
Started Aug 10 05:11:13 PM PDT 24
Finished Aug 10 05:11:13 PM PDT 24
Peak memory 196116 kb
Host smart-0ff831d0-3e05-423a-839c-68c872fe8fed
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3659507514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.3659507514
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.953393288
Short name T924
Test name
Test status
Simulation time 49329918 ps
CPU time 1.09 seconds
Started Aug 10 05:11:16 PM PDT 24
Finished Aug 10 05:11:17 PM PDT 24
Peak memory 198068 kb
Host smart-d79281e6-204a-4ca0-865b-4e168154ecbf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953393288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.953393288
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.769727911
Short name T934
Test name
Test status
Simulation time 151945727 ps
CPU time 1.47 seconds
Started Aug 10 05:11:15 PM PDT 24
Finished Aug 10 05:11:16 PM PDT 24
Peak memory 196988 kb
Host smart-84695306-d808-4c81-83ba-7f2643250b09
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=769727911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.769727911
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3872199667
Short name T854
Test name
Test status
Simulation time 187754945 ps
CPU time 1.37 seconds
Started Aug 10 05:11:13 PM PDT 24
Finished Aug 10 05:11:14 PM PDT 24
Peak memory 197940 kb
Host smart-e6c306cf-6c1d-400e-8970-85eba8689a76
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872199667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3872199667
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2203202635
Short name T849
Test name
Test status
Simulation time 43375621 ps
CPU time 0.98 seconds
Started Aug 10 05:11:11 PM PDT 24
Finished Aug 10 05:11:12 PM PDT 24
Peak memory 196480 kb
Host smart-e867dbc5-3393-41ef-a8d0-721f0292fdb5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2203202635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2203202635
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1016884394
Short name T921
Test name
Test status
Simulation time 94259452 ps
CPU time 0.75 seconds
Started Aug 10 05:11:14 PM PDT 24
Finished Aug 10 05:11:15 PM PDT 24
Peak memory 194896 kb
Host smart-4833e10f-5d52-403f-9a24-0fc5f5bf30b6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016884394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1016884394
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1983107333
Short name T925
Test name
Test status
Simulation time 36890495 ps
CPU time 1.18 seconds
Started Aug 10 05:11:16 PM PDT 24
Finished Aug 10 05:11:17 PM PDT 24
Peak memory 195612 kb
Host smart-a9fda934-f960-4d98-b59d-8cff5f874240
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1983107333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.1983107333
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.849048760
Short name T915
Test name
Test status
Simulation time 95589366 ps
CPU time 1.57 seconds
Started Aug 10 05:11:11 PM PDT 24
Finished Aug 10 05:11:12 PM PDT 24
Peak memory 196892 kb
Host smart-bb7ebf83-91a1-4588-8b5d-36ae82e4d5ec
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849048760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.849048760
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2211945482
Short name T911
Test name
Test status
Simulation time 936476957 ps
CPU time 1.29 seconds
Started Aug 10 05:11:13 PM PDT 24
Finished Aug 10 05:11:14 PM PDT 24
Peak memory 196612 kb
Host smart-32ab6191-c369-46e3-abcd-6a5fb240dd85
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2211945482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.2211945482
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4126179952
Short name T912
Test name
Test status
Simulation time 229177321 ps
CPU time 1.11 seconds
Started Aug 10 05:11:15 PM PDT 24
Finished Aug 10 05:11:16 PM PDT 24
Peak memory 196612 kb
Host smart-bb94db92-8dea-4bad-b9af-baf3551a3081
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126179952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4126179952
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1460445323
Short name T878
Test name
Test status
Simulation time 240856214 ps
CPU time 1.22 seconds
Started Aug 10 05:11:12 PM PDT 24
Finished Aug 10 05:11:13 PM PDT 24
Peak memory 197608 kb
Host smart-bc7eb094-919b-4245-ad92-d1e489bbd888
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1460445323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.1460445323
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3609878095
Short name T901
Test name
Test status
Simulation time 91171788 ps
CPU time 0.87 seconds
Started Aug 10 05:11:14 PM PDT 24
Finished Aug 10 05:11:15 PM PDT 24
Peak memory 195436 kb
Host smart-b2286308-a058-4c31-bb83-f7d2defa946e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609878095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3609878095
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3361968704
Short name T928
Test name
Test status
Simulation time 536149914 ps
CPU time 1.09 seconds
Started Aug 10 05:11:14 PM PDT 24
Finished Aug 10 05:11:15 PM PDT 24
Peak memory 196612 kb
Host smart-adc67bb2-a42f-4b90-98ca-d346e0411e59
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3361968704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3361968704
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2319649794
Short name T891
Test name
Test status
Simulation time 106327121 ps
CPU time 1 seconds
Started Aug 10 05:11:14 PM PDT 24
Finished Aug 10 05:11:15 PM PDT 24
Peak memory 198000 kb
Host smart-ea668336-f561-4cea-a55e-ace33b8111f1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319649794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2319649794
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2620814540
Short name T913
Test name
Test status
Simulation time 269823057 ps
CPU time 1.29 seconds
Started Aug 10 05:11:04 PM PDT 24
Finished Aug 10 05:11:06 PM PDT 24
Peak memory 198024 kb
Host smart-3c93092b-8e52-41e0-9e17-8ef93d55cfec
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2620814540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2620814540
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.513921546
Short name T860
Test name
Test status
Simulation time 87373987 ps
CPU time 1.39 seconds
Started Aug 10 05:11:04 PM PDT 24
Finished Aug 10 05:11:05 PM PDT 24
Peak memory 195704 kb
Host smart-825442e0-f435-4756-81f9-e5da5c22a24e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513921546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.513921546
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1785296914
Short name T896
Test name
Test status
Simulation time 206131035 ps
CPU time 1.07 seconds
Started Aug 10 05:11:12 PM PDT 24
Finished Aug 10 05:11:13 PM PDT 24
Peak memory 196708 kb
Host smart-c362ae73-126d-4425-a2a1-6b1ecb5a288e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1785296914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1785296914
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.477090735
Short name T845
Test name
Test status
Simulation time 311802506 ps
CPU time 1.31 seconds
Started Aug 10 05:11:16 PM PDT 24
Finished Aug 10 05:11:17 PM PDT 24
Peak memory 196692 kb
Host smart-947ad29f-1a55-489d-af46-d4c719b005e3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477090735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.477090735
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1152497161
Short name T893
Test name
Test status
Simulation time 171594782 ps
CPU time 1.37 seconds
Started Aug 10 05:11:11 PM PDT 24
Finished Aug 10 05:11:13 PM PDT 24
Peak memory 197336 kb
Host smart-4b109ca2-eb08-42f1-a2d1-2cefbd31c75a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1152497161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1152497161
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3822103460
Short name T892
Test name
Test status
Simulation time 33242232 ps
CPU time 0.79 seconds
Started Aug 10 05:11:23 PM PDT 24
Finished Aug 10 05:11:24 PM PDT 24
Peak memory 195488 kb
Host smart-5fe679e7-1e40-4c02-b0a5-cc2c277963f2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822103460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3822103460
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.765581058
Short name T885
Test name
Test status
Simulation time 102569110 ps
CPU time 0.77 seconds
Started Aug 10 05:11:24 PM PDT 24
Finished Aug 10 05:11:25 PM PDT 24
Peak memory 195264 kb
Host smart-04261428-6d2e-48a2-8244-eb8f1da6605b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=765581058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.765581058
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1122313200
Short name T850
Test name
Test status
Simulation time 427822340 ps
CPU time 1.69 seconds
Started Aug 10 05:11:25 PM PDT 24
Finished Aug 10 05:11:26 PM PDT 24
Peak memory 196888 kb
Host smart-04d3fdac-24ef-45ef-bf16-f6c92ad85af6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122313200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1122313200
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2352648589
Short name T908
Test name
Test status
Simulation time 79228132 ps
CPU time 1.25 seconds
Started Aug 10 05:11:22 PM PDT 24
Finished Aug 10 05:11:24 PM PDT 24
Peak memory 196832 kb
Host smart-d99362a9-9e1d-4268-8c68-7aeccbc0c1a0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2352648589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.2352648589
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3919856974
Short name T876
Test name
Test status
Simulation time 26256024 ps
CPU time 0.71 seconds
Started Aug 10 05:11:24 PM PDT 24
Finished Aug 10 05:11:25 PM PDT 24
Peak memory 195064 kb
Host smart-d2ff6ac4-c4e7-4dc2-9eec-cb6b53de5179
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919856974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3919856974
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1966511040
Short name T852
Test name
Test status
Simulation time 230271898 ps
CPU time 1.5 seconds
Started Aug 10 05:11:24 PM PDT 24
Finished Aug 10 05:11:26 PM PDT 24
Peak memory 196704 kb
Host smart-e0f03326-3e9d-447f-8837-f9344d9eca00
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1966511040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1966511040
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.735526222
Short name T931
Test name
Test status
Simulation time 282509442 ps
CPU time 1.56 seconds
Started Aug 10 05:11:35 PM PDT 24
Finished Aug 10 05:11:37 PM PDT 24
Peak memory 196728 kb
Host smart-122e7fc9-46c1-4bcb-9bc2-524c85d645e5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735526222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.735526222
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1784766442
Short name T936
Test name
Test status
Simulation time 379646046 ps
CPU time 1.45 seconds
Started Aug 10 05:11:26 PM PDT 24
Finished Aug 10 05:11:28 PM PDT 24
Peak memory 196684 kb
Host smart-ea906526-be36-4483-bcbe-20b21e832d75
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1784766442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.1784766442
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1364094070
Short name T933
Test name
Test status
Simulation time 104199384 ps
CPU time 1.1 seconds
Started Aug 10 05:11:26 PM PDT 24
Finished Aug 10 05:11:27 PM PDT 24
Peak memory 195968 kb
Host smart-f8be04a1-cbbf-466a-853f-3682323248cc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364094070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1364094070
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1486812878
Short name T859
Test name
Test status
Simulation time 38554666 ps
CPU time 1.07 seconds
Started Aug 10 05:11:25 PM PDT 24
Finished Aug 10 05:11:27 PM PDT 24
Peak memory 195864 kb
Host smart-a8745c12-450a-4bf8-8643-91fc323a92d7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1486812878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1486812878
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3058432139
Short name T847
Test name
Test status
Simulation time 252583821 ps
CPU time 1.2 seconds
Started Aug 10 05:11:35 PM PDT 24
Finished Aug 10 05:11:37 PM PDT 24
Peak memory 196380 kb
Host smart-8513025c-c287-417d-be1d-c3d9de492bfe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058432139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3058432139
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.815394855
Short name T929
Test name
Test status
Simulation time 46124974 ps
CPU time 0.78 seconds
Started Aug 10 05:11:35 PM PDT 24
Finished Aug 10 05:11:37 PM PDT 24
Peak memory 195344 kb
Host smart-e5c72f22-58f7-489e-ae4b-20a447c89f0c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=815394855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.815394855
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2569453086
Short name T868
Test name
Test status
Simulation time 96229949 ps
CPU time 1.42 seconds
Started Aug 10 05:11:26 PM PDT 24
Finished Aug 10 05:11:27 PM PDT 24
Peak memory 197940 kb
Host smart-c3441e85-f792-4b76-9e13-8d81c1f5b953
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569453086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2569453086
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1422523645
Short name T842
Test name
Test status
Simulation time 169624724 ps
CPU time 1.35 seconds
Started Aug 10 05:11:23 PM PDT 24
Finished Aug 10 05:11:24 PM PDT 24
Peak memory 196620 kb
Host smart-8786ce2e-209a-47a1-9797-29d643f376c9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1422523645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.1422523645
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.722210623
Short name T919
Test name
Test status
Simulation time 354544518 ps
CPU time 0.82 seconds
Started Aug 10 05:11:23 PM PDT 24
Finished Aug 10 05:11:24 PM PDT 24
Peak memory 197312 kb
Host smart-ce6894a1-cdfa-483f-a6c5-ae33c6496910
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722210623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.722210623
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.4179743202
Short name T905
Test name
Test status
Simulation time 534323748 ps
CPU time 1.06 seconds
Started Aug 10 05:11:24 PM PDT 24
Finished Aug 10 05:11:25 PM PDT 24
Peak memory 196572 kb
Host smart-06a1ca5d-6a2b-47d0-9a68-55d52d8d2943
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4179743202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.4179743202
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.695486642
Short name T903
Test name
Test status
Simulation time 79348874 ps
CPU time 1.06 seconds
Started Aug 10 05:11:24 PM PDT 24
Finished Aug 10 05:11:25 PM PDT 24
Peak memory 196576 kb
Host smart-af24a16c-7a29-43f0-993f-f0ba3b975ff4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695486642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.695486642
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1942820285
Short name T918
Test name
Test status
Simulation time 261582586 ps
CPU time 1.29 seconds
Started Aug 10 05:11:08 PM PDT 24
Finished Aug 10 05:11:09 PM PDT 24
Peak memory 198020 kb
Host smart-eecda188-08f1-4363-b300-d2eb2bfb4003
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1942820285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1942820285
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3125463739
Short name T902
Test name
Test status
Simulation time 80488017 ps
CPU time 1.26 seconds
Started Aug 10 05:11:03 PM PDT 24
Finished Aug 10 05:11:05 PM PDT 24
Peak memory 196448 kb
Host smart-3168ef35-2c8b-42cc-996d-aae60cedfbc3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125463739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3125463739
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.716325658
Short name T875
Test name
Test status
Simulation time 39133042 ps
CPU time 1.22 seconds
Started Aug 10 05:11:24 PM PDT 24
Finished Aug 10 05:11:26 PM PDT 24
Peak memory 196764 kb
Host smart-24baa234-dcb9-406b-99e2-5aa1b342a8cc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=716325658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.716325658
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2464769086
Short name T907
Test name
Test status
Simulation time 74651365 ps
CPU time 1.14 seconds
Started Aug 10 05:11:35 PM PDT 24
Finished Aug 10 05:11:36 PM PDT 24
Peak memory 191624 kb
Host smart-50a22a30-53d4-4163-ad7b-41519c1c0ef7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464769086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2464769086
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1588824850
Short name T898
Test name
Test status
Simulation time 61949084 ps
CPU time 1.2 seconds
Started Aug 10 05:11:35 PM PDT 24
Finished Aug 10 05:11:36 PM PDT 24
Peak memory 195852 kb
Host smart-dbb75276-fbc0-4547-96c1-8de47a22c2c2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1588824850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.1588824850
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4209345297
Short name T843
Test name
Test status
Simulation time 292069816 ps
CPU time 1.26 seconds
Started Aug 10 05:11:31 PM PDT 24
Finished Aug 10 05:11:33 PM PDT 24
Peak memory 198048 kb
Host smart-b1198e32-cf4c-4e61-a3b9-7550982510e4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209345297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4209345297
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1913074363
Short name T872
Test name
Test status
Simulation time 74432049 ps
CPU time 1.19 seconds
Started Aug 10 05:11:24 PM PDT 24
Finished Aug 10 05:11:25 PM PDT 24
Peak memory 197680 kb
Host smart-6a18c433-c1c4-4718-baf1-ec95e6bf232d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1913074363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.1913074363
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4026391987
Short name T881
Test name
Test status
Simulation time 110518318 ps
CPU time 0.81 seconds
Started Aug 10 05:11:23 PM PDT 24
Finished Aug 10 05:11:24 PM PDT 24
Peak memory 195260 kb
Host smart-6662c17c-e08b-47f0-83ca-d2e6369948ac
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026391987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4026391987
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2457649331
Short name T888
Test name
Test status
Simulation time 321986991 ps
CPU time 1.41 seconds
Started Aug 10 05:11:36 PM PDT 24
Finished Aug 10 05:11:38 PM PDT 24
Peak memory 196548 kb
Host smart-acbdea1e-ada9-433a-b9b4-5538f4798698
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2457649331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2457649331
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2538279791
Short name T869
Test name
Test status
Simulation time 88913971 ps
CPU time 0.87 seconds
Started Aug 10 05:11:26 PM PDT 24
Finished Aug 10 05:11:27 PM PDT 24
Peak memory 196484 kb
Host smart-6fce678e-27a2-4ae0-91c7-da66f634556a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538279791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2538279791
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3785471171
Short name T870
Test name
Test status
Simulation time 89690727 ps
CPU time 0.77 seconds
Started Aug 10 05:11:32 PM PDT 24
Finished Aug 10 05:11:33 PM PDT 24
Peak memory 195360 kb
Host smart-5aa9513a-0599-406c-8048-2ea2c87704d3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3785471171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.3785471171
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.693667631
Short name T853
Test name
Test status
Simulation time 84590975 ps
CPU time 1.25 seconds
Started Aug 10 05:11:34 PM PDT 24
Finished Aug 10 05:11:35 PM PDT 24
Peak memory 196572 kb
Host smart-0a5a784a-c3c6-4efa-bff8-109fcc1b9061
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693667631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.693667631
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1086396963
Short name T871
Test name
Test status
Simulation time 150359645 ps
CPU time 1.31 seconds
Started Aug 10 05:11:32 PM PDT 24
Finished Aug 10 05:11:34 PM PDT 24
Peak memory 195936 kb
Host smart-23e914bc-06a9-457f-8eb8-f062eb1d1bec
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1086396963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.1086396963
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1039882208
Short name T917
Test name
Test status
Simulation time 135939039 ps
CPU time 1.24 seconds
Started Aug 10 05:11:32 PM PDT 24
Finished Aug 10 05:11:34 PM PDT 24
Peak memory 195864 kb
Host smart-e86d3db7-cbd2-4047-bfaf-a25cf762ce44
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039882208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1039882208
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.720991509
Short name T874
Test name
Test status
Simulation time 680505886 ps
CPU time 1.35 seconds
Started Aug 10 05:11:33 PM PDT 24
Finished Aug 10 05:11:34 PM PDT 24
Peak memory 195748 kb
Host smart-40a5907b-e7b5-48dc-9841-dca3d78c99cf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=720991509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.720991509
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1512821160
Short name T880
Test name
Test status
Simulation time 38474705 ps
CPU time 1.28 seconds
Started Aug 10 05:11:32 PM PDT 24
Finished Aug 10 05:11:34 PM PDT 24
Peak memory 197772 kb
Host smart-70db4325-8b7d-4339-9a8d-c352726b29b1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512821160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1512821160
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2419664534
Short name T846
Test name
Test status
Simulation time 77252354 ps
CPU time 1.45 seconds
Started Aug 10 05:11:33 PM PDT 24
Finished Aug 10 05:11:34 PM PDT 24
Peak memory 196908 kb
Host smart-9e321731-0b43-4730-bdb0-22dc3ec604a0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2419664534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2419664534
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.136044767
Short name T848
Test name
Test status
Simulation time 59338252 ps
CPU time 1.13 seconds
Started Aug 10 05:11:35 PM PDT 24
Finished Aug 10 05:11:36 PM PDT 24
Peak memory 196484 kb
Host smart-b9875b44-7de1-450e-a59c-5c179dc579c3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136044767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.136044767
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.595763222
Short name T895
Test name
Test status
Simulation time 67204095 ps
CPU time 0.92 seconds
Started Aug 10 05:11:31 PM PDT 24
Finished Aug 10 05:11:32 PM PDT 24
Peak memory 195632 kb
Host smart-dc8f38c0-8e40-41f7-8a25-793b72e225d9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=595763222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.595763222
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1657039685
Short name T909
Test name
Test status
Simulation time 143097536 ps
CPU time 1.08 seconds
Started Aug 10 05:11:33 PM PDT 24
Finished Aug 10 05:11:35 PM PDT 24
Peak memory 196688 kb
Host smart-05c568be-5c2c-40fd-a388-f8f8dbca9403
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657039685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1657039685
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.4285805797
Short name T906
Test name
Test status
Simulation time 28359801 ps
CPU time 0.89 seconds
Started Aug 10 05:11:33 PM PDT 24
Finished Aug 10 05:11:34 PM PDT 24
Peak memory 195448 kb
Host smart-4faa1ca5-b7a9-4cfe-9974-79e4655e06bc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4285805797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.4285805797
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4240917639
Short name T887
Test name
Test status
Simulation time 84230963 ps
CPU time 0.75 seconds
Started Aug 10 05:11:35 PM PDT 24
Finished Aug 10 05:11:35 PM PDT 24
Peak memory 195336 kb
Host smart-0332bb7a-fb2a-4967-bfa3-389ac4c113c6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240917639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4240917639
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1216733362
Short name T900
Test name
Test status
Simulation time 64744593 ps
CPU time 1.22 seconds
Started Aug 10 05:11:11 PM PDT 24
Finished Aug 10 05:11:12 PM PDT 24
Peak memory 196612 kb
Host smart-38784fca-435d-4470-bfbf-2f504400dbab
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1216733362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1216733362
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3402718404
Short name T940
Test name
Test status
Simulation time 59999639 ps
CPU time 1.18 seconds
Started Aug 10 05:11:13 PM PDT 24
Finished Aug 10 05:11:14 PM PDT 24
Peak memory 197888 kb
Host smart-05a511e9-56f3-4a33-9b89-883a5424d514
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402718404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3402718404
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3683568500
Short name T894
Test name
Test status
Simulation time 333540000 ps
CPU time 1.03 seconds
Started Aug 10 05:11:35 PM PDT 24
Finished Aug 10 05:11:36 PM PDT 24
Peak memory 196680 kb
Host smart-308ce2f7-695d-40cb-99eb-b442c8fc2ade
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3683568500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.3683568500
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3807594709
Short name T932
Test name
Test status
Simulation time 263142608 ps
CPU time 0.91 seconds
Started Aug 10 05:11:34 PM PDT 24
Finished Aug 10 05:11:35 PM PDT 24
Peak memory 196568 kb
Host smart-cf325dfe-5fbd-422e-bbfb-aca5a3610b39
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807594709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3807594709
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1266583332
Short name T856
Test name
Test status
Simulation time 216092350 ps
CPU time 1.28 seconds
Started Aug 10 05:11:32 PM PDT 24
Finished Aug 10 05:11:33 PM PDT 24
Peak memory 197084 kb
Host smart-04abe536-d820-4b14-9dc2-78ff479995d3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1266583332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1266583332
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2980538756
Short name T904
Test name
Test status
Simulation time 32585346 ps
CPU time 0.95 seconds
Started Aug 10 05:11:34 PM PDT 24
Finished Aug 10 05:11:36 PM PDT 24
Peak memory 196500 kb
Host smart-2d41fcc1-0b70-4dbc-8c10-55614c4fde83
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980538756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2980538756
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.4096038450
Short name T890
Test name
Test status
Simulation time 70643923 ps
CPU time 1.09 seconds
Started Aug 10 05:11:31 PM PDT 24
Finished Aug 10 05:11:33 PM PDT 24
Peak memory 195692 kb
Host smart-6e80e319-e85a-4f76-8420-4daa572bc2ff
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4096038450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.4096038450
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1097433592
Short name T937
Test name
Test status
Simulation time 221071495 ps
CPU time 1.54 seconds
Started Aug 10 05:11:34 PM PDT 24
Finished Aug 10 05:11:36 PM PDT 24
Peak memory 196768 kb
Host smart-d65b2824-8234-4e66-953e-2f0f83ff98ef
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097433592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1097433592
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.4170949874
Short name T841
Test name
Test status
Simulation time 41125730 ps
CPU time 1.18 seconds
Started Aug 10 05:11:34 PM PDT 24
Finished Aug 10 05:11:35 PM PDT 24
Peak memory 194952 kb
Host smart-fb4955a3-e2e7-4703-a008-e141966e4ab7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4170949874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.4170949874
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2787547644
Short name T926
Test name
Test status
Simulation time 82229579 ps
CPU time 1.21 seconds
Started Aug 10 05:11:33 PM PDT 24
Finished Aug 10 05:11:34 PM PDT 24
Peak memory 196604 kb
Host smart-bc0198e6-d913-4a34-8abe-44a47af53e51
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787547644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2787547644
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1287839836
Short name T889
Test name
Test status
Simulation time 50591841 ps
CPU time 1.04 seconds
Started Aug 10 05:11:32 PM PDT 24
Finished Aug 10 05:11:33 PM PDT 24
Peak memory 197924 kb
Host smart-42704935-4975-4312-b093-10b976d980e1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1287839836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.1287839836
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2399176913
Short name T873
Test name
Test status
Simulation time 33011031 ps
CPU time 0.91 seconds
Started Aug 10 05:11:34 PM PDT 24
Finished Aug 10 05:11:35 PM PDT 24
Peak memory 195284 kb
Host smart-69670bf9-5f7e-41d5-9d73-863e5756d644
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399176913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2399176913
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3653705862
Short name T861
Test name
Test status
Simulation time 71661874 ps
CPU time 0.98 seconds
Started Aug 10 05:11:42 PM PDT 24
Finished Aug 10 05:11:43 PM PDT 24
Peak memory 196620 kb
Host smart-21e5385c-c16d-4d54-96de-0de0cf94d52f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3653705862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.3653705862
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1511111186
Short name T884
Test name
Test status
Simulation time 39789433 ps
CPU time 1.03 seconds
Started Aug 10 05:11:43 PM PDT 24
Finished Aug 10 05:11:44 PM PDT 24
Peak memory 196472 kb
Host smart-73c546c7-5c2f-4366-ada0-0ec95a6778b4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511111186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1511111186
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.774000348
Short name T866
Test name
Test status
Simulation time 138787148 ps
CPU time 1.21 seconds
Started Aug 10 05:11:42 PM PDT 24
Finished Aug 10 05:11:44 PM PDT 24
Peak memory 196612 kb
Host smart-335c2bdc-0df7-4b20-b01e-90067333060b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=774000348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.774000348
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2058259045
Short name T916
Test name
Test status
Simulation time 87126652 ps
CPU time 1.07 seconds
Started Aug 10 05:11:44 PM PDT 24
Finished Aug 10 05:11:45 PM PDT 24
Peak memory 198040 kb
Host smart-90a2c9d3-444c-42da-b20e-480d2ff76e89
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058259045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2058259045
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.4225281302
Short name T855
Test name
Test status
Simulation time 29257000 ps
CPU time 0.92 seconds
Started Aug 10 05:11:45 PM PDT 24
Finished Aug 10 05:11:46 PM PDT 24
Peak memory 195508 kb
Host smart-1ea89ac4-312a-4ecb-a792-3afe80909441
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4225281302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.4225281302
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.618386225
Short name T897
Test name
Test status
Simulation time 43257678 ps
CPU time 1.18 seconds
Started Aug 10 05:11:41 PM PDT 24
Finished Aug 10 05:11:42 PM PDT 24
Peak memory 195640 kb
Host smart-f27961d6-439e-42a4-9f4c-3b576724e426
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618386225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.618386225
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1699630689
Short name T864
Test name
Test status
Simulation time 106488933 ps
CPU time 0.99 seconds
Started Aug 10 05:11:41 PM PDT 24
Finished Aug 10 05:11:42 PM PDT 24
Peak memory 196572 kb
Host smart-d074e167-0352-4056-9644-916ff4bea93c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1699630689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.1699630689
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3152604372
Short name T939
Test name
Test status
Simulation time 615874564 ps
CPU time 1.34 seconds
Started Aug 10 05:11:44 PM PDT 24
Finished Aug 10 05:11:45 PM PDT 24
Peak memory 197160 kb
Host smart-70ad0933-3cde-4ea4-9cda-2169a4aafa89
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152604372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3152604372
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2448675381
Short name T865
Test name
Test status
Simulation time 91474102 ps
CPU time 1.19 seconds
Started Aug 10 05:11:43 PM PDT 24
Finished Aug 10 05:11:44 PM PDT 24
Peak memory 197968 kb
Host smart-d05c1148-f530-4709-952a-be31ab6e4e62
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2448675381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2448675381
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3879749981
Short name T899
Test name
Test status
Simulation time 169059492 ps
CPU time 1.2 seconds
Started Aug 10 05:11:43 PM PDT 24
Finished Aug 10 05:11:45 PM PDT 24
Peak memory 196868 kb
Host smart-0e74a0a7-14db-4e35-bcb5-e071ae74d3aa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879749981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3879749981
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1535735450
Short name T935
Test name
Test status
Simulation time 133332347 ps
CPU time 1.17 seconds
Started Aug 10 05:11:11 PM PDT 24
Finished Aug 10 05:11:13 PM PDT 24
Peak memory 196508 kb
Host smart-5bbaa753-f872-44fa-8634-21741adb8526
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1535735450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1535735450
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3192603839
Short name T883
Test name
Test status
Simulation time 172147583 ps
CPU time 1.35 seconds
Started Aug 10 05:11:14 PM PDT 24
Finished Aug 10 05:11:15 PM PDT 24
Peak memory 198068 kb
Host smart-ed1c9e28-cbc7-4742-aecd-69e6631dd954
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192603839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3192603839
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1175736138
Short name T927
Test name
Test status
Simulation time 109595018 ps
CPU time 1.13 seconds
Started Aug 10 05:11:12 PM PDT 24
Finished Aug 10 05:11:13 PM PDT 24
Peak memory 196556 kb
Host smart-0a66ecb5-41a0-47f5-abf9-184c7cf9f1a9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1175736138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.1175736138
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.414694151
Short name T922
Test name
Test status
Simulation time 262617521 ps
CPU time 1.22 seconds
Started Aug 10 05:11:14 PM PDT 24
Finished Aug 10 05:11:15 PM PDT 24
Peak memory 196612 kb
Host smart-f752f746-941c-44b4-bcd2-c0973e802f9f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414694151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.414694151
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.844561617
Short name T867
Test name
Test status
Simulation time 246726811 ps
CPU time 1.05 seconds
Started Aug 10 05:11:11 PM PDT 24
Finished Aug 10 05:11:12 PM PDT 24
Peak memory 198096 kb
Host smart-8a26b7bb-9d2c-48c1-a5a8-5344ed101f92
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=844561617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.844561617
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.337731599
Short name T857
Test name
Test status
Simulation time 227672412 ps
CPU time 1.19 seconds
Started Aug 10 05:11:13 PM PDT 24
Finished Aug 10 05:11:14 PM PDT 24
Peak memory 196472 kb
Host smart-f06e8c2f-7069-48c1-a7df-2c8af006ecd5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337731599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.337731599
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2535156011
Short name T851
Test name
Test status
Simulation time 115434316 ps
CPU time 1.3 seconds
Started Aug 10 05:11:13 PM PDT 24
Finished Aug 10 05:11:14 PM PDT 24
Peak memory 196772 kb
Host smart-01260003-3bd8-4f91-86f0-2d8aa00a11fb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2535156011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.2535156011
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.311573242
Short name T930
Test name
Test status
Simulation time 208784492 ps
CPU time 1.17 seconds
Started Aug 10 05:11:16 PM PDT 24
Finished Aug 10 05:11:17 PM PDT 24
Peak memory 196960 kb
Host smart-9a5e3568-2f40-45e3-8bb7-793c241bae5c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311573242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.311573242
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.400770981
Short name T910
Test name
Test status
Simulation time 69936339 ps
CPU time 0.78 seconds
Started Aug 10 05:11:13 PM PDT 24
Finished Aug 10 05:11:14 PM PDT 24
Peak memory 195232 kb
Host smart-7041e9b2-9338-4b16-a0b4-b5a898c73b84
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=400770981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.400770981
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2006969800
Short name T938
Test name
Test status
Simulation time 49353565 ps
CPU time 1.07 seconds
Started Aug 10 05:11:12 PM PDT 24
Finished Aug 10 05:11:14 PM PDT 24
Peak memory 196592 kb
Host smart-b04c3307-8a22-4e63-991f-0b0607f878c9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006969800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2006969800
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%