Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	13572506	1			T32	135735		T33	1124		T34	587
all_values[1]	13572506	1			T32	135735		T33	1124		T34	587
all_values[2]	13572506	1			T32	135735		T33	1124		T34	587
all_values[3]	13572506	1			T32	135735		T33	1124		T34	587
all_values[4]	13572506	1			T32	135735		T33	1124		T34	587
all_values[5]	13572506	1			T32	135735		T33	1124		T34	587
all_values[6]	13572506	1			T32	135735		T33	1124		T34	587
all_values[7]	13572506	1			T32	135735		T33	1124		T34	587
all_values[8]	13572506	1			T32	135735		T33	1124		T34	587
all_values[9]	13572506	1			T32	135735		T33	1124		T34	587
all_values[10]	13572506	1			T32	135735		T33	1124		T34	587
all_values[11]	13572506	1			T32	135735		T33	1124		T34	587
all_values[12]	13572506	1			T32	135735		T33	1124		T34	587
all_values[13]	13572506	1			T32	135735		T33	1124		T34	587
all_values[14]	13572506	1			T32	135735		T33	1124		T34	587
all_values[15]	13572506	1			T32	135735		T33	1124		T34	587
all_values[16]	13572506	1			T32	135735		T33	1124		T34	587
all_values[17]	13572506	1			T32	135735		T33	1124		T34	587
all_values[18]	13572506	1			T32	135735		T33	1124		T34	587
all_values[19]	13572506	1			T32	135735		T33	1124		T34	587
all_values[20]	13572506	1			T32	135735		T33	1124		T34	587
all_values[21]	13572506	1			T32	135735		T33	1124		T34	587
all_values[22]	13572506	1			T32	135735		T33	1124		T34	587
all_values[23]	13572506	1			T32	135735		T33	1124		T34	587
all_values[24]	13572506	1			T32	135735		T33	1124		T34	587
all_values[25]	13572506	1			T32	135735		T33	1124		T34	587
all_values[26]	13572506	1			T32	135735		T33	1124		T34	587
all_values[27]	13572506	1			T32	135735		T33	1124		T34	587
all_values[28]	13572506	1			T32	135735		T33	1124		T34	587
all_values[29]	13572506	1			T32	135735		T33	1124		T34	587
all_values[30]	13572506	1			T32	135735		T33	1124		T34	587
all_values[31]	13572506	1			T32	135735		T33	1124		T34	587

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

250107347

1

T32

241626

T33

35968

T34

8889

auto[1]

184212845

1

T32

192725

T34

9895

T20

1348

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101414184

1

T32

851793

T33

35968

T34

1792

auto[1]

332906008

1

T32

349172

T34

16992

T20

1104

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2606117	1			T32	21629		T33	1124		T34	24
all_values[0]	auto[0]	auto[1]	5198968	1			T32	55240		T34	268		T20	21
all_values[0]	auto[1]	auto[0]	564008	1			T32	5735		T34	36		T20	35
all_values[0]	auto[1]	auto[1]	5203413	1			T32	53131		T34	259		T20	13
all_values[1]	auto[0]	auto[0]	2607443	1			T32	21567		T33	1124		T34	36
all_values[1]	auto[0]	auto[1]	5212488	1			T32	53182		T34	170		T20	15
all_values[1]	auto[1]	auto[0]	558944	1			T32	5896		T34	24		T20	30
all_values[1]	auto[1]	auto[1]	5193631	1			T32	55090		T34	357		T20	20
all_values[2]	auto[0]	auto[0]	2611715	1			T32	20469		T33	1124		T34	20
all_values[2]	auto[0]	auto[1]	5193005	1			T32	55006		T34	349		T20	18
all_values[2]	auto[1]	auto[0]	566952	1			T32	5881		T34	5		T20	32
all_values[2]	auto[1]	auto[1]	5200834	1			T32	54379		T34	213		T20	19
all_values[3]	auto[0]	auto[0]	2606523	1			T32	20581		T33	1124		T34	28
all_values[3]	auto[0]	auto[1]	5192207	1			T32	56486		T34	287		T20	4
all_values[3]	auto[1]	auto[0]	559420	1			T32	6298		T34	42		T20	38
all_values[3]	auto[1]	auto[1]	5214356	1			T32	52370		T34	230		T20	17
all_values[4]	auto[0]	auto[0]	2606287	1			T32	20491		T33	1124		T34	43
all_values[4]	auto[0]	auto[1]	5177371	1			T32	55753		T34	170		T20	15
all_values[4]	auto[1]	auto[0]	564005	1			T32	5842		T34	31		T20	19
all_values[4]	auto[1]	auto[1]	5224843	1			T32	53649		T34	343		T20	29
all_values[5]	auto[0]	auto[0]	2608053	1			T32	21035		T33	1124		T34	31
all_values[5]	auto[0]	auto[1]	5210112	1			T32	57541		T34	346		T20	19
all_values[5]	auto[1]	auto[0]	554296	1			T32	5808		T34	6		T20	40
all_values[5]	auto[1]	auto[1]	5200045	1			T32	51351		T34	204		T20	3
all_values[6]	auto[0]	auto[0]	2607411	1			T32	21104		T33	1124		T34	20
all_values[6]	auto[0]	auto[1]	5226362	1			T32	57985		T34	295		T20	14
all_values[6]	auto[1]	auto[0]	560541	1			T32	5310		T34	21		T20	26
all_values[6]	auto[1]	auto[1]	5178192	1			T32	51336		T34	251		T20	25
all_values[7]	auto[0]	auto[0]	2606687	1			T32	20682		T33	1124		T34	11
all_values[7]	auto[0]	auto[1]	5193844	1			T32	52940		T34	167		T20	21
all_values[7]	auto[1]	auto[0]	560876	1			T32	6180		T34	31		T20	16
all_values[7]	auto[1]	auto[1]	5211099	1			T32	55933		T34	378		T20	8
all_values[8]	auto[0]	auto[0]	2606863	1			T32	20260		T33	1124		T34	33
all_values[8]	auto[0]	auto[1]	5219515	1			T32	54819		T34	169		T20	17
all_values[8]	auto[1]	auto[0]	564372	1			T32	6072		T34	6		T20	41
all_values[8]	auto[1]	auto[1]	5181756	1			T32	54584		T34	379		T20	3
all_values[9]	auto[0]	auto[0]	2610454	1			T32	20400		T33	1124		T34	54
all_values[9]	auto[0]	auto[1]	5166851	1			T32	55780		T34	187		T20	16
all_values[9]	auto[1]	auto[0]	576383	1			T32	5709		T34	31		T20	20
all_values[9]	auto[1]	auto[1]	5218818	1			T32	53846		T34	315		T20	14
all_values[10]	auto[0]	auto[0]	2615976	1			T32	21036		T33	1124		T34	62
all_values[10]	auto[0]	auto[1]	5221760	1			T32	56113		T34	303		T20	18
all_values[10]	auto[1]	auto[0]	558897	1			T32	6272		T34	22		T20	28
all_values[10]	auto[1]	auto[1]	5175873	1			T32	52314		T34	200		T20	22
all_values[11]	auto[0]	auto[0]	2612150	1			T32	20924		T33	1124		T34	18
all_values[11]	auto[0]	auto[1]	5230792	1			T32	55425		T34	371		T20	20
all_values[11]	auto[1]	auto[0]	553475	1			T32	5948		T34	4		T20	25
all_values[11]	auto[1]	auto[1]	5176089	1			T32	53438		T34	194		T20	21
all_values[12]	auto[0]	auto[0]	2611530	1			T32	20805		T33	1124		T34	16
all_values[12]	auto[0]	auto[1]	5244681	1			T32	53469		T34	174		T20	23
all_values[12]	auto[1]	auto[0]	557769	1			T32	5931		T34	21		T20	19
all_values[12]	auto[1]	auto[1]	5158526	1			T32	55530		T34	376		T20	22
all_values[13]	auto[0]	auto[0]	2609812	1			T32	21046		T33	1124		T34	48
all_values[13]	auto[0]	auto[1]	5161909	1			T32	54141		T34	256		T20	12
all_values[13]	auto[1]	auto[0]	575016	1			T32	5772		T34	12		T20	11
all_values[13]	auto[1]	auto[1]	5225769	1			T32	54776		T34	271		T20	6
all_values[14]	auto[0]	auto[0]	2600806	1			T32	20537		T33	1124		T34	41
all_values[14]	auto[0]	auto[1]	5238400	1			T32	53263		T34	225		T20	14
all_values[14]	auto[1]	auto[0]	564037	1			T32	5924		T34	13		T20	22
all_values[14]	auto[1]	auto[1]	5169263	1			T32	56011		T34	308		T20	8
all_values[15]	auto[0]	auto[0]	2613720	1			T32	20483		T33	1124		T34	20
all_values[15]	auto[0]	auto[1]	5215224	1			T32	54021		T34	281		T20	16
all_values[15]	auto[1]	auto[0]	556493	1			T32	5496		T34	24		T20	33
all_values[15]	auto[1]	auto[1]	5187069	1			T32	55735		T34	262		T20	18
all_values[16]	auto[0]	auto[0]	2612112	1			T32	20567		T33	1124		T34	23
all_values[16]	auto[0]	auto[1]	5228868	1			T32	55500		T34	239		T20	15
all_values[16]	auto[1]	auto[0]	556332	1			T32	6225		T34	75		T20	30
all_values[16]	auto[1]	auto[1]	5175194	1			T32	53443		T34	250		T20	16
all_values[17]	auto[0]	auto[0]	2604491	1			T32	21387		T33	1124		T34	37
all_values[17]	auto[0]	auto[1]	5183341	1			T32	53782		T34	344		T20	18
all_values[17]	auto[1]	auto[0]	557735	1			T32	6015		T34	5		T20	37
all_values[17]	auto[1]	auto[1]	5226939	1			T32	54551		T34	201		T20	9
all_values[18]	auto[0]	auto[0]	2608199	1			T32	20292		T33	1124		T34	12
all_values[18]	auto[0]	auto[1]	5227367	1			T32	54790		T34	121		T20	16
all_values[18]	auto[1]	auto[0]	556989	1			T32	5391		T34	30		T20	27
all_values[18]	auto[1]	auto[1]	5179951	1			T32	55262		T34	424		T20	13
all_values[19]	auto[0]	auto[0]	2600984	1			T32	20698		T33	1124		T34	58
all_values[19]	auto[0]	auto[1]	5214994	1			T32	56608		T34	238		T20	19
all_values[19]	auto[1]	auto[0]	557505	1			T32	5843		T34	17		T20	17
all_values[19]	auto[1]	auto[1]	5199023	1			T32	52586		T34	274		T20	12
all_values[20]	auto[0]	auto[0]	2614796	1			T32	20950		T33	1124		T34	61
all_values[20]	auto[0]	auto[1]	5228572	1			T32	54606		T34	323		T20	24
all_values[20]	auto[1]	auto[0]	552768	1			T32	6076		T34	14		T20	29
all_values[20]	auto[1]	auto[1]	5176370	1			T32	54103		T34	189		T20	10
all_values[21]	auto[0]	auto[0]	2607018	1			T32	20488		T33	1124		T34	21
all_values[21]	auto[0]	auto[1]	5224150	1			T32	53001		T34	262		T20	17
all_values[21]	auto[1]	auto[0]	554929	1			T32	6190		T34	36		T20	8
all_values[21]	auto[1]	auto[1]	5186409	1			T32	56056		T34	268		T20	25
all_values[22]	auto[0]	auto[0]	2609679	1			T32	20864		T33	1124		T34	19
all_values[22]	auto[0]	auto[1]	5185683	1			T32	54876		T34	140		T20	11
all_values[22]	auto[1]	auto[0]	564627	1			T32	6455		T34	49		T20	30
all_values[22]	auto[1]	auto[1]	5212517	1			T32	53540		T34	379		T20	26
all_values[23]	auto[0]	auto[0]	2604578	1			T32	20433		T33	1124		T34	35
all_values[23]	auto[0]	auto[1]	5200187	1			T32	54708		T34	147		T20	29
all_values[23]	auto[1]	auto[0]	558913	1			T32	5833		T34	20		T20	18
all_values[23]	auto[1]	auto[1]	5208828	1			T32	54761		T34	385		T20	15
all_values[24]	auto[0]	auto[0]	2608132	1			T32	20521		T33	1124		T34	40
all_values[24]	auto[0]	auto[1]	5195161	1			T32	56571		T34	262		T20	30
all_values[24]	auto[1]	auto[0]	559760	1			T32	5232		T34	8		T20	18
all_values[24]	auto[1]	auto[1]	5209453	1			T32	53411		T34	277		T20	5
all_values[25]	auto[0]	auto[0]	2607490	1			T32	20668		T33	1124		T34	13
all_values[25]	auto[0]	auto[1]	5187088	1			T32	54602		T34	253		T20	5
all_values[25]	auto[1]	auto[0]	562043	1			T32	5760		T34	17		T20	19
all_values[25]	auto[1]	auto[1]	5215885	1			T32	54705		T34	304		T20	37
all_values[26]	auto[0]	auto[0]	2604112	1			T32	20309		T33	1124		T34	52
all_values[26]	auto[0]	auto[1]	5231080	1			T32	54621		T34	296		T20	13
all_values[26]	auto[1]	auto[0]	564681	1			T32	6469		T34	3		T20	13
all_values[26]	auto[1]	auto[1]	5172633	1			T32	54336		T34	236		T20	31
all_values[27]	auto[0]	auto[0]	2603381	1			T32	20457		T33	1124		T34	34
all_values[27]	auto[0]	auto[1]	5200861	1			T32	55072		T34	124		T20	26
all_values[27]	auto[1]	auto[0]	558091	1			T32	5501		T34	13		T20	11
all_values[27]	auto[1]	auto[1]	5210173	1			T32	54705		T34	416		T20	18
all_values[28]	auto[0]	auto[0]	2612905	1			T32	20468		T33	1124		T34	45
all_values[28]	auto[0]	auto[1]	5203974	1			T32	53903		T34	246		T20	11
all_values[28]	auto[1]	auto[0]	563007	1			T32	6109		T34	5		T20	35
all_values[28]	auto[1]	auto[1]	5192620	1			T32	55255		T34	291		T20	26
all_values[29]	auto[0]	auto[0]	2613691	1			T32	20761		T33	1124		T34	68
all_values[29]	auto[0]	auto[1]	5230235	1			T32	53251		T34	239		T20	16
all_values[29]	auto[1]	auto[0]	570313	1			T32	6336		T34	12		T20	34
all_values[29]	auto[1]	auto[1]	5158267	1			T32	55387		T34	268		T20	25
all_values[30]	auto[0]	auto[0]	2603855	1			T32	20736		T33	1124		T34	32
all_values[30]	auto[0]	auto[1]	5204092	1			T32	54510		T34	224		T20	27
all_values[30]	auto[1]	auto[0]	551210	1			T32	5697		T34	55		T20	21
all_values[30]	auto[1]	auto[1]	5213349	1			T32	54792		T34	276		T20	9
all_values[31]	auto[0]	auto[0]	2607914	1			T32	20322		T33	1124		T34	34
all_values[31]	auto[0]	auto[1]	5193321	1			T32	51729		T34	324		T20	31
all_values[31]	auto[1]	auto[0]	564913	1			T32	5617		T34	15		T20	33
all_values[31]	auto[1]	auto[1]	5206358	1			T32	58067		T34	214		T20	8