Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4090330	1			T32	41860		T33	71		T34	172
all_pins[1]	4090330	1			T32	41860		T33	71		T34	172
all_pins[2]	4090330	1			T32	41860		T33	71		T34	172
all_pins[3]	4090330	1			T32	41860		T33	71		T34	172
all_pins[4]	4090330	1			T32	41860		T33	71		T34	172
all_pins[5]	4090330	1			T32	41860		T33	71		T34	172
all_pins[6]	4090330	1			T32	41860		T33	71		T34	172
all_pins[7]	4090330	1			T32	41860		T33	71		T34	172
all_pins[8]	4090330	1			T32	41860		T33	71		T34	172
all_pins[9]	4090330	1			T32	41860		T33	71		T34	172
all_pins[10]	4090330	1			T32	41860		T33	71		T34	172
all_pins[11]	4090330	1			T32	41860		T33	71		T34	172
all_pins[12]	4090330	1			T32	41860		T33	71		T34	172
all_pins[13]	4090330	1			T32	41860		T33	71		T34	172
all_pins[14]	4090330	1			T32	41860		T33	71		T34	172
all_pins[15]	4090330	1			T32	41860		T33	71		T34	172
all_pins[16]	4090330	1			T32	41860		T33	71		T34	172
all_pins[17]	4090330	1			T32	41860		T33	71		T34	172
all_pins[18]	4090330	1			T32	41860		T33	71		T34	172
all_pins[19]	4090330	1			T32	41860		T33	71		T34	172
all_pins[20]	4090330	1			T32	41860		T33	71		T34	172
all_pins[21]	4090330	1			T32	41860		T33	71		T34	172
all_pins[22]	4090330	1			T32	41860		T33	71		T34	172
all_pins[23]	4090330	1			T32	41860		T33	71		T34	172
all_pins[24]	4090330	1			T32	41860		T33	71		T34	172
all_pins[25]	4090330	1			T32	41860		T33	71		T34	172
all_pins[26]	4090330	1			T32	41860		T33	71		T34	172
all_pins[27]	4090330	1			T32	41860		T33	71		T34	172
all_pins[28]	4090330	1			T32	41860		T33	71		T34	172
all_pins[29]	4090330	1			T32	41860		T33	71		T34	172
all_pins[30]	4090330	1			T32	41860		T33	71		T34	172
all_pins[31]	4090330	1			T32	41860		T33	71		T34	172

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	81320799	1			T32	831901		T33	1194		T34	3204
values[0x1]	49569761	1			T32	507619		T33	1078		T34	2300
transitions[0x0=>0x1]	29698972	1			T32	304183		T33	544		T34	1265
transitions[0x1=>0x0]	29698810	1			T32	304183		T33	544		T34	1265

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2540725	1			T32	26276		T33	29		T34	102
all_pins[0]	values[0x1]	1549605	1			T32	15584		T33	42		T34	70
all_pins[0]	transitions[0x0=>0x1]	960187	1			T32	9554		T33	26		T34	52
all_pins[0]	transitions[0x1=>0x0]	960250	1			T32	10534		T33	17		T34	33
all_pins[1]	values[0x0]	2542271	1			T32	26057		T33	33		T34	80
all_pins[1]	values[0x1]	1548059	1			T32	15803		T33	38		T34	92
all_pins[1]	transitions[0x0=>0x1]	927483	1			T32	9601		T33	15		T34	53
all_pins[1]	transitions[0x1=>0x0]	929029	1			T32	9382		T33	19		T34	31
all_pins[2]	values[0x0]	2541117	1			T32	25855		T33	33		T34	108
all_pins[2]	values[0x1]	1549213	1			T32	16005		T33	38		T34	64
all_pins[2]	transitions[0x0=>0x1]	926381	1			T32	9504		T33	20		T34	13
all_pins[2]	transitions[0x1=>0x0]	925227	1			T32	9302		T33	20		T34	41
all_pins[3]	values[0x0]	2537687	1			T32	26297		T33	36		T34	114
all_pins[3]	values[0x1]	1552643	1			T32	15563		T33	35		T34	58
all_pins[3]	transitions[0x0=>0x1]	928427	1			T32	9208		T33	16		T34	16
all_pins[3]	transitions[0x1=>0x0]	924997	1			T32	9650		T33	19		T34	22
all_pins[4]	values[0x0]	2541545	1			T32	26352		T33	43		T34	85
all_pins[4]	values[0x1]	1548785	1			T32	15508		T33	28		T34	87
all_pins[4]	transitions[0x0=>0x1]	926419	1			T32	9329		T33	15		T34	53
all_pins[4]	transitions[0x1=>0x0]	930277	1			T32	9384		T33	22		T34	24
all_pins[5]	values[0x0]	2544640	1			T32	26436		T33	40		T34	121
all_pins[5]	values[0x1]	1545690	1			T32	15424		T33	31		T34	51
all_pins[5]	transitions[0x0=>0x1]	924786	1			T32	9531		T33	18		T34	21
all_pins[5]	transitions[0x1=>0x0]	927881	1			T32	9615		T33	15		T34	57
all_pins[6]	values[0x0]	2541355	1			T32	26293		T33	37		T34	106
all_pins[6]	values[0x1]	1548975	1			T32	15567		T33	34		T34	66
all_pins[6]	transitions[0x0=>0x1]	927919	1			T32	9551		T33	19		T34	48
all_pins[6]	transitions[0x1=>0x0]	924634	1			T32	9408		T33	16		T34	33
all_pins[7]	values[0x0]	2538913	1			T32	26000		T33	48		T34	72
all_pins[7]	values[0x1]	1551417	1			T32	15860		T33	23		T34	100
all_pins[7]	transitions[0x0=>0x1]	930875	1			T32	9645		T33	13		T34	59
all_pins[7]	transitions[0x1=>0x0]	928433	1			T32	9352		T33	24		T34	25
all_pins[8]	values[0x0]	2540889	1			T32	25865		T33	37		T34	66
all_pins[8]	values[0x1]	1549441	1			T32	15995		T33	34		T34	106
all_pins[8]	transitions[0x0=>0x1]	926653	1			T32	9646		T33	24		T34	49
all_pins[8]	transitions[0x1=>0x0]	928629	1			T32	9511		T33	13		T34	43
all_pins[9]	values[0x0]	2540244	1			T32	26170		T33	27		T34	89
all_pins[9]	values[0x1]	1550086	1			T32	15690		T33	44		T34	83
all_pins[9]	transitions[0x0=>0x1]	927496	1			T32	9446		T33	23		T34	19
all_pins[9]	transitions[0x1=>0x0]	926851	1			T32	9751		T33	13		T34	42
all_pins[10]	values[0x0]	2543766	1			T32	26399		T33	32		T34	123
all_pins[10]	values[0x1]	1546564	1			T32	15461		T33	39		T34	49
all_pins[10]	transitions[0x0=>0x1]	926934	1			T32	9169		T33	14		T34	11
all_pins[10]	transitions[0x1=>0x0]	930456	1			T32	9398		T33	19		T34	45
all_pins[11]	values[0x0]	2545510	1			T32	26363		T33	38		T34	120
all_pins[11]	values[0x1]	1544820	1			T32	15497		T33	33		T34	52
all_pins[11]	transitions[0x0=>0x1]	924852	1			T32	9436		T33	13		T34	44
all_pins[11]	transitions[0x1=>0x0]	926596	1			T32	9400		T33	19		T34	41
all_pins[12]	values[0x0]	2546282	1			T32	25893		T33	44		T34	88
all_pins[12]	values[0x1]	1544048	1			T32	15967		T33	27		T34	84
all_pins[12]	transitions[0x0=>0x1]	927562	1			T32	9841		T33	13		T34	60
all_pins[12]	transitions[0x1=>0x0]	928334	1			T32	9371		T33	19		T34	28
all_pins[13]	values[0x0]	2534165	1			T32	25942		T33	34		T34	107
all_pins[13]	values[0x1]	1556165	1			T32	15918		T33	37		T34	65
all_pins[13]	transitions[0x0=>0x1]	934427	1			T32	9408		T33	21		T34	29
all_pins[13]	transitions[0x1=>0x0]	922310	1			T32	9457		T33	11		T34	48
all_pins[14]	values[0x0]	2540579	1			T32	25808		T33	35		T34	96
all_pins[14]	values[0x1]	1549751	1			T32	16052		T33	36		T34	76
all_pins[14]	transitions[0x0=>0x1]	923949	1			T32	9838		T33	15		T34	54
all_pins[14]	transitions[0x1=>0x0]	930363	1			T32	9704		T33	16		T34	43
all_pins[15]	values[0x0]	2546576	1			T32	25487		T33	45		T34	110
all_pins[15]	values[0x1]	1543754	1			T32	16373		T33	26		T34	62
all_pins[15]	transitions[0x0=>0x1]	924789	1			T32	9682		T33	7		T34	37
all_pins[15]	transitions[0x1=>0x0]	930786	1			T32	9361		T33	17		T34	51
all_pins[16]	values[0x0]	2545330	1			T32	26164		T33	40		T34	107
all_pins[16]	values[0x1]	1545000	1			T32	15696		T33	31		T34	65
all_pins[16]	transitions[0x0=>0x1]	926364	1			T32	9081		T33	19		T34	43
all_pins[16]	transitions[0x1=>0x0]	925118	1			T32	9758		T33	14		T34	40
all_pins[17]	values[0x0]	2534119	1			T32	25995		T33	34		T34	125
all_pins[17]	values[0x1]	1556211	1			T32	15865		T33	37		T34	47
all_pins[17]	transitions[0x0=>0x1]	931395	1			T32	9334		T33	22		T34	13
all_pins[17]	transitions[0x1=>0x0]	920184	1			T32	9165		T33	16		T34	31
all_pins[18]	values[0x0]	2534722	1			T32	25734		T33	37		T34	65
all_pins[18]	values[0x1]	1555608	1			T32	16126		T33	34		T34	107
all_pins[18]	transitions[0x0=>0x1]	930053	1			T32	9778		T33	12		T34	81
all_pins[18]	transitions[0x1=>0x0]	930656	1			T32	9517		T33	15		T34	21
all_pins[19]	values[0x0]	2539345	1			T32	26111		T33	36		T34	105
all_pins[19]	values[0x1]	1550985	1			T32	15749		T33	35		T34	67
all_pins[19]	transitions[0x0=>0x1]	924253	1			T32	9301		T33	15		T34	26
all_pins[19]	transitions[0x1=>0x0]	928876	1			T32	9678		T33	14		T34	66
all_pins[20]	values[0x0]	2544530	1			T32	25810		T33	36		T34	127
all_pins[20]	values[0x1]	1545800	1			T32	16050		T33	35		T34	45
all_pins[20]	transitions[0x0=>0x1]	923011	1			T32	9555		T33	19		T34	24
all_pins[20]	transitions[0x1=>0x0]	928196	1			T32	9254		T33	19		T34	46
all_pins[21]	values[0x0]	2541495	1			T32	25663		T33	35		T34	109
all_pins[21]	values[0x1]	1548835	1			T32	16197		T33	36		T34	63
all_pins[21]	transitions[0x0=>0x1]	927897	1			T32	9520		T33	16		T34	49
all_pins[21]	transitions[0x1=>0x0]	924862	1			T32	9373		T33	15		T34	31
all_pins[22]	values[0x0]	2543620	1			T32	26268		T33	39		T34	71
all_pins[22]	values[0x1]	1546710	1			T32	15592		T33	32		T34	101
all_pins[22]	transitions[0x0=>0x1]	923294	1			T32	9239		T33	17		T34	68
all_pins[22]	transitions[0x1=>0x0]	925419	1			T32	9844		T33	21		T34	30
all_pins[23]	values[0x0]	2537366	1			T32	26173		T33	31		T34	85
all_pins[23]	values[0x1]	1552964	1			T32	15687		T33	40		T34	87
all_pins[23]	transitions[0x0=>0x1]	928430	1			T32	9430		T33	23		T34	25
all_pins[23]	transitions[0x1=>0x0]	922176	1			T32	9335		T33	15		T34	39
all_pins[24]	values[0x0]	2541133	1			T32	25857		T33	34		T34	108
all_pins[24]	values[0x1]	1549197	1			T32	16003		T33	37		T34	64
all_pins[24]	transitions[0x0=>0x1]	924881	1			T32	9567		T33	18		T34	26
all_pins[24]	transitions[0x1=>0x0]	928648	1			T32	9251		T33	21		T34	49
all_pins[25]	values[0x0]	2540808	1			T32	26194		T33	41		T34	93
all_pins[25]	values[0x1]	1549522	1			T32	15666		T33	30		T34	79
all_pins[25]	transitions[0x0=>0x1]	928196	1			T32	9278		T33	17		T34	64
all_pins[25]	transitions[0x1=>0x0]	927871	1			T32	9615		T33	24		T34	49
all_pins[26]	values[0x0]	2541935	1			T32	25856		T33	35		T34	100
all_pins[26]	values[0x1]	1548395	1			T32	16004		T33	36		T34	72
all_pins[26]	transitions[0x0=>0x1]	927645	1			T32	9745		T33	20		T34	26
all_pins[26]	transitions[0x1=>0x0]	928772	1			T32	9407		T33	14		T34	33
all_pins[27]	values[0x0]	2541938	1			T32	25816		T33	36		T34	74
all_pins[27]	values[0x1]	1548392	1			T32	16044		T33	35		T34	98
all_pins[27]	transitions[0x0=>0x1]	927751	1			T32	9356		T33	14		T34	49
all_pins[27]	transitions[0x1=>0x0]	927754	1			T32	9316		T33	15		T34	23
all_pins[28]	values[0x0]	2541378	1			T32	25658		T33	41		T34	113
all_pins[28]	values[0x1]	1548952	1			T32	16202		T33	30		T34	59
all_pins[28]	transitions[0x0=>0x1]	925963	1			T32	9558		T33	13		T34	21
all_pins[28]	transitions[0x1=>0x0]	925403	1			T32	9400		T33	18		T34	60
all_pins[29]	values[0x0]	2547535	1			T32	25908		T33	47		T34	107
all_pins[29]	values[0x1]	1542795	1			T32	15952		T33	24		T34	65
all_pins[29]	transitions[0x0=>0x1]	923022	1			T32	9496		T33	13		T34	44
all_pins[29]	transitions[0x1=>0x0]	929179	1			T32	9746		T33	19		T34	38
all_pins[30]	values[0x0]	2538781	1			T32	25905		T33	43		T34	107
all_pins[30]	values[0x1]	1551549	1			T32	15955		T33	28		T34	65
all_pins[30]	transitions[0x0=>0x1]	929280	1			T32	9541		T33	15		T34	48
all_pins[30]	transitions[0x1=>0x0]	920526	1			T32	9538		T33	11		T34	48
all_pins[31]	values[0x0]	2540500	1			T32	25296		T33	38		T34	121
all_pins[31]	values[0x1]	1549830	1			T32	16564		T33	33		T34	51
all_pins[31]	transitions[0x0=>0x1]	928398	1			T32	10015		T33	19		T34	40
all_pins[31]	transitions[0x1=>0x0]	930117	1			T32	9406		T33	14		T34	54