Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	13572506	1			T32	135735		T33	1124		T34	587
all_values[1]	13572506	1			T32	135735		T33	1124		T34	587
all_values[2]	13572506	1			T32	135735		T33	1124		T34	587
all_values[3]	13572506	1			T32	135735		T33	1124		T34	587
all_values[4]	13572506	1			T32	135735		T33	1124		T34	587
all_values[5]	13572506	1			T32	135735		T33	1124		T34	587
all_values[6]	13572506	1			T32	135735		T33	1124		T34	587
all_values[7]	13572506	1			T32	135735		T33	1124		T34	587
all_values[8]	13572506	1			T32	135735		T33	1124		T34	587
all_values[9]	13572506	1			T32	135735		T33	1124		T34	587
all_values[10]	13572506	1			T32	135735		T33	1124		T34	587
all_values[11]	13572506	1			T32	135735		T33	1124		T34	587
all_values[12]	13572506	1			T32	135735		T33	1124		T34	587
all_values[13]	13572506	1			T32	135735		T33	1124		T34	587
all_values[14]	13572506	1			T32	135735		T33	1124		T34	587
all_values[15]	13572506	1			T32	135735		T33	1124		T34	587
all_values[16]	13572506	1			T32	135735		T33	1124		T34	587
all_values[17]	13572506	1			T32	135735		T33	1124		T34	587
all_values[18]	13572506	1			T32	135735		T33	1124		T34	587
all_values[19]	13572506	1			T32	135735		T33	1124		T34	587
all_values[20]	13572506	1			T32	135735		T33	1124		T34	587
all_values[21]	13572506	1			T32	135735		T33	1124		T34	587
all_values[22]	13572506	1			T32	135735		T33	1124		T34	587
all_values[23]	13572506	1			T32	135735		T33	1124		T34	587
all_values[24]	13572506	1			T32	135735		T33	1124		T34	587
all_values[25]	13572506	1			T32	135735		T33	1124		T34	587
all_values[26]	13572506	1			T32	135735		T33	1124		T34	587
all_values[27]	13572506	1			T32	135735		T33	1124		T34	587
all_values[28]	13572506	1			T32	135735		T33	1124		T34	587
all_values[29]	13572506	1			T32	135735		T33	1124		T34	587
all_values[30]	13572506	1			T32	135735		T33	1124		T34	587
all_values[31]	13572506	1			T32	135735		T33	1124		T34	587

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

250107347

1

T32

241626

T33

35968

T34

8889

auto[1]

184212845

1

T32

192725

T34

9895

T20

1348

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101414184

1

T32

851793

T33

35968

T34

1792

auto[1]

332906008

1

T32

349172

T34

16992

T20

1104

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

429454699

1

T32

428496

T33

35968

T34

18784

auto[1]

4865493

1

T32

58552

T20

122

T26

12592

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2606117	1			T32	21629		T33	1124		T34	24
all_values[0]	auto[0]	auto[0]	auto[1]	5122769	1			T32	54279		T34	268		T20	21
all_values[0]	auto[0]	auto[1]	auto[0]	564008	1			T32	5735		T34	36		T20	35
all_values[0]	auto[0]	auto[1]	auto[1]	5127845	1			T32	52241		T34	259		T20	13
all_values[0]	auto[1]	auto[0]	auto[1]	76199	1			T32	961		T26	200		T31	14
all_values[0]	auto[1]	auto[1]	auto[1]	75568	1			T32	890		T26	191		T31	6
all_values[1]	auto[0]	auto[0]	auto[0]	2607443	1			T32	21567		T33	1124		T34	36
all_values[1]	auto[0]	auto[0]	auto[1]	5136494	1			T32	52258		T34	170		T20	13
all_values[1]	auto[0]	auto[1]	auto[0]	558944	1			T32	5896		T34	24		T20	30
all_values[1]	auto[0]	auto[1]	auto[1]	5117835	1			T32	54210		T34	357		T20	19
all_values[1]	auto[1]	auto[0]	auto[1]	75994	1			T32	924		T20	2		T26	194
all_values[1]	auto[1]	auto[1]	auto[1]	75796	1			T32	880		T20	1		T26	191
all_values[2]	auto[0]	auto[0]	auto[0]	2611715	1			T32	20469		T33	1124		T34	20
all_values[2]	auto[0]	auto[0]	auto[1]	5117142	1			T32	54094		T34	349		T20	18
all_values[2]	auto[0]	auto[1]	auto[0]	566952	1			T32	5881		T34	5		T20	32
all_values[2]	auto[0]	auto[1]	auto[1]	5124561	1			T32	53516		T34	213		T20	15
all_values[2]	auto[1]	auto[0]	auto[1]	75863	1			T32	912		T26	202		T31	12
all_values[2]	auto[1]	auto[1]	auto[1]	76273	1			T32	863		T20	4		T26	180
all_values[3]	auto[0]	auto[0]	auto[0]	2606523	1			T32	20581		T33	1124		T34	28
all_values[3]	auto[0]	auto[0]	auto[1]	5116033	1			T32	55529		T34	287		T20	4
all_values[3]	auto[0]	auto[1]	auto[0]	559420	1			T32	6298		T34	42		T20	38
all_values[3]	auto[0]	auto[1]	auto[1]	5138342	1			T32	51496		T34	230		T20	13
all_values[3]	auto[1]	auto[0]	auto[1]	76174	1			T32	957		T26	202		T31	10
all_values[3]	auto[1]	auto[1]	auto[1]	76014	1			T32	874		T20	4		T26	199
all_values[4]	auto[0]	auto[0]	auto[0]	2606287	1			T32	20491		T33	1124		T34	43
all_values[4]	auto[0]	auto[0]	auto[1]	5101352	1			T32	54848		T34	170		T20	13
all_values[4]	auto[0]	auto[1]	auto[0]	564005	1			T32	5842		T34	31		T20	19
all_values[4]	auto[0]	auto[1]	auto[1]	5148657	1			T32	52769		T34	343		T20	26
all_values[4]	auto[1]	auto[0]	auto[1]	76019	1			T32	905		T20	2		T26	218
all_values[4]	auto[1]	auto[1]	auto[1]	76186	1			T32	880		T20	3		T26	187
all_values[5]	auto[0]	auto[0]	auto[0]	2608053	1			T32	21035		T33	1124		T34	31
all_values[5]	auto[0]	auto[0]	auto[1]	5133766	1			T32	56627		T34	346		T20	18
all_values[5]	auto[0]	auto[1]	auto[0]	554296	1			T32	5808		T34	6		T20	40
all_values[5]	auto[0]	auto[1]	auto[1]	5124206	1			T32	50437		T34	204		T20	2
all_values[5]	auto[1]	auto[0]	auto[1]	76346	1			T32	914		T20	1		T26	229
all_values[5]	auto[1]	auto[1]	auto[1]	75839	1			T32	914		T20	1		T26	174
all_values[6]	auto[0]	auto[0]	auto[0]	2607411	1			T32	21104		T33	1124		T34	20
all_values[6]	auto[0]	auto[0]	auto[1]	5150194	1			T32	57054		T34	295		T20	13
all_values[6]	auto[0]	auto[1]	auto[0]	560541	1			T32	5310		T34	21		T20	26
all_values[6]	auto[0]	auto[1]	auto[1]	5102271	1			T32	50446		T34	251		T20	21
all_values[6]	auto[1]	auto[0]	auto[1]	76168	1			T32	931		T20	1		T26	193
all_values[6]	auto[1]	auto[1]	auto[1]	75921	1			T32	890		T20	4		T26	204
all_values[7]	auto[0]	auto[0]	auto[0]	2606687	1			T32	20682		T33	1124		T34	11
all_values[7]	auto[0]	auto[0]	auto[1]	5117657	1			T32	52053		T34	167		T20	18
all_values[7]	auto[0]	auto[1]	auto[0]	560876	1			T32	6180		T34	31		T20	16
all_values[7]	auto[0]	auto[1]	auto[1]	5135246	1			T32	54980		T34	378		T20	4
all_values[7]	auto[1]	auto[0]	auto[1]	76187	1			T32	887		T20	3		T26	226
all_values[7]	auto[1]	auto[1]	auto[1]	75853	1			T32	953		T20	4		T26	177
all_values[8]	auto[0]	auto[0]	auto[0]	2606863	1			T32	20260		T33	1124		T34	33
all_values[8]	auto[0]	auto[0]	auto[1]	5142964	1			T32	53918		T34	169		T20	16
all_values[8]	auto[0]	auto[1]	auto[0]	564372	1			T32	6072		T34	6		T20	41
all_values[8]	auto[0]	auto[1]	auto[1]	5106268	1			T32	53659		T34	379		T20	2
all_values[8]	auto[1]	auto[0]	auto[1]	76551	1			T32	901		T20	1		T26	197
all_values[8]	auto[1]	auto[1]	auto[1]	75488	1			T32	925		T20	1		T26	193
all_values[9]	auto[0]	auto[0]	auto[0]	2610454	1			T32	20400		T33	1124		T34	54
all_values[9]	auto[0]	auto[0]	auto[1]	5090737	1			T32	54829		T34	187		T20	15
all_values[9]	auto[0]	auto[1]	auto[0]	576383	1			T32	5709		T34	31		T20	20
all_values[9]	auto[0]	auto[1]	auto[1]	5142930	1			T32	52998		T34	315		T20	12
all_values[9]	auto[1]	auto[0]	auto[1]	76114	1			T32	951		T20	1		T26	178
all_values[9]	auto[1]	auto[1]	auto[1]	75888	1			T32	848		T20	2		T26	206
all_values[10]	auto[0]	auto[0]	auto[0]	2615976	1			T32	21036		T33	1124		T34	62
all_values[10]	auto[0]	auto[0]	auto[1]	5145421	1			T32	55226		T34	303		T20	16
all_values[10]	auto[0]	auto[1]	auto[0]	558897	1			T32	6272		T34	22		T20	28
all_values[10]	auto[0]	auto[1]	auto[1]	5100308	1			T32	51372		T34	200		T20	19
all_values[10]	auto[1]	auto[0]	auto[1]	76339	1			T32	887		T20	2		T26	210
all_values[10]	auto[1]	auto[1]	auto[1]	75565	1			T32	942		T20	3		T26	184
all_values[11]	auto[0]	auto[0]	auto[0]	2612150	1			T32	20924		T33	1124		T34	18
all_values[11]	auto[0]	auto[0]	auto[1]	5154110	1			T32	54515		T34	371		T20	17
all_values[11]	auto[0]	auto[1]	auto[0]	553475	1			T32	5948		T34	4		T20	25
all_values[11]	auto[0]	auto[1]	auto[1]	5101042	1			T32	52536		T34	194		T20	18
all_values[11]	auto[1]	auto[0]	auto[1]	76682	1			T32	910		T20	3		T26	203
all_values[11]	auto[1]	auto[1]	auto[1]	75047	1			T32	902		T20	3		T26	206
all_values[12]	auto[0]	auto[0]	auto[0]	2611530	1			T32	20805		T33	1124		T34	16
all_values[12]	auto[0]	auto[0]	auto[1]	5168173	1			T32	52552		T34	174		T20	19
all_values[12]	auto[0]	auto[1]	auto[0]	557769	1			T32	5931		T34	21		T20	19
all_values[12]	auto[0]	auto[1]	auto[1]	5082642	1			T32	54628		T34	376		T20	20
all_values[12]	auto[1]	auto[0]	auto[1]	76508	1			T32	917		T20	4		T26	195
all_values[12]	auto[1]	auto[1]	auto[1]	75884	1			T32	902		T20	2		T26	202
all_values[13]	auto[0]	auto[0]	auto[0]	2609812	1			T32	21046		T33	1124		T34	48
all_values[13]	auto[0]	auto[0]	auto[1]	5085642	1			T32	53240		T34	256		T20	11
all_values[13]	auto[0]	auto[1]	auto[0]	575016	1			T32	5772		T34	12		T20	11
all_values[13]	auto[0]	auto[1]	auto[1]	5149967	1			T32	53831		T34	271		T20	5
all_values[13]	auto[1]	auto[0]	auto[1]	76267	1			T32	901		T20	1		T26	183
all_values[13]	auto[1]	auto[1]	auto[1]	75802	1			T32	945		T20	1		T26	200
all_values[14]	auto[0]	auto[0]	auto[0]	2600806	1			T32	20537		T33	1124		T34	41
all_values[14]	auto[0]	auto[0]	auto[1]	5162147	1			T32	52326		T34	225		T20	12
all_values[14]	auto[0]	auto[1]	auto[0]	564037	1			T32	5924		T34	13		T20	22
all_values[14]	auto[0]	auto[1]	auto[1]	5093336	1			T32	55074		T34	308		T20	6
all_values[14]	auto[1]	auto[0]	auto[1]	76253	1			T32	937		T20	2		T26	196
all_values[14]	auto[1]	auto[1]	auto[1]	75927	1			T32	937		T20	2		T26	194
all_values[15]	auto[0]	auto[0]	auto[0]	2613720	1			T32	20483		T33	1124		T34	20
all_values[15]	auto[0]	auto[0]	auto[1]	5138623	1			T32	53147		T34	281		T20	15
all_values[15]	auto[0]	auto[1]	auto[0]	556493	1			T32	5496		T34	24		T20	33
all_values[15]	auto[0]	auto[1]	auto[1]	5111665	1			T32	54763		T34	262		T20	16
all_values[15]	auto[1]	auto[0]	auto[1]	76601	1			T32	874		T20	1		T26	197
all_values[15]	auto[1]	auto[1]	auto[1]	75404	1			T32	972		T20	2		T26	212
all_values[16]	auto[0]	auto[0]	auto[0]	2612112	1			T32	20567		T33	1124		T34	23
all_values[16]	auto[0]	auto[0]	auto[1]	5153052	1			T32	54626		T34	239		T20	15
all_values[16]	auto[0]	auto[1]	auto[0]	556332	1			T32	6225		T34	75		T20	30
all_values[16]	auto[0]	auto[1]	auto[1]	5099269	1			T32	52489		T34	250		T20	14
all_values[16]	auto[1]	auto[0]	auto[1]	75816	1			T32	874		T26	214		T31	10
all_values[16]	auto[1]	auto[1]	auto[1]	75925	1			T32	954		T20	2		T26	202
all_values[17]	auto[0]	auto[0]	auto[0]	2604491	1			T32	21387		T33	1124		T34	37
all_values[17]	auto[0]	auto[0]	auto[1]	5106736	1			T32	52846		T34	344		T20	17
all_values[17]	auto[0]	auto[1]	auto[0]	557735	1			T32	6015		T34	5		T20	37
all_values[17]	auto[0]	auto[1]	auto[1]	5150754	1			T32	53698		T34	201		T20	8
all_values[17]	auto[1]	auto[0]	auto[1]	76605	1			T32	936		T20	1		T26	172
all_values[17]	auto[1]	auto[1]	auto[1]	76185	1			T32	853		T20	1		T26	229
all_values[18]	auto[0]	auto[0]	auto[0]	2608199	1			T32	20292		T33	1124		T34	12
all_values[18]	auto[0]	auto[0]	auto[1]	5151230	1			T32	53836		T34	121		T20	13
all_values[18]	auto[0]	auto[1]	auto[0]	556989	1			T32	5391		T34	30		T20	27
all_values[18]	auto[0]	auto[1]	auto[1]	5104125	1			T32	54336		T34	424		T20	12
all_values[18]	auto[1]	auto[0]	auto[1]	76137	1			T32	954		T20	3		T26	190
all_values[18]	auto[1]	auto[1]	auto[1]	75826	1			T32	926		T20	1		T26	194
all_values[19]	auto[0]	auto[0]	auto[0]	2600984	1			T32	20698		T33	1124		T34	58
all_values[19]	auto[0]	auto[0]	auto[1]	5138873	1			T32	55607		T34	238		T20	17
all_values[19]	auto[0]	auto[1]	auto[0]	557505	1			T32	5843		T34	17		T20	17
all_values[19]	auto[0]	auto[1]	auto[1]	5123239	1			T32	51740		T34	274		T20	11
all_values[19]	auto[1]	auto[0]	auto[1]	76121	1			T32	1001		T20	2		T26	195
all_values[19]	auto[1]	auto[1]	auto[1]	75784	1			T32	846		T20	1		T26	211
all_values[20]	auto[0]	auto[0]	auto[0]	2614796	1			T32	20950		T33	1124		T34	61
all_values[20]	auto[0]	auto[0]	auto[1]	5152265	1			T32	53686		T34	323		T20	19
all_values[20]	auto[0]	auto[1]	auto[0]	552768	1			T32	6076		T34	14		T20	29
all_values[20]	auto[0]	auto[1]	auto[1]	5100784	1			T32	53167		T34	189		T20	8
all_values[20]	auto[1]	auto[0]	auto[1]	76307	1			T32	920		T20	5		T26	192
all_values[20]	auto[1]	auto[1]	auto[1]	75586	1			T32	936		T20	2		T26	197
all_values[21]	auto[0]	auto[0]	auto[0]	2607018	1			T32	20488		T33	1124		T34	21
all_values[21]	auto[0]	auto[0]	auto[1]	5148178	1			T32	52120		T34	262		T20	14
all_values[21]	auto[0]	auto[1]	auto[0]	554929	1			T32	6190		T34	36		T20	8
all_values[21]	auto[0]	auto[1]	auto[1]	5110853	1			T32	55124		T34	268		T20	23
all_values[21]	auto[1]	auto[0]	auto[1]	75972	1			T32	881		T20	3		T26	193
all_values[21]	auto[1]	auto[1]	auto[1]	75556	1			T32	932		T20	2		T26	188
all_values[22]	auto[0]	auto[0]	auto[0]	2609679	1			T32	20864		T33	1124		T34	19
all_values[22]	auto[0]	auto[0]	auto[1]	5109609	1			T32	53929		T34	140		T20	11
all_values[22]	auto[0]	auto[1]	auto[0]	564627	1			T32	6455		T34	49		T20	30
all_values[22]	auto[0]	auto[1]	auto[1]	5136834	1			T32	52674		T34	379		T20	21
all_values[22]	auto[1]	auto[0]	auto[1]	76074	1			T32	947		T26	190		T31	6
all_values[22]	auto[1]	auto[1]	auto[1]	75683	1			T32	866		T20	5		T26	192
all_values[23]	auto[0]	auto[0]	auto[0]	2604578	1			T32	20433		T33	1124		T34	35
all_values[23]	auto[0]	auto[0]	auto[1]	5124011	1			T32	53827		T34	147		T20	27
all_values[23]	auto[0]	auto[1]	auto[0]	558913	1			T32	5833		T34	20		T20	18
all_values[23]	auto[0]	auto[1]	auto[1]	5132818	1			T32	53815		T34	385		T20	13
all_values[23]	auto[1]	auto[0]	auto[1]	76176	1			T32	881		T20	2		T26	180
all_values[23]	auto[1]	auto[1]	auto[1]	76010	1			T32	946		T20	2		T26	215
all_values[24]	auto[0]	auto[0]	auto[0]	2608132	1			T32	20521		T33	1124		T34	40
all_values[24]	auto[0]	auto[0]	auto[1]	5118902	1			T32	55637		T34	262		T20	27
all_values[24]	auto[0]	auto[1]	auto[0]	559760	1			T32	5232		T34	8		T20	18
all_values[24]	auto[0]	auto[1]	auto[1]	5133824	1			T32	52525		T34	277		T20	5
all_values[24]	auto[1]	auto[0]	auto[1]	76259	1			T32	934		T20	3		T26	190
all_values[24]	auto[1]	auto[1]	auto[1]	75629	1			T32	886		T26	192		T31	11
all_values[25]	auto[0]	auto[0]	auto[0]	2607490	1			T32	20668		T33	1124		T34	13
all_values[25]	auto[0]	auto[0]	auto[1]	5110581	1			T32	53671		T34	253		T20	4
all_values[25]	auto[0]	auto[1]	auto[0]	562043	1			T32	5760		T34	17		T20	19
all_values[25]	auto[0]	auto[1]	auto[1]	5140056	1			T32	53864		T34	304		T20	35
all_values[25]	auto[1]	auto[0]	auto[1]	76507	1			T32	931		T20	1		T26	210
all_values[25]	auto[1]	auto[1]	auto[1]	75829	1			T32	841		T20	2		T26	195
all_values[26]	auto[0]	auto[0]	auto[0]	2604112	1			T32	20309		T33	1124		T34	52
all_values[26]	auto[0]	auto[0]	auto[1]	5154559	1			T32	53694		T34	296		T20	11
all_values[26]	auto[0]	auto[1]	auto[0]	564681	1			T32	6469		T34	3		T20	13
all_values[26]	auto[0]	auto[1]	auto[1]	5097293	1			T32	53409		T34	236		T20	29
all_values[26]	auto[1]	auto[0]	auto[1]	76521	1			T32	927		T20	2		T26	211
all_values[26]	auto[1]	auto[1]	auto[1]	75340	1			T32	927		T20	2		T26	164
all_values[27]	auto[0]	auto[0]	auto[0]	2603381	1			T32	20457		T33	1124		T34	34
all_values[27]	auto[0]	auto[0]	auto[1]	5124287	1			T32	54105		T34	124		T20	22
all_values[27]	auto[0]	auto[1]	auto[0]	558091	1			T32	5501		T34	13		T20	11
all_values[27]	auto[0]	auto[1]	auto[1]	5134618	1			T32	53820		T34	416		T20	16
all_values[27]	auto[1]	auto[0]	auto[1]	76574	1			T32	967		T20	4		T26	206
all_values[27]	auto[1]	auto[1]	auto[1]	75555	1			T32	885		T20	2		T26	179
all_values[28]	auto[0]	auto[0]	auto[0]	2612905	1			T32	20468		T33	1124		T34	45
all_values[28]	auto[0]	auto[0]	auto[1]	5128036	1			T32	53019		T34	246		T20	9
all_values[28]	auto[0]	auto[1]	auto[0]	563007	1			T32	6109		T34	5		T20	35
all_values[28]	auto[0]	auto[1]	auto[1]	5116882	1			T32	54320		T34	291		T20	25
all_values[28]	auto[1]	auto[0]	auto[1]	75938	1			T32	884		T20	2		T26	192
all_values[28]	auto[1]	auto[1]	auto[1]	75738	1			T32	935		T20	1		T26	186
all_values[29]	auto[0]	auto[0]	auto[0]	2613691	1			T32	20761		T33	1124		T34	68
all_values[29]	auto[0]	auto[0]	auto[1]	5153621	1			T32	52275		T34	239		T20	14
all_values[29]	auto[0]	auto[1]	auto[0]	570313	1			T32	6336		T34	12		T20	34
all_values[29]	auto[0]	auto[1]	auto[1]	5082689	1			T32	54491		T34	268		T20	22
all_values[29]	auto[1]	auto[0]	auto[1]	76614	1			T32	976		T20	2		T26	206
all_values[29]	auto[1]	auto[1]	auto[1]	75578	1			T32	896		T20	3		T26	190
all_values[30]	auto[0]	auto[0]	auto[0]	2603855	1			T32	20736		T33	1124		T34	32
all_values[30]	auto[0]	auto[0]	auto[1]	5127678	1			T32	53624		T34	224		T20	26
all_values[30]	auto[0]	auto[1]	auto[0]	551210	1			T32	5697		T34	55		T20	21
all_values[30]	auto[0]	auto[1]	auto[1]	5136944	1			T32	53862		T34	276		T20	8
all_values[30]	auto[1]	auto[0]	auto[1]	76414	1			T32	886		T20	1		T26	209
all_values[30]	auto[1]	auto[1]	auto[1]	76405	1			T32	930		T20	1		T26	197
all_values[31]	auto[0]	auto[0]	auto[0]	2607914	1			T32	20322		T33	1124		T34	34
all_values[31]	auto[0]	auto[0]	auto[1]	5116694	1			T32	50757		T34	324		T20	29
all_values[31]	auto[0]	auto[1]	auto[0]	564913	1			T32	5617		T34	15		T20	33
all_values[31]	auto[0]	auto[1]	auto[1]	5130876	1			T32	57131		T34	214		T20	7
all_values[31]	auto[1]	auto[0]	auto[1]	76627	1			T32	972		T20	2		T26	163
all_values[31]	auto[1]	auto[1]	auto[1]	75482	1			T32	936		T20	1		T26	225

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal