Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[1]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[2]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[3]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[4]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[5]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[6]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[7]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[8]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[9]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[10]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[11]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[12]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[13]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[14]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[15]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[16]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[17]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[18]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[19]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[20]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[21]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[22]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[23]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[24]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[25]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[26]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[27]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[28]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[29]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[30]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[31]	13347095	1			T32	134552		T33	1124		T34	459

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

254528321

1

T32

284119

T33

18293

T34

7455

auto[1]

172578719

1

T32

146446

T33

17675

T34

7233

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

341509457

1

T32

334244

T33

35968

T34

14688

auto[1]

85597583

1

T32

963219

T35

8544

T20

450

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316714934

1

T32

303950

T33

35968

T34

14688

auto[1]

110392106

1

T32

126616

T35

8637

T20

1274

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4920598	1			T32	51031		T33	561		T34	250
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3635309	1			T32	29002		T33	563		T34	209
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1345158	1			T32	14848		T35	97		T25	18
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1681711	1			T32	23058		T35	164		T20	10
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	431782	1			T32	1612		T20	14		T23	7
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1332537	1			T32	15001		T35	100		T20	11
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4920953	1			T32	51089		T33	606		T34	236
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3631486	1			T32	29158		T33	518		T34	223
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1344214	1			T32	14611		T35	134		T20	12
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1684601	1			T32	22987		T35	140		T20	8
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	432239	1			T32	1710		T20	10		T23	2
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1333602	1			T32	14997		T35	131		T20	5
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4915650	1			T32	50780		T33	563		T34	231
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3638769	1			T32	29202		T33	561		T34	228
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1348263	1			T32	15127		T35	121		T20	7
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1681890	1			T32	22446		T35	144		T20	46
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	432661	1			T32	1611		T20	5		T23	5
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1329862	1			T32	15386		T35	116		T20	2
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4921311	1			T32	50579		T33	596		T34	224
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3629384	1			T32	28904		T33	528		T34	235
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1346183	1			T32	14552		T35	108		T20	1
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1684678	1			T32	23610		T35	144		T20	16
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	432166	1			T32	1740		T20	15		T23	1
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1333373	1			T32	15167		T35	128		T20	7
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4937219	1			T32	50683		T33	555		T34	230
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3617043	1			T32	29180		T33	569		T34	229
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1347178	1			T32	15817		T35	152		T20	10
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1680928	1			T32	22638		T35	118		T20	3
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	432159	1			T32	1606		T20	18		T25	9
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1332568	1			T32	14628		T35	125		T20	22
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4920319	1			T32	50493		T33	609		T34	244
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3629691	1			T32	28985		T33	515		T34	215
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1344972	1			T32	15222		T35	130		T20	6
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1685086	1			T32	23113		T35	150		T20	11
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	433429	1			T32	1788		T20	6		T23	5
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1333598	1			T32	14951		T35	142		T20	4
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4930305	1			T32	51453		T33	582		T34	221
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3616996	1			T32	28897		T33	542		T34	238
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1346138	1			T32	15221		T35	128		T20	6
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1683886	1			T32	23044		T35	143		T20	29
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	435598	1			T32	1779		T20	5		T23	1
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1334172	1			T32	14158		T35	144		T20	6
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4923420	1			T32	50838		T33	543		T34	241
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3628603	1			T32	29112		T33	581		T34	218
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1346272	1			T32	15463		T35	124		T20	4
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1686960	1			T32	22935		T35	154		T20	35
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	432695	1			T32	1720		T20	11		T23	2
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1329145	1			T32	14484		T35	121		T20	19
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4911490	1			T32	50339		T33	550		T34	221
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3631669	1			T32	29242		T33	574		T34	238
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1342557	1			T32	14470		T35	168		T20	7
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1693671	1			T32	23609		T35	132		T20	28
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	432896	1			T32	1716		T20	5		T23	4
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1334812	1			T32	15176		T35	124		T20	20
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4925347	1			T32	50710		T33	519		T34	228
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3625840	1			T32	29168		T33	605		T34	231
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1345797	1			T32	15445		T35	114		T20	2
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1682786	1			T32	22298		T35	126		T20	23
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	433307	1			T32	1658		T20	18		T25	6
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1334018	1			T32	15273		T35	138		T20	9
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4930471	1			T32	50675		T33	583		T34	225
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3621339	1			T32	28766		T33	541		T34	234
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1346877	1			T32	15373		T35	136		T20	4
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1684186	1			T32	23543		T35	132		T20	27
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	429556	1			T32	1725		T20	14		T23	3
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1334666	1			T32	14470		T35	160		T20	10
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4922427	1			T32	50373		T33	548		T34	229
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3627623	1			T32	29017		T33	576		T34	230
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1344532	1			T32	15291		T35	118		T20	13
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1681329	1			T32	23289		T35	152		T20	16
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	434372	1			T32	1723		T20	6		T23	4
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1336812	1			T32	14859		T35	119		T20	5
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4928192	1			T32	50557		T33	553		T34	224
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3623002	1			T32	29023		T33	571		T34	235
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1349449	1			T32	15192		T35	122		T25	3
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1679718	1			T32	22811		T35	122		T20	35
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	432164	1			T32	1765		T20	15		T23	2
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1334570	1			T32	15204		T35	154		T25	6
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4914010	1			T32	51220		T33	620		T34	221
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3629305	1			T32	29139		T33	504		T34	238
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1340002	1			T32	15057		T35	132		T23	18
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1693133	1			T32	22354		T35	155		T20	18
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	435831	1			T32	1629		T20	29		T25	2
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1334814	1			T32	15153		T35	140		T20	4
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4919926	1			T32	50693		T33	659		T34	212
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3633593	1			T32	29006		T33	465		T34	247
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1349862	1			T32	14859		T35	114		T20	9
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1680470	1			T32	23126		T35	152		T20	51
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	431760	1			T32	1740		T20	9		T23	5
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1331484	1			T32	15128		T35	123		T20	13
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4927814	1			T32	50149		T33	561		T34	227
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3621922	1			T32	29059		T33	563		T34	232
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1338282	1			T32	14816		T35	167		T20	7
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1687054	1			T32	23188		T35	114		T20	23
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	432936	1			T32	1752		T20	14		T23	8
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1339087	1			T32	15588		T35	134		T20	14
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4930253	1			T32	51027		T33	576		T34	230
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3624494	1			T32	29176		T33	548		T34	229
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1343639	1			T32	14745		T35	151		T20	3
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1684317	1			T32	23150		T35	126		T20	24
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	433326	1			T32	1685		T20	6		T23	6
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1331066	1			T32	14769		T35	126		T20	5
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4917543	1			T32	50323		T33	449		T34	254
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3635848	1			T32	28853		T33	675		T34	205
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1341443	1			T32	14849		T35	138		T20	2
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1690473	1			T32	23303		T35	125		T20	4
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	432606	1			T32	1705		T20	3		T26	370
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1329182	1			T32	15519		T35	122		T20	6
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4922503	1			T32	50762		T33	603		T34	259
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3636478	1			T32	29248		T33	521		T34	200
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1342131	1			T32	15002		T35	146		T20	5
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1686430	1			T32	22914		T35	113		T20	21
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	430930	1			T32	1750		T20	7		T23	3
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1328623	1			T32	14876		T35	138		T20	5
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4922111	1			T32	51021		T33	562		T34	228
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3635385	1			T32	29073		T33	562		T34	231
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1339899	1			T32	15078		T35	175		T20	3
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1686470	1			T32	22754		T35	102		T20	8
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	432009	1			T32	1762		T20	4		T23	3
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1331221	1			T32	14864		T35	142		T20	1
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4921681	1			T32	51007		T33	624		T34	236
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3630881	1			T32	28932		T33	500		T34	223
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1342018	1			T32	15442		T35	125		T23	9
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1688384	1			T32	22252		T35	148		T20	6
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	433888	1			T32	1729		T20	7		T23	3
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1330243	1			T32	15190		T35	172		T20	8
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4920322	1			T32	50516		T33	576		T34	241
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3633394	1			T32	29082		T33	548		T34	218
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1340172	1			T32	15341		T35	181		T20	5
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1687211	1			T32	22894		T35	112		T20	9
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	435529	1			T32	1631		T20	2		T23	2
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1330467	1			T32	15088		T35	88		T20	2
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4938369	1			T32	51338		T33	579		T34	236
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3626066	1			T32	29084		T33	545		T34	223
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1341984	1			T32	15170		T35	120		T20	4
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1681889	1			T32	22418		T35	124		T20	12
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	431817	1			T32	1583		T20	16		T23	1
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1326970	1			T32	14959		T35	192		T20	11
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4925874	1			T32	50717		T33	511		T34	235
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3633617	1			T32	28986		T33	613		T34	224
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1346333	1			T32	15235		T35	125		T20	3
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1684524	1			T32	23138		T35	140		T20	17
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	430911	1			T32	1744		T20	13		T25	10
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1325836	1			T32	14732		T35	124		T20	11
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4925947	1			T32	50131		T33	567		T34	246
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3635321	1			T32	28922		T33	557		T34	213
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1341801	1			T32	15093		T35	100		T20	10
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1686475	1			T32	23288		T35	160		T20	12
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	433703	1			T32	1807		T20	16		T25	25
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1323848	1			T32	15311		T35	144		T20	11
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4913690	1			T32	50932		T33	577		T34	236
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3636086	1			T32	29154		T33	547		T34	223
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1340113	1			T32	14836		T35	151		T20	2
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1693163	1			T32	22943		T35	134		T20	28
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	432814	1			T32	1725		T20	15		T23	1
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1331229	1			T32	14962		T35	134		T20	10
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4924993	1			T32	50759		T33	639		T34	218
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3632703	1			T32	29309		T33	485		T34	241
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1341580	1			T32	15648		T35	142		T20	2
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1684234	1			T32	22325		T35	118		T20	35
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	433789	1			T32	1698		T20	15		T23	3
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1329796	1			T32	14813		T35	106		T20	12
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4925898	1			T32	50973		T33	560		T34	214
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3630364	1			T32	29152		T33	564		T34	245
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1344597	1			T32	14633		T35	112		T20	7
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1688442	1			T32	22803		T35	162		T20	1
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	430748	1			T32	1600		T20	14		T25	22
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1327046	1			T32	15391		T35	125		T20	8
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4936752	1			T32	50875		T33	562		T34	255
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3620029	1			T32	29238		T33	562		T34	204
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1340036	1			T32	15107		T35	117		T20	9
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1687755	1			T32	22434		T35	128		T20	14
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	432370	1			T32	1624		T20	8		T25	21
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1330153	1			T32	15274		T35	184		T20	1
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4927914	1			T32	51260		T33	578		T34	233
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3625428	1			T32	29135		T33	546		T34	226
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1345798	1			T32	15361		T35	104		T20	2
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1685460	1			T32	22215		T35	143		T20	5
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	435610	1			T32	1563		T20	15		T23	3
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1326885	1			T32	15018		T35	140		T20	13
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4926517	1			T32	50748		T33	518		T34	237
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3627973	1			T32	29021		T33	606		T34	222
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1343354	1			T32	15274		T35	158		T20	12
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1688521	1			T32	22575		T35	114		T20	11
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	434511	1			T32	1676		T20	19		T23	2
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1326219	1			T32	15258		T35	130		T20	26
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4937451	1			T32	51626		T33	604		T34	233
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3622156	1			T32	29181		T33	520		T34	226
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1339233	1			T32	15242		T35	136		T20	3
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1685349	1			T32	22645		T35	148		T20	32
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	433094	1			T32	1706		T20	12		T25	7
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1329812	1			T32	14152		T35	132		T20	9

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal