Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[1]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[2]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[3]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[4]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[5]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[6]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[7]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[8]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[9]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[10]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[11]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[12]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[13]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[14]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[15]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[16]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[17]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[18]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[19]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[20]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[21]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[22]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[23]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[24]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[25]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[26]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[27]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[28]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[29]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[30]	13347095	1			T32	134552		T33	1124		T34	459
bins_for_gpio_bits[31]	13347095	1			T32	134552		T33	1124		T34	459

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

254528321

1

T32

284119

T33

18293

T34

7455

auto[1]

172578719

1

T32

146446

T33

17675

T34

7233

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

254519974

1

T32

284091

T33

18293

T34

7455

auto[1]

172587066

1

T32

146474

T33

17675

T34

7233

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7709440	1			T32	86347		T33	561		T34	250
bins_for_gpio_bits[0]	auto[0]	auto[1]	237715	1			T32	2578		T35	26		T26	464
bins_for_gpio_bits[0]	auto[1]	auto[0]	238027	1			T32	2590		T35	26		T26	466
bins_for_gpio_bits[0]	auto[1]	auto[1]	5161913	1			T32	43037		T33	563		T34	209
bins_for_gpio_bits[1]	auto[0]	auto[0]	7711449	1			T32	86027		T33	606		T34	236
bins_for_gpio_bits[1]	auto[0]	auto[1]	238029	1			T32	2648		T35	34		T23	2
bins_for_gpio_bits[1]	auto[1]	auto[0]	238319	1			T32	2660		T35	35		T23	2
bins_for_gpio_bits[1]	auto[1]	auto[1]	5159298	1			T32	43217		T33	518		T34	223
bins_for_gpio_bits[2]	auto[0]	auto[0]	7707422	1			T32	85662		T33	563		T34	231
bins_for_gpio_bits[2]	auto[0]	auto[1]	238069	1			T32	2681		T35	32		T25	2
bins_for_gpio_bits[2]	auto[1]	auto[0]	238381	1			T32	2691		T35	32		T23	1
bins_for_gpio_bits[2]	auto[1]	auto[1]	5163223	1			T32	43518		T33	561		T34	228
bins_for_gpio_bits[3]	auto[0]	auto[0]	7714223	1			T32	86096		T33	596		T34	224
bins_for_gpio_bits[3]	auto[0]	auto[1]	237651	1			T32	2635		T35	31		T23	2
bins_for_gpio_bits[3]	auto[1]	auto[0]	237949	1			T32	2645		T35	31		T23	2
bins_for_gpio_bits[3]	auto[1]	auto[1]	5157272	1			T32	43176		T33	528		T34	235
bins_for_gpio_bits[4]	auto[0]	auto[0]	7727169	1			T32	86483		T33	555		T34	230
bins_for_gpio_bits[4]	auto[0]	auto[1]	237895	1			T32	2647		T35	34		T25	1
bins_for_gpio_bits[4]	auto[1]	auto[0]	238156	1			T32	2655		T35	35		T25	1
bins_for_gpio_bits[4]	auto[1]	auto[1]	5143875	1			T32	42767		T33	569		T34	229
bins_for_gpio_bits[5]	auto[0]	auto[0]	7712490	1			T32	86222		T33	609		T34	244
bins_for_gpio_bits[5]	auto[0]	auto[1]	237615	1			T32	2594		T35	30		T23	3
bins_for_gpio_bits[5]	auto[1]	auto[0]	237887	1			T32	2606		T35	30		T23	3
bins_for_gpio_bits[5]	auto[1]	auto[1]	5159103	1			T32	43130		T33	515		T34	215
bins_for_gpio_bits[6]	auto[0]	auto[0]	7721856	1			T32	87150		T33	582		T34	221
bins_for_gpio_bits[6]	auto[0]	auto[1]	238244	1			T32	2559		T35	40		T20	1
bins_for_gpio_bits[6]	auto[1]	auto[0]	238473	1			T32	2568		T35	40		T23	2
bins_for_gpio_bits[6]	auto[1]	auto[1]	5148522	1			T32	42275		T33	542		T34	238
bins_for_gpio_bits[7]	auto[0]	auto[0]	7718312	1			T32	86591		T33	543		T34	241
bins_for_gpio_bits[7]	auto[0]	auto[1]	238073	1			T32	2636		T35	31		T23	2
bins_for_gpio_bits[7]	auto[1]	auto[0]	238340	1			T32	2645		T35	32		T23	2
bins_for_gpio_bits[7]	auto[1]	auto[1]	5152370	1			T32	42680		T33	581		T34	218
bins_for_gpio_bits[8]	auto[0]	auto[0]	7708811	1			T32	85720		T33	550		T34	221
bins_for_gpio_bits[8]	auto[0]	auto[1]	238713	1			T32	2693		T35	33		T20	2
bins_for_gpio_bits[8]	auto[1]	auto[0]	238907	1			T32	2698		T35	33		T20	1
bins_for_gpio_bits[8]	auto[1]	auto[1]	5160664	1			T32	43441		T33	574		T34	238
bins_for_gpio_bits[9]	auto[0]	auto[0]	7716283	1			T32	85830		T33	519		T34	228
bins_for_gpio_bits[9]	auto[0]	auto[1]	237341	1			T32	2612		T35	30		T23	1
bins_for_gpio_bits[9]	auto[1]	auto[0]	237647	1			T32	2623		T35	30		T23	2
bins_for_gpio_bits[9]	auto[1]	auto[1]	5155824	1			T32	43487		T33	605		T34	231
bins_for_gpio_bits[10]	auto[0]	auto[0]	7722720	1			T32	86958		T33	583		T34	225
bins_for_gpio_bits[10]	auto[0]	auto[1]	238605	1			T32	2625		T35	37		T23	1
bins_for_gpio_bits[10]	auto[1]	auto[0]	238814	1			T32	2633		T35	37		T23	2
bins_for_gpio_bits[10]	auto[1]	auto[1]	5146956	1			T32	42336		T33	541		T34	234
bins_for_gpio_bits[11]	auto[0]	auto[0]	7710127	1			T32	86325		T33	548		T34	229
bins_for_gpio_bits[11]	auto[0]	auto[1]	237950	1			T32	2620		T35	33		T25	2
bins_for_gpio_bits[11]	auto[1]	auto[0]	238161	1			T32	2628		T35	34		T25	2
bins_for_gpio_bits[11]	auto[1]	auto[1]	5160857	1			T32	42979		T33	576		T34	230
bins_for_gpio_bits[12]	auto[0]	auto[0]	7718627	1			T32	85863		T33	553		T34	224
bins_for_gpio_bits[12]	auto[0]	auto[1]	238469	1			T32	2690		T35	37		T25	1
bins_for_gpio_bits[12]	auto[1]	auto[0]	238732	1			T32	2697		T35	37		T25	1
bins_for_gpio_bits[12]	auto[1]	auto[1]	5151267	1			T32	43302		T33	571		T34	235
bins_for_gpio_bits[13]	auto[0]	auto[0]	7708912	1			T32	86042		T33	620		T34	221
bins_for_gpio_bits[13]	auto[0]	auto[1]	237921	1			T32	2579		T35	35		T23	2
bins_for_gpio_bits[13]	auto[1]	auto[0]	238233	1			T32	2589		T35	35		T23	2
bins_for_gpio_bits[13]	auto[1]	auto[1]	5162029	1			T32	43342		T33	504		T34	238
bins_for_gpio_bits[14]	auto[0]	auto[0]	7712018	1			T32	86029		T33	659		T34	212
bins_for_gpio_bits[14]	auto[0]	auto[1]	237985	1			T32	2640		T35	26		T20	1
bins_for_gpio_bits[14]	auto[1]	auto[0]	238240	1			T32	2649		T35	27		T23	3
bins_for_gpio_bits[14]	auto[1]	auto[1]	5158852	1			T32	43234		T33	465		T34	247
bins_for_gpio_bits[15]	auto[0]	auto[0]	7714758	1			T32	85428		T33	561		T34	227
bins_for_gpio_bits[15]	auto[0]	auto[1]	238115	1			T32	2718		T35	36		T20	1
bins_for_gpio_bits[15]	auto[1]	auto[0]	238392	1			T32	2725		T35	36		T23	1
bins_for_gpio_bits[15]	auto[1]	auto[1]	5155830	1			T32	43681		T33	563		T34	232
bins_for_gpio_bits[16]	auto[0]	auto[0]	7719699	1			T32	86274		T33	576		T34	230
bins_for_gpio_bits[16]	auto[0]	auto[1]	238219	1			T32	2641		T35	37		T23	2
bins_for_gpio_bits[16]	auto[1]	auto[0]	238510	1			T32	2648		T35	37		T23	3
bins_for_gpio_bits[16]	auto[1]	auto[1]	5150667	1			T32	42989		T33	548		T34	229
bins_for_gpio_bits[17]	auto[0]	auto[0]	7711407	1			T32	85762		T33	449		T34	254
bins_for_gpio_bits[17]	auto[0]	auto[1]	237776	1			T32	2708		T35	32		T26	454
bins_for_gpio_bits[17]	auto[1]	auto[0]	238052	1			T32	2713		T35	32		T26	456
bins_for_gpio_bits[17]	auto[1]	auto[1]	5159860	1			T32	43369		T33	675		T34	205
bins_for_gpio_bits[18]	auto[0]	auto[0]	7712137	1			T32	86054		T33	603		T34	259
bins_for_gpio_bits[18]	auto[0]	auto[1]	238701	1			T32	2618		T35	39		T25	4
bins_for_gpio_bits[18]	auto[1]	auto[0]	238927	1			T32	2624		T35	39		T25	4
bins_for_gpio_bits[18]	auto[1]	auto[1]	5157330	1			T32	43256		T33	521		T34	200
bins_for_gpio_bits[19]	auto[0]	auto[0]	7709460	1			T32	86216		T33	562		T34	228
bins_for_gpio_bits[19]	auto[0]	auto[1]	238779	1			T32	2632		T35	35		T23	1
bins_for_gpio_bits[19]	auto[1]	auto[0]	239020	1			T32	2637		T35	35		T23	2
bins_for_gpio_bits[19]	auto[1]	auto[1]	5159836	1			T32	43067		T33	562		T34	231
bins_for_gpio_bits[20]	auto[0]	auto[0]	7713540	1			T32	86080		T33	624		T34	236
bins_for_gpio_bits[20]	auto[0]	auto[1]	238297	1			T32	2615		T35	35		T23	2
bins_for_gpio_bits[20]	auto[1]	auto[0]	238543	1			T32	2621		T35	35		T23	2
bins_for_gpio_bits[20]	auto[1]	auto[1]	5156715	1			T32	43236		T33	500		T34	223
bins_for_gpio_bits[21]	auto[0]	auto[0]	7709255	1			T32	86078		T33	576		T34	241
bins_for_gpio_bits[21]	auto[0]	auto[1]	238226	1			T32	2666		T35	26		T23	2
bins_for_gpio_bits[21]	auto[1]	auto[0]	238450	1			T32	2673		T35	26		T23	2
bins_for_gpio_bits[21]	auto[1]	auto[1]	5161164	1			T32	43135		T33	548		T34	218
bins_for_gpio_bits[22]	auto[0]	auto[0]	7724009	1			T32	86342		T33	579		T34	236
bins_for_gpio_bits[22]	auto[0]	auto[1]	237988	1			T32	2574		T35	39		T23	2
bins_for_gpio_bits[22]	auto[1]	auto[0]	238233	1			T32	2584		T35	39		T23	2
bins_for_gpio_bits[22]	auto[1]	auto[1]	5146865	1			T32	43052		T33	545		T34	223
bins_for_gpio_bits[23]	auto[0]	auto[0]	7718132	1			T32	86463		T33	511		T34	235
bins_for_gpio_bits[23]	auto[0]	auto[1]	238330	1			T32	2610		T35	30		T23	1
bins_for_gpio_bits[23]	auto[1]	auto[0]	238599	1			T32	2627		T35	30		T23	1
bins_for_gpio_bits[23]	auto[1]	auto[1]	5152034	1			T32	42852		T33	613		T34	224
bins_for_gpio_bits[24]	auto[0]	auto[0]	7716263	1			T32	85802		T33	567		T34	246
bins_for_gpio_bits[24]	auto[0]	auto[1]	237703	1			T32	2701		T35	35		T25	8
bins_for_gpio_bits[24]	auto[1]	auto[0]	237960	1			T32	2710		T35	35		T25	8
bins_for_gpio_bits[24]	auto[1]	auto[1]	5155169	1			T32	43339		T33	557		T34	213
bins_for_gpio_bits[25]	auto[0]	auto[0]	7708402	1			T32	86056		T33	577		T34	236
bins_for_gpio_bits[25]	auto[0]	auto[1]	238302	1			T32	2646		T35	36		T25	1
bins_for_gpio_bits[25]	auto[1]	auto[0]	238564	1			T32	2655		T35	36		T25	1
bins_for_gpio_bits[25]	auto[1]	auto[1]	5161827	1			T32	43195		T33	547		T34	223
bins_for_gpio_bits[26]	auto[0]	auto[0]	7712059	1			T32	86088		T33	639		T34	218
bins_for_gpio_bits[26]	auto[0]	auto[1]	238504	1			T32	2634		T35	32		T23	1
bins_for_gpio_bits[26]	auto[1]	auto[0]	238748	1			T32	2644		T35	32		T23	2
bins_for_gpio_bits[26]	auto[1]	auto[1]	5157784	1			T32	43186		T33	485		T34	241
bins_for_gpio_bits[27]	auto[0]	auto[0]	7720216	1			T32	85676		T33	560		T34	214
bins_for_gpio_bits[27]	auto[0]	auto[1]	238472	1			T32	2723		T35	32		T25	2
bins_for_gpio_bits[27]	auto[1]	auto[0]	238721	1			T32	2733		T35	33		T25	2
bins_for_gpio_bits[27]	auto[1]	auto[1]	5149686	1			T32	43420		T33	564		T34	245
bins_for_gpio_bits[28]	auto[0]	auto[0]	7726177	1			T32	85736		T33	562		T34	255
bins_for_gpio_bits[28]	auto[0]	auto[1]	238112	1			T32	2673		T35	38		T25	5
bins_for_gpio_bits[28]	auto[1]	auto[0]	238366	1			T32	2680		T35	38		T23	1
bins_for_gpio_bits[28]	auto[1]	auto[1]	5144440	1			T32	43463		T33	562		T34	204
bins_for_gpio_bits[29]	auto[0]	auto[0]	7721067	1			T32	86232		T33	578		T34	233
bins_for_gpio_bits[29]	auto[0]	auto[1]	237848	1			T32	2594		T35	30		T23	2
bins_for_gpio_bits[29]	auto[1]	auto[0]	238105	1			T32	2604		T35	30		T23	2
bins_for_gpio_bits[29]	auto[1]	auto[1]	5150075	1			T32	43122		T33	546		T34	226
bins_for_gpio_bits[30]	auto[0]	auto[0]	7720268	1			T32	85960		T33	518		T34	237
bins_for_gpio_bits[30]	auto[0]	auto[1]	237823	1			T32	2629		T35	34		T20	1
bins_for_gpio_bits[30]	auto[1]	auto[0]	238124	1			T32	2637		T35	34		T23	1
bins_for_gpio_bits[30]	auto[1]	auto[1]	5150880	1			T32	43326		T33	606		T34	222
bins_for_gpio_bits[31]	auto[0]	auto[0]	7723886	1			T32	86954		T33	604		T34	233
bins_for_gpio_bits[31]	auto[0]	auto[1]	237910	1			T32	2553		T35	30		T26	474
bins_for_gpio_bits[31]	auto[1]	auto[0]	238147	1			T32	2559		T35	30		T26	475
bins_for_gpio_bits[31]	auto[1]	auto[1]	5147152	1			T32	42486		T33	520		T34	226