Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7805085 |
1 |
|
|
T32 |
76869 |
|
T33 |
1124 |
|
T34 |
292 |
| auto[1] |
5767421 |
1 |
|
|
T32 |
58866 |
|
T34 |
295 |
|
T20 |
48 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12847173 |
1 |
|
|
T32 |
128194 |
|
T33 |
1124 |
|
T34 |
500 |
| auto[1] |
725333 |
1 |
|
|
T32 |
7541 |
|
T34 |
87 |
|
T26 |
2113 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7844393 |
1 |
|
|
T32 |
76448 |
|
T33 |
1124 |
|
T34 |
179 |
| auto[1] |
5728113 |
1 |
|
|
T32 |
59287 |
|
T34 |
408 |
|
T20 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2498886 |
1 |
|
|
T32 |
26735 |
|
T34 |
167 |
|
T20 |
6 |
| auto[1] |
auto[0] |
auto[1] |
362621 |
1 |
|
|
T32 |
3847 |
|
T34 |
48 |
|
T26 |
1114 |
| auto[1] |
auto[1] |
auto[0] |
2503894 |
1 |
|
|
T32 |
25011 |
|
T34 |
154 |
|
T20 |
4 |
| auto[1] |
auto[1] |
auto[1] |
362712 |
1 |
|
|
T32 |
3694 |
|
T34 |
39 |
|
T26 |
999 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7819931 |
1 |
|
|
T32 |
74749 |
|
T33 |
1124 |
|
T34 |
206 |
| auto[1] |
5752575 |
1 |
|
|
T32 |
60986 |
|
T34 |
381 |
|
T20 |
50 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12837303 |
1 |
|
|
T32 |
127953 |
|
T33 |
1124 |
|
T34 |
528 |
| auto[1] |
735203 |
1 |
|
|
T32 |
7782 |
|
T34 |
59 |
|
T20 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7788169 |
1 |
|
|
T32 |
74128 |
|
T33 |
1124 |
|
T34 |
274 |
| auto[1] |
5784337 |
1 |
|
|
T32 |
61607 |
|
T34 |
313 |
|
T20 |
42 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2521829 |
1 |
|
|
T32 |
26258 |
|
T34 |
85 |
|
T20 |
19 |
| auto[1] |
auto[0] |
auto[1] |
367651 |
1 |
|
|
T32 |
3876 |
|
T34 |
21 |
|
T26 |
1021 |
| auto[1] |
auto[1] |
auto[0] |
2527305 |
1 |
|
|
T32 |
27567 |
|
T34 |
169 |
|
T20 |
21 |
| auto[1] |
auto[1] |
auto[1] |
367552 |
1 |
|
|
T32 |
3906 |
|
T34 |
38 |
|
T20 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7837736 |
1 |
|
|
T32 |
77149 |
|
T33 |
1124 |
|
T34 |
365 |
| auto[1] |
5734770 |
1 |
|
|
T32 |
58586 |
|
T34 |
222 |
|
T20 |
50 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12847938 |
1 |
|
|
T32 |
128339 |
|
T33 |
1124 |
|
T34 |
502 |
| auto[1] |
724568 |
1 |
|
|
T32 |
7396 |
|
T34 |
85 |
|
T20 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7853599 |
1 |
|
|
T32 |
76314 |
|
T33 |
1124 |
|
T34 |
180 |
| auto[1] |
5718907 |
1 |
|
|
T32 |
59421 |
|
T34 |
407 |
|
T20 |
17 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2503706 |
1 |
|
|
T32 |
26763 |
|
T34 |
192 |
|
T20 |
3 |
| auto[1] |
auto[0] |
auto[1] |
364037 |
1 |
|
|
T32 |
3906 |
|
T34 |
50 |
|
T26 |
1345 |
| auto[1] |
auto[1] |
auto[0] |
2490633 |
1 |
|
|
T32 |
25262 |
|
T34 |
130 |
|
T20 |
13 |
| auto[1] |
auto[1] |
auto[1] |
360531 |
1 |
|
|
T32 |
3490 |
|
T34 |
35 |
|
T20 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7842942 |
1 |
|
|
T32 |
76349 |
|
T33 |
1124 |
|
T34 |
389 |
| auto[1] |
5729564 |
1 |
|
|
T32 |
59386 |
|
T34 |
198 |
|
T20 |
46 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12842520 |
1 |
|
|
T32 |
128195 |
|
T33 |
1124 |
|
T34 |
524 |
| auto[1] |
729986 |
1 |
|
|
T32 |
7540 |
|
T34 |
63 |
|
T20 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7824046 |
1 |
|
|
T32 |
76454 |
|
T33 |
1124 |
|
T34 |
285 |
| auto[1] |
5748460 |
1 |
|
|
T32 |
59281 |
|
T34 |
302 |
|
T20 |
26 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2532125 |
1 |
|
|
T32 |
26393 |
|
T34 |
168 |
|
T20 |
10 |
| auto[1] |
auto[0] |
auto[1] |
368220 |
1 |
|
|
T32 |
3759 |
|
T34 |
42 |
|
T26 |
1141 |
| auto[1] |
auto[1] |
auto[0] |
2486349 |
1 |
|
|
T32 |
25348 |
|
T34 |
71 |
|
T20 |
15 |
| auto[1] |
auto[1] |
auto[1] |
361766 |
1 |
|
|
T32 |
3781 |
|
T34 |
21 |
|
T20 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7856211 |
1 |
|
|
T32 |
74274 |
|
T33 |
1124 |
|
T34 |
190 |
| auto[1] |
5716295 |
1 |
|
|
T32 |
61461 |
|
T34 |
397 |
|
T20 |
41 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12847261 |
1 |
|
|
T32 |
128019 |
|
T33 |
1124 |
|
T34 |
548 |
| auto[1] |
725245 |
1 |
|
|
T32 |
7716 |
|
T34 |
39 |
|
T20 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7840725 |
1 |
|
|
T32 |
75393 |
|
T33 |
1124 |
|
T34 |
412 |
| auto[1] |
5731781 |
1 |
|
|
T32 |
60342 |
|
T34 |
175 |
|
T20 |
37 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2527335 |
1 |
|
|
T32 |
25504 |
|
T34 |
55 |
|
T20 |
21 |
| auto[1] |
auto[0] |
auto[1] |
367097 |
1 |
|
|
T32 |
3710 |
|
T34 |
17 |
|
T20 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2479201 |
1 |
|
|
T32 |
27122 |
|
T34 |
81 |
|
T20 |
15 |
| auto[1] |
auto[1] |
auto[1] |
358148 |
1 |
|
|
T32 |
4006 |
|
T34 |
22 |
|
T26 |
1020 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7771721 |
1 |
|
|
T32 |
75187 |
|
T33 |
1124 |
|
T34 |
304 |
| auto[1] |
5800785 |
1 |
|
|
T32 |
60548 |
|
T34 |
283 |
|
T20 |
17 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12841052 |
1 |
|
|
T32 |
128293 |
|
T33 |
1124 |
|
T34 |
504 |
| auto[1] |
731454 |
1 |
|
|
T32 |
7442 |
|
T34 |
83 |
|
T26 |
2429 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7810132 |
1 |
|
|
T32 |
76193 |
|
T33 |
1124 |
|
T34 |
158 |
| auto[1] |
5762374 |
1 |
|
|
T32 |
59542 |
|
T34 |
429 |
|
T20 |
21 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2506763 |
1 |
|
|
T32 |
25355 |
|
T34 |
178 |
|
T20 |
17 |
| auto[1] |
auto[0] |
auto[1] |
363144 |
1 |
|
|
T32 |
3606 |
|
T34 |
43 |
|
T26 |
1352 |
| auto[1] |
auto[1] |
auto[0] |
2524157 |
1 |
|
|
T32 |
26745 |
|
T34 |
168 |
|
T20 |
4 |
| auto[1] |
auto[1] |
auto[1] |
368310 |
1 |
|
|
T32 |
3836 |
|
T34 |
40 |
|
T26 |
1077 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7839206 |
1 |
|
|
T32 |
73800 |
|
T33 |
1124 |
|
T34 |
266 |
| auto[1] |
5733300 |
1 |
|
|
T32 |
61935 |
|
T34 |
321 |
|
T20 |
30 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12842860 |
1 |
|
|
T32 |
127831 |
|
T33 |
1124 |
|
T34 |
508 |
| auto[1] |
729646 |
1 |
|
|
T32 |
7904 |
|
T34 |
79 |
|
T26 |
2335 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7820372 |
1 |
|
|
T32 |
74008 |
|
T33 |
1124 |
|
T34 |
201 |
| auto[1] |
5752134 |
1 |
|
|
T32 |
61727 |
|
T34 |
386 |
|
T20 |
24 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2529374 |
1 |
|
|
T32 |
26335 |
|
T34 |
124 |
|
T20 |
13 |
| auto[1] |
auto[0] |
auto[1] |
367588 |
1 |
|
|
T32 |
3763 |
|
T34 |
33 |
|
T26 |
1341 |
| auto[1] |
auto[1] |
auto[0] |
2493114 |
1 |
|
|
T32 |
27488 |
|
T34 |
183 |
|
T20 |
11 |
| auto[1] |
auto[1] |
auto[1] |
362058 |
1 |
|
|
T32 |
4141 |
|
T34 |
46 |
|
T26 |
994 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7828944 |
1 |
|
|
T32 |
74504 |
|
T33 |
1124 |
|
T34 |
301 |
| auto[1] |
5743562 |
1 |
|
|
T32 |
61231 |
|
T34 |
286 |
|
T20 |
51 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12842360 |
1 |
|
|
T32 |
128214 |
|
T33 |
1124 |
|
T34 |
535 |
| auto[1] |
730146 |
1 |
|
|
T32 |
7521 |
|
T34 |
52 |
|
T20 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7819850 |
1 |
|
|
T32 |
76163 |
|
T33 |
1124 |
|
T34 |
331 |
| auto[1] |
5752656 |
1 |
|
|
T32 |
59572 |
|
T34 |
256 |
|
T20 |
28 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2524551 |
1 |
|
|
T32 |
25326 |
|
T34 |
101 |
|
T20 |
7 |
| auto[1] |
auto[0] |
auto[1] |
367611 |
1 |
|
|
T32 |
3565 |
|
T34 |
25 |
|
T26 |
1044 |
| auto[1] |
auto[1] |
auto[0] |
2497959 |
1 |
|
|
T32 |
26725 |
|
T34 |
103 |
|
T20 |
20 |
| auto[1] |
auto[1] |
auto[1] |
362535 |
1 |
|
|
T32 |
3956 |
|
T34 |
27 |
|
T20 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7840980 |
1 |
|
|
T32 |
76067 |
|
T33 |
1124 |
|
T34 |
262 |
| auto[1] |
5731526 |
1 |
|
|
T32 |
59668 |
|
T34 |
325 |
|
T20 |
46 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12844469 |
1 |
|
|
T32 |
127715 |
|
T33 |
1124 |
|
T34 |
519 |
| auto[1] |
728037 |
1 |
|
|
T32 |
8020 |
|
T34 |
68 |
|
T20 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7825022 |
1 |
|
|
T32 |
72910 |
|
T33 |
1124 |
|
T34 |
274 |
| auto[1] |
5747484 |
1 |
|
|
T32 |
62825 |
|
T34 |
313 |
|
T20 |
30 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2525353 |
1 |
|
|
T32 |
28401 |
|
T34 |
112 |
|
T20 |
12 |
| auto[1] |
auto[0] |
auto[1] |
366852 |
1 |
|
|
T32 |
4112 |
|
T34 |
29 |
|
T20 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2494094 |
1 |
|
|
T32 |
26404 |
|
T34 |
133 |
|
T20 |
15 |
| auto[1] |
auto[1] |
auto[1] |
361185 |
1 |
|
|
T32 |
3908 |
|
T34 |
39 |
|
T20 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7787832 |
1 |
|
|
T32 |
75169 |
|
T33 |
1124 |
|
T34 |
381 |
| auto[1] |
5784674 |
1 |
|
|
T32 |
60566 |
|
T34 |
206 |
|
T20 |
46 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12844404 |
1 |
|
|
T32 |
127835 |
|
T33 |
1124 |
|
T34 |
512 |
| auto[1] |
728102 |
1 |
|
|
T32 |
7900 |
|
T34 |
75 |
|
T20 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7833945 |
1 |
|
|
T32 |
74365 |
|
T33 |
1124 |
|
T34 |
216 |
| auto[1] |
5738561 |
1 |
|
|
T32 |
61370 |
|
T34 |
371 |
|
T20 |
43 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2502675 |
1 |
|
|
T32 |
26834 |
|
T34 |
186 |
|
T20 |
21 |
| auto[1] |
auto[0] |
auto[1] |
362718 |
1 |
|
|
T32 |
3865 |
|
T34 |
43 |
|
T26 |
1155 |
| auto[1] |
auto[1] |
auto[0] |
2507784 |
1 |
|
|
T32 |
26636 |
|
T34 |
110 |
|
T20 |
21 |
| auto[1] |
auto[1] |
auto[1] |
365384 |
1 |
|
|
T32 |
4035 |
|
T34 |
32 |
|
T20 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7835566 |
1 |
|
|
T32 |
75082 |
|
T33 |
1124 |
|
T34 |
133 |
| auto[1] |
5736940 |
1 |
|
|
T32 |
60653 |
|
T34 |
454 |
|
T20 |
40 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12841112 |
1 |
|
|
T32 |
128532 |
|
T33 |
1124 |
|
T34 |
524 |
| auto[1] |
731394 |
1 |
|
|
T32 |
7203 |
|
T34 |
63 |
|
T20 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7821413 |
1 |
|
|
T32 |
79216 |
|
T33 |
1124 |
|
T34 |
232 |
| auto[1] |
5751093 |
1 |
|
|
T32 |
56519 |
|
T34 |
355 |
|
T20 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2518433 |
1 |
|
|
T32 |
25019 |
|
T34 |
85 |
|
T20 |
13 |
| auto[1] |
auto[0] |
auto[1] |
367157 |
1 |
|
|
T32 |
3684 |
|
T34 |
18 |
|
T20 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2501266 |
1 |
|
|
T32 |
24297 |
|
T34 |
207 |
|
T20 |
1 |
| auto[1] |
auto[1] |
auto[1] |
364237 |
1 |
|
|
T32 |
3519 |
|
T34 |
45 |
|
T26 |
1078 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7815978 |
1 |
|
|
T32 |
77306 |
|
T33 |
1124 |
|
T34 |
296 |
| auto[1] |
5756528 |
1 |
|
|
T32 |
58429 |
|
T34 |
291 |
|
T20 |
29 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12846080 |
1 |
|
|
T32 |
128008 |
|
T33 |
1124 |
|
T34 |
550 |
| auto[1] |
726426 |
1 |
|
|
T32 |
7727 |
|
T34 |
37 |
|
T20 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7835784 |
1 |
|
|
T32 |
75227 |
|
T33 |
1124 |
|
T34 |
402 |
| auto[1] |
5736722 |
1 |
|
|
T32 |
60508 |
|
T34 |
185 |
|
T20 |
38 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2491732 |
1 |
|
|
T32 |
26242 |
|
T34 |
65 |
|
T20 |
29 |
| auto[1] |
auto[0] |
auto[1] |
360830 |
1 |
|
|
T32 |
3807 |
|
T34 |
11 |
|
T20 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2518564 |
1 |
|
|
T32 |
26539 |
|
T34 |
83 |
|
T20 |
8 |
| auto[1] |
auto[1] |
auto[1] |
365596 |
1 |
|
|
T32 |
3920 |
|
T34 |
26 |
|
T26 |
1132 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7804720 |
1 |
|
|
T32 |
75475 |
|
T33 |
1124 |
|
T34 |
369 |
| auto[1] |
5767786 |
1 |
|
|
T32 |
60260 |
|
T34 |
218 |
|
T20 |
51 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12840673 |
1 |
|
|
T32 |
128039 |
|
T33 |
1124 |
|
T34 |
525 |
| auto[1] |
731833 |
1 |
|
|
T32 |
7696 |
|
T34 |
62 |
|
T20 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7797827 |
1 |
|
|
T32 |
75272 |
|
T33 |
1124 |
|
T34 |
269 |
| auto[1] |
5774679 |
1 |
|
|
T32 |
60463 |
|
T34 |
318 |
|
T20 |
40 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2526982 |
1 |
|
|
T32 |
26319 |
|
T34 |
203 |
|
T20 |
9 |
| auto[1] |
auto[0] |
auto[1] |
367557 |
1 |
|
|
T32 |
3814 |
|
T34 |
49 |
|
T20 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2515864 |
1 |
|
|
T32 |
26448 |
|
T34 |
53 |
|
T20 |
29 |
| auto[1] |
auto[1] |
auto[1] |
364276 |
1 |
|
|
T32 |
3882 |
|
T34 |
13 |
|
T20 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7843368 |
1 |
|
|
T32 |
75556 |
|
T33 |
1124 |
|
T34 |
384 |
| auto[1] |
5729138 |
1 |
|
|
T32 |
60179 |
|
T34 |
203 |
|
T20 |
39 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12843519 |
1 |
|
|
T32 |
128064 |
|
T33 |
1124 |
|
T34 |
552 |
| auto[1] |
728987 |
1 |
|
|
T32 |
7671 |
|
T34 |
35 |
|
T26 |
2347 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7826775 |
1 |
|
|
T32 |
74453 |
|
T33 |
1124 |
|
T34 |
415 |
| auto[1] |
5745731 |
1 |
|
|
T32 |
61282 |
|
T34 |
172 |
|
T20 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2525441 |
1 |
|
|
T32 |
27127 |
|
T34 |
90 |
|
T20 |
9 |
| auto[1] |
auto[0] |
auto[1] |
367065 |
1 |
|
|
T32 |
3810 |
|
T34 |
24 |
|
T26 |
1202 |
| auto[1] |
auto[1] |
auto[0] |
2491303 |
1 |
|
|
T32 |
26484 |
|
T34 |
47 |
|
T20 |
6 |
| auto[1] |
auto[1] |
auto[1] |
361922 |
1 |
|
|
T32 |
3861 |
|
T34 |
11 |
|
T26 |
1145 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7831168 |
1 |
|
|
T32 |
73489 |
|
T33 |
1124 |
|
T34 |
283 |
| auto[1] |
5741338 |
1 |
|
|
T32 |
62246 |
|
T34 |
304 |
|
T20 |
33 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12839122 |
1 |
|
|
T32 |
128172 |
|
T33 |
1124 |
|
T34 |
520 |
| auto[1] |
733384 |
1 |
|
|
T32 |
7563 |
|
T34 |
67 |
|
T20 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7799279 |
1 |
|
|
T32 |
75457 |
|
T33 |
1124 |
|
T34 |
208 |
| auto[1] |
5773227 |
1 |
|
|
T32 |
60278 |
|
T34 |
379 |
|
T20 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2531305 |
1 |
|
|
T32 |
26687 |
|
T34 |
157 |
|
T20 |
6 |
| auto[1] |
auto[0] |
auto[1] |
368737 |
1 |
|
|
T32 |
3767 |
|
T34 |
34 |
|
T20 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2508538 |
1 |
|
|
T32 |
26028 |
|
T34 |
155 |
|
T20 |
11 |
| auto[1] |
auto[1] |
auto[1] |
364647 |
1 |
|
|
T32 |
3796 |
|
T34 |
33 |
|
T26 |
1287 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7795362 |
1 |
|
|
T32 |
75740 |
|
T33 |
1124 |
|
T34 |
159 |
| auto[1] |
5777144 |
1 |
|
|
T32 |
59995 |
|
T34 |
428 |
|
T20 |
56 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12840031 |
1 |
|
|
T32 |
128307 |
|
T33 |
1124 |
|
T34 |
527 |
| auto[1] |
732475 |
1 |
|
|
T32 |
7428 |
|
T34 |
60 |
|
T20 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7795177 |
1 |
|
|
T32 |
77290 |
|
T33 |
1124 |
|
T34 |
300 |
| auto[1] |
5777329 |
1 |
|
|
T32 |
58445 |
|
T34 |
287 |
|
T20 |
29 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2525126 |
1 |
|
|
T32 |
25985 |
|
T34 |
28 |
|
T20 |
11 |
| auto[1] |
auto[0] |
auto[1] |
366593 |
1 |
|
|
T32 |
3768 |
|
T34 |
5 |
|
T20 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2519728 |
1 |
|
|
T32 |
25032 |
|
T34 |
199 |
|
T20 |
16 |
| auto[1] |
auto[1] |
auto[1] |
365882 |
1 |
|
|
T32 |
3660 |
|
T34 |
55 |
|
T20 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7804765 |
1 |
|
|
T32 |
75141 |
|
T33 |
1124 |
|
T34 |
182 |
| auto[1] |
5767741 |
1 |
|
|
T32 |
60594 |
|
T34 |
405 |
|
T20 |
33 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12849839 |
1 |
|
|
T32 |
128091 |
|
T33 |
1124 |
|
T34 |
535 |
| auto[1] |
722667 |
1 |
|
|
T32 |
7644 |
|
T34 |
52 |
|
T20 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7863663 |
1 |
|
|
T32 |
75408 |
|
T33 |
1124 |
|
T34 |
332 |
| auto[1] |
5708843 |
1 |
|
|
T32 |
60327 |
|
T34 |
255 |
|
T20 |
36 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2481881 |
1 |
|
|
T32 |
26297 |
|
T34 |
37 |
|
T20 |
21 |
| auto[1] |
auto[0] |
auto[1] |
360881 |
1 |
|
|
T32 |
3859 |
|
T34 |
12 |
|
T20 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2504295 |
1 |
|
|
T32 |
26386 |
|
T34 |
166 |
|
T20 |
13 |
| auto[1] |
auto[1] |
auto[1] |
361786 |
1 |
|
|
T32 |
3785 |
|
T34 |
40 |
|
T20 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7803293 |
1 |
|
|
T32 |
77092 |
|
T33 |
1124 |
|
T34 |
302 |
| auto[1] |
5769213 |
1 |
|
|
T32 |
58643 |
|
T34 |
285 |
|
T20 |
23 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12844352 |
1 |
|
|
T32 |
127872 |
|
T33 |
1124 |
|
T34 |
541 |
| auto[1] |
728154 |
1 |
|
|
T32 |
7863 |
|
T34 |
46 |
|
T20 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7823364 |
1 |
|
|
T32 |
73840 |
|
T33 |
1124 |
|
T34 |
361 |
| auto[1] |
5749142 |
1 |
|
|
T32 |
61895 |
|
T34 |
226 |
|
T20 |
17 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2507211 |
1 |
|
|
T32 |
28529 |
|
T34 |
87 |
|
T20 |
9 |
| auto[1] |
auto[0] |
auto[1] |
363069 |
1 |
|
|
T32 |
4209 |
|
T34 |
18 |
|
T20 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2513777 |
1 |
|
|
T32 |
25503 |
|
T34 |
93 |
|
T20 |
6 |
| auto[1] |
auto[1] |
auto[1] |
365085 |
1 |
|
|
T32 |
3654 |
|
T34 |
28 |
|
T20 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7794578 |
1 |
|
|
T32 |
75270 |
|
T33 |
1124 |
|
T34 |
266 |
| auto[1] |
5777928 |
1 |
|
|
T32 |
60465 |
|
T34 |
321 |
|
T20 |
56 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12840584 |
1 |
|
|
T32 |
128318 |
|
T33 |
1124 |
|
T34 |
511 |
| auto[1] |
731922 |
1 |
|
|
T32 |
7417 |
|
T34 |
76 |
|
T20 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7797524 |
1 |
|
|
T32 |
76384 |
|
T33 |
1124 |
|
T34 |
214 |
| auto[1] |
5774982 |
1 |
|
|
T32 |
59351 |
|
T34 |
373 |
|
T20 |
24 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2518454 |
1 |
|
|
T32 |
25636 |
|
T34 |
87 |
|
T20 |
7 |
| auto[1] |
auto[0] |
auto[1] |
364447 |
1 |
|
|
T32 |
3675 |
|
T34 |
19 |
|
T26 |
1310 |
| auto[1] |
auto[1] |
auto[0] |
2524606 |
1 |
|
|
T32 |
26298 |
|
T34 |
210 |
|
T20 |
16 |
| auto[1] |
auto[1] |
auto[1] |
367475 |
1 |
|
|
T32 |
3742 |
|
T34 |
57 |
|
T20 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7835192 |
1 |
|
|
T32 |
74930 |
|
T33 |
1124 |
|
T34 |
348 |
| auto[1] |
5737314 |
1 |
|
|
T32 |
60805 |
|
T34 |
239 |
|
T20 |
44 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12836957 |
1 |
|
|
T32 |
128213 |
|
T33 |
1124 |
|
T34 |
538 |
| auto[1] |
735549 |
1 |
|
|
T32 |
7522 |
|
T34 |
49 |
|
T20 |
1 |