Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7842942 |
1 |
|
|
T32 |
76349 |
|
T33 |
1124 |
|
T34 |
389 |
| auto[1] |
5729564 |
1 |
|
|
T32 |
59386 |
|
T34 |
198 |
|
T20 |
46 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11186224 |
1 |
|
|
T32 |
113435 |
|
T33 |
1124 |
|
T34 |
404 |
| auto[1] |
2386282 |
1 |
|
|
T32 |
22300 |
|
T34 |
183 |
|
T20 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7804240 |
1 |
|
|
T32 |
76835 |
|
T33 |
1124 |
|
T34 |
259 |
| auto[1] |
5768266 |
1 |
|
|
T32 |
58900 |
|
T34 |
328 |
|
T20 |
17 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1700332 |
1 |
|
|
T32 |
18476 |
|
T34 |
114 |
|
T20 |
4 |
| auto[1] |
auto[0] |
auto[1] |
1199080 |
1 |
|
|
T32 |
11182 |
|
T34 |
146 |
|
T20 |
11 |
| auto[1] |
auto[1] |
auto[0] |
1681652 |
1 |
|
|
T32 |
18124 |
|
T34 |
31 |
|
T26 |
5576 |
| auto[1] |
auto[1] |
auto[1] |
1187202 |
1 |
|
|
T32 |
11118 |
|
T34 |
37 |
|
T20 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |