Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7786147 |
1 |
|
|
T32 |
76767 |
|
T33 |
1124 |
|
T34 |
350 |
| auto[1] |
5786359 |
1 |
|
|
T32 |
58968 |
|
T34 |
237 |
|
T20 |
40 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2553153 |
1 |
|
|
T32 |
26042 |
|
T34 |
103 |
|
T20 |
10 |
| auto[1] |
auto[0] |
auto[1] |
372492 |
1 |
|
|
T32 |
3838 |
|
T34 |
27 |
|
T20 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2497657 |
1 |
|
|
T32 |
25404 |
|
T34 |
85 |
|
T20 |
29 |
| auto[1] |
auto[1] |
auto[1] |
363057 |
1 |
|
|
T32 |
3684 |
|
T34 |
22 |
|
T26 |
1269 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |